2 * Copyright IBM Corporation 2001, 2005, 2006
3 * Copyright Dave Engebretsen & Todd Inglett 2001
4 * Copyright Linas Vepstas 2005, 2006
5 * Copyright 2001-2012 IBM Corporation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
24 #include <linux/delay.h>
25 #include <linux/debugfs.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
28 #include <linux/list.h>
29 #include <linux/pci.h>
30 #include <linux/iommu.h>
31 #include <linux/proc_fs.h>
32 #include <linux/rbtree.h>
33 #include <linux/reboot.h>
34 #include <linux/seq_file.h>
35 #include <linux/spinlock.h>
36 #include <linux/export.h>
39 #include <linux/atomic.h>
40 #include <asm/debug.h>
42 #include <asm/eeh_event.h>
44 #include <asm/iommu.h>
45 #include <asm/machdep.h>
46 #include <asm/ppc-pci.h>
51 * EEH, or "Extended Error Handling" is a PCI bridge technology for
52 * dealing with PCI bus errors that can't be dealt with within the
53 * usual PCI framework, except by check-stopping the CPU. Systems
54 * that are designed for high-availability/reliability cannot afford
55 * to crash due to a "mere" PCI error, thus the need for EEH.
56 * An EEH-capable bridge operates by converting a detected error
57 * into a "slot freeze", taking the PCI adapter off-line, making
58 * the slot behave, from the OS'es point of view, as if the slot
59 * were "empty": all reads return 0xff's and all writes are silently
60 * ignored. EEH slot isolation events can be triggered by parity
61 * errors on the address or data busses (e.g. during posted writes),
62 * which in turn might be caused by low voltage on the bus, dust,
63 * vibration, humidity, radioactivity or plain-old failed hardware.
65 * Note, however, that one of the leading causes of EEH slot
66 * freeze events are buggy device drivers, buggy device microcode,
67 * or buggy device hardware. This is because any attempt by the
68 * device to bus-master data to a memory address that is not
69 * assigned to the device will trigger a slot freeze. (The idea
70 * is to prevent devices-gone-wild from corrupting system memory).
71 * Buggy hardware/drivers will have a miserable time co-existing
74 * Ideally, a PCI device driver, when suspecting that an isolation
75 * event has occurred (e.g. by reading 0xff's), will then ask EEH
76 * whether this is the case, and then take appropriate steps to
77 * reset the PCI slot, the PCI device, and then resume operations.
78 * However, until that day, the checking is done here, with the
79 * eeh_check_failure() routine embedded in the MMIO macros. If
80 * the slot is found to be isolated, an "EEH Event" is synthesized
81 * and sent out for processing.
84 /* If a device driver keeps reading an MMIO register in an interrupt
85 * handler after a slot isolation event, it might be broken.
86 * This sets the threshold for how many read attempts we allow
87 * before printing an error message.
89 #define EEH_MAX_FAILS 2100000
91 /* Time to wait for a PCI slot to report status, in milliseconds */
92 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
95 * EEH probe mode support, which is part of the flags,
96 * is to support multiple platforms for EEH. Some platforms
97 * like pSeries do PCI emunation based on device tree.
98 * However, other platforms like powernv probe PCI devices
99 * from hardware. The flag is used to distinguish that.
100 * In addition, struct eeh_ops::probe would be invoked for
101 * particular OF node or PCI device so that the corresponding
102 * PE would be created there.
104 int eeh_subsystem_flags;
105 EXPORT_SYMBOL(eeh_subsystem_flags);
108 * EEH allowed maximal frozen times. If one particular PE's
109 * frozen count in last hour exceeds this limit, the PE will
110 * be forced to be offline permanently.
112 int eeh_max_freezes = 5;
114 /* Platform dependent EEH operations */
115 struct eeh_ops *eeh_ops = NULL;
117 /* Lock to avoid races due to multiple reports of an error */
118 DEFINE_RAW_SPINLOCK(confirm_error_lock);
120 /* Lock to protect passed flags */
121 static DEFINE_MUTEX(eeh_dev_mutex);
123 /* Buffer for reporting pci register dumps. Its here in BSS, and
124 * not dynamically alloced, so that it ends up in RMO where RTAS
127 #define EEH_PCI_REGS_LOG_LEN 8192
128 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
131 * The struct is used to maintain the EEH global statistic
132 * information. Besides, the EEH global statistics will be
133 * exported to user space through procfs
136 u64 no_device; /* PCI device not found */
137 u64 no_dn; /* OF node not found */
138 u64 no_cfg_addr; /* Config address not found */
139 u64 ignored_check; /* EEH check skipped */
140 u64 total_mmio_ffs; /* Total EEH checks */
141 u64 false_positives; /* Unnecessary EEH checks */
142 u64 slot_resets; /* PE reset */
145 static struct eeh_stats eeh_stats;
147 static int __init eeh_setup(char *str)
149 if (!strcmp(str, "off"))
150 eeh_add_flag(EEH_FORCE_DISABLED);
151 else if (!strcmp(str, "early_log"))
152 eeh_add_flag(EEH_EARLY_DUMP_LOG);
156 __setup("eeh=", eeh_setup);
159 * This routine captures assorted PCI configuration space data
160 * for the indicated PCI device, and puts them into a buffer
161 * for RTAS error logging.
163 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
165 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
171 n += scnprintf(buf+n, len-n, "%04x:%02x:%02x:%01x\n",
172 edev->phb->global_number, pdn->busno,
173 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
174 pr_warn("EEH: of node=%04x:%02x:%02x:%01x\n",
175 edev->phb->global_number, pdn->busno,
176 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
178 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
179 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
180 pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
182 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
183 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
184 pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
186 /* Gather bridge-specific registers */
187 if (edev->mode & EEH_DEV_BRIDGE) {
188 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
189 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
190 pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
192 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
193 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
194 pr_warn("EEH: Bridge control: %04x\n", cfg);
197 /* Dump out the PCI-X command and status regs */
198 cap = edev->pcix_cap;
200 eeh_ops->read_config(pdn, cap, 4, &cfg);
201 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
202 pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
204 eeh_ops->read_config(pdn, cap+4, 4, &cfg);
205 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
206 pr_warn("EEH: PCI-X status: %08x\n", cfg);
209 /* If PCI-E capable, dump PCI-E cap 10 */
210 cap = edev->pcie_cap;
212 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
213 pr_warn("EEH: PCI-E capabilities and status follow:\n");
215 for (i=0; i<=8; i++) {
216 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
217 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
221 pr_warn("%s\n", buffer);
223 l = scnprintf(buffer, sizeof(buffer),
224 "EEH: PCI-E %02x: %08x ",
227 l += scnprintf(buffer+l, sizeof(buffer)-l,
233 pr_warn("%s\n", buffer);
236 /* If AER capable, dump it */
239 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
240 pr_warn("EEH: PCI-E AER capability register set follows:\n");
242 for (i=0; i<=13; i++) {
243 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
244 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
248 pr_warn("%s\n", buffer);
250 l = scnprintf(buffer, sizeof(buffer),
251 "EEH: PCI-E AER %02x: %08x ",
254 l += scnprintf(buffer+l, sizeof(buffer)-l,
259 pr_warn("%s\n", buffer);
265 static void *eeh_dump_pe_log(void *data, void *flag)
267 struct eeh_pe *pe = data;
268 struct eeh_dev *edev, *tmp;
271 /* If the PE's config space is blocked, 0xFF's will be
272 * returned. It's pointless to collect the log in this
275 if (pe->state & EEH_PE_CFG_BLOCKED)
278 eeh_pe_for_each_dev(pe, edev, tmp)
279 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
280 EEH_PCI_REGS_LOG_LEN - *plen);
286 * eeh_slot_error_detail - Generate combined log including driver log and error log
288 * @severity: temporary or permanent error log
290 * This routine should be called to generate the combined log, which
291 * is comprised of driver log and error log. The driver log is figured
292 * out from the config space of the corresponding PCI device, while
293 * the error log is fetched through platform dependent function call.
295 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
300 * When the PHB is fenced or dead, it's pointless to collect
301 * the data from PCI config space because it should return
302 * 0xFF's. For ER, we still retrieve the data from the PCI
305 * For pHyp, we have to enable IO for log retrieval. Otherwise,
306 * 0xFF's is always returned from PCI config space.
308 if (!(pe->type & EEH_PE_PHB)) {
309 if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG))
310 eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
313 * The config space of some PCI devices can't be accessed
314 * when their PEs are in frozen state. Otherwise, fenced
315 * PHB might be seen. Those PEs are identified with flag
316 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
317 * is set automatically when the PE is put to EEH_PE_ISOLATED.
319 * Restoring BARs possibly triggers PCI config access in
320 * (OPAL) firmware and then causes fenced PHB. If the
321 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
322 * pointless to restore BARs and dump config space.
324 eeh_ops->configure_bridge(pe);
325 if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
326 eeh_pe_restore_bars(pe);
329 eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
333 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
337 * eeh_token_to_phys - Convert EEH address token to phys address
338 * @token: I/O token, should be address in the form 0xA....
340 * This routine should be called to convert virtual I/O address
343 static inline unsigned long eeh_token_to_phys(unsigned long token)
350 * We won't find hugepages here(this is iomem). Hence we are not
351 * worried about _PAGE_SPLITTING/collapse. Also we will not hit
352 * page table free, because of init_mm.
354 ptep = __find_linux_pte_or_hugepte(init_mm.pgd, token,
355 NULL, &hugepage_shift);
358 WARN_ON(hugepage_shift);
359 pa = pte_pfn(*ptep) << PAGE_SHIFT;
361 return pa | (token & (PAGE_SIZE-1));
365 * On PowerNV platform, we might already have fenced PHB there.
366 * For that case, it's meaningless to recover frozen PE. Intead,
367 * We have to handle fenced PHB firstly.
369 static int eeh_phb_check_failure(struct eeh_pe *pe)
371 struct eeh_pe *phb_pe;
375 if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
378 /* Find the PHB PE */
379 phb_pe = eeh_phb_pe_get(pe->phb);
381 pr_warn("%s Can't find PE for PHB#%d\n",
382 __func__, pe->phb->global_number);
386 /* If the PHB has been in problematic state */
387 eeh_serialize_lock(&flags);
388 if (phb_pe->state & EEH_PE_ISOLATED) {
393 /* Check PHB state */
394 ret = eeh_ops->get_state(phb_pe, NULL);
396 (ret == EEH_STATE_NOT_SUPPORT) ||
397 (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
398 (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
403 /* Isolate the PHB and send event */
404 eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
405 eeh_serialize_unlock(flags);
407 pr_err("EEH: PHB#%x failure detected, location: %s\n",
408 phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
410 eeh_send_failure_event(phb_pe);
414 eeh_serialize_unlock(flags);
419 * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
422 * Check for an EEH failure for the given device node. Call this
423 * routine if the result of a read was all 0xff's and you want to
424 * find out if this is due to an EEH slot freeze. This routine
425 * will query firmware for the EEH status.
427 * Returns 0 if there has not been an EEH error; otherwise returns
428 * a non-zero value and queues up a slot isolation event notification.
430 * It is safe to call this routine in an interrupt context.
432 int eeh_dev_check_failure(struct eeh_dev *edev)
435 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
439 struct eeh_pe *pe, *parent_pe, *phb_pe;
441 const char *location = NULL;
443 eeh_stats.total_mmio_ffs++;
452 dev = eeh_dev_to_pci_dev(edev);
453 pe = eeh_dev_to_pe(edev);
455 /* Access to IO BARs might get this far and still not want checking. */
457 eeh_stats.ignored_check++;
458 pr_debug("EEH: Ignored check for %s\n",
463 if (!pe->addr && !pe->config_addr) {
464 eeh_stats.no_cfg_addr++;
469 * On PowerNV platform, we might already have fenced PHB
470 * there and we need take care of that firstly.
472 ret = eeh_phb_check_failure(pe);
477 * If the PE isn't owned by us, we shouldn't check the
478 * state. Instead, let the owner handle it if the PE has
481 if (eeh_pe_passed(pe))
484 /* If we already have a pending isolation event for this
485 * slot, we know it's bad already, we don't need to check.
486 * Do this checking under a lock; as multiple PCI devices
487 * in one slot might report errors simultaneously, and we
488 * only want one error recovery routine running.
490 eeh_serialize_lock(&flags);
492 if (pe->state & EEH_PE_ISOLATED) {
494 if (pe->check_count % EEH_MAX_FAILS == 0) {
495 pdn = eeh_dev_to_pdn(edev);
497 location = of_get_property(pdn->node, "ibm,loc-code", NULL);
498 printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
499 "location=%s driver=%s pci addr=%s\n",
501 location ? location : "unknown",
502 eeh_driver_name(dev), eeh_pci_name(dev));
503 printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
504 eeh_driver_name(dev));
511 * Now test for an EEH failure. This is VERY expensive.
512 * Note that the eeh_config_addr may be a parent device
513 * in the case of a device behind a bridge, or it may be
514 * function zero of a multi-function device.
515 * In any case they must share a common PHB.
517 ret = eeh_ops->get_state(pe, NULL);
519 /* Note that config-io to empty slots may fail;
520 * they are empty when they don't have children.
521 * We will punt with the following conditions: Failure to get
522 * PE's state, EEH not support and Permanently unavailable
523 * state, PE is in good state.
526 (ret == EEH_STATE_NOT_SUPPORT) ||
527 ((ret & active_flags) == active_flags)) {
528 eeh_stats.false_positives++;
529 pe->false_positives++;
535 * It should be corner case that the parent PE has been
536 * put into frozen state as well. We should take care
539 parent_pe = pe->parent;
541 /* Hit the ceiling ? */
542 if (parent_pe->type & EEH_PE_PHB)
545 /* Frozen parent PE ? */
546 ret = eeh_ops->get_state(parent_pe, NULL);
548 (ret & active_flags) != active_flags)
551 /* Next parent level */
552 parent_pe = parent_pe->parent;
555 eeh_stats.slot_resets++;
557 /* Avoid repeated reports of this failure, including problems
558 * with other functions on this device, and functions under
561 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
562 eeh_serialize_unlock(flags);
564 /* Most EEH events are due to device driver bugs. Having
565 * a stack trace will help the device-driver authors figure
566 * out what happened. So print that out.
568 phb_pe = eeh_phb_pe_get(pe->phb);
569 pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
570 pe->phb->global_number, pe->addr);
571 pr_err("EEH: PE location: %s, PHB location: %s\n",
572 eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
575 eeh_send_failure_event(pe);
580 eeh_serialize_unlock(flags);
584 EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
587 * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
588 * @token: I/O address
590 * Check for an EEH failure at the given I/O address. Call this
591 * routine if the result of a read was all 0xff's and you want to
592 * find out if this is due to an EEH slot freeze event. This routine
593 * will query firmware for the EEH status.
595 * Note this routine is safe to call in an interrupt context.
597 int eeh_check_failure(const volatile void __iomem *token)
600 struct eeh_dev *edev;
602 /* Finding the phys addr + pci device; this is pretty quick. */
603 addr = eeh_token_to_phys((unsigned long __force) token);
604 edev = eeh_addr_cache_get_dev(addr);
606 eeh_stats.no_device++;
610 return eeh_dev_check_failure(edev);
612 EXPORT_SYMBOL(eeh_check_failure);
616 * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
619 * This routine should be called to reenable frozen MMIO or DMA
620 * so that it would work correctly again. It's useful while doing
621 * recovery or log collection on the indicated device.
623 int eeh_pci_enable(struct eeh_pe *pe, int function)
628 * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
629 * Also, it's pointless to enable them on unfrozen PE. So
630 * we have to check before enabling IO or DMA.
633 case EEH_OPT_THAW_MMIO:
634 active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
636 case EEH_OPT_THAW_DMA:
637 active_flag = EEH_STATE_DMA_ACTIVE;
639 case EEH_OPT_DISABLE:
641 case EEH_OPT_FREEZE_PE:
645 pr_warn("%s: Invalid function %d\n",
651 * Check if IO or DMA has been enabled before
655 rc = eeh_ops->get_state(pe, NULL);
659 /* Needn't enable it at all */
660 if (rc == EEH_STATE_NOT_SUPPORT)
663 /* It's already enabled */
664 if (rc & active_flag)
669 /* Issue the request */
670 rc = eeh_ops->set_option(pe, function);
672 pr_warn("%s: Unexpected state change %d on "
673 "PHB#%d-PE#%x, err=%d\n",
674 __func__, function, pe->phb->global_number,
677 /* Check if the request is finished successfully */
679 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
683 if (rc & active_flag)
692 static void *eeh_disable_and_save_dev_state(void *data, void *userdata)
694 struct eeh_dev *edev = data;
695 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
696 struct pci_dev *dev = userdata;
699 * The caller should have disabled and saved the
700 * state for the specified device
702 if (!pdev || pdev == dev)
705 /* Ensure we have D0 power state */
706 pci_set_power_state(pdev, PCI_D0);
708 /* Save device state */
709 pci_save_state(pdev);
712 * Disable device to avoid any DMA traffic and
713 * interrupt from the device
715 pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
720 static void *eeh_restore_dev_state(void *data, void *userdata)
722 struct eeh_dev *edev = data;
723 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
724 struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
725 struct pci_dev *dev = userdata;
730 /* Apply customization from firmware */
731 if (pdn && eeh_ops->restore_config)
732 eeh_ops->restore_config(pdn);
734 /* The caller should restore state for the specified device */
736 pci_restore_state(pdev);
742 * pcibios_set_pcie_reset_state - Set PCI-E reset state
743 * @dev: pci device struct
744 * @state: reset state to enter
749 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
751 struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
752 struct eeh_pe *pe = eeh_dev_to_pe(edev);
755 pr_err("%s: No PE found on PCI device %s\n",
756 __func__, pci_name(dev));
761 case pcie_deassert_reset:
762 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
763 eeh_unfreeze_pe(pe, false);
764 if (!(pe->type & EEH_PE_VF))
765 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
766 eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
767 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
770 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
771 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
772 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
773 if (!(pe->type & EEH_PE_VF))
774 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
775 eeh_ops->reset(pe, EEH_RESET_HOT);
777 case pcie_warm_reset:
778 eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
779 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
780 eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
781 if (!(pe->type & EEH_PE_VF))
782 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
783 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
786 eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);
794 * eeh_set_pe_freset - Check the required reset for the indicated device
796 * @flag: return value
798 * Each device might have its preferred reset type: fundamental or
799 * hot reset. The routine is used to collected the information for
800 * the indicated device and its children so that the bunch of the
801 * devices could be reset properly.
803 static void *eeh_set_dev_freset(void *data, void *flag)
806 unsigned int *freset = (unsigned int *)flag;
807 struct eeh_dev *edev = (struct eeh_dev *)data;
809 dev = eeh_dev_to_pci_dev(edev);
811 *freset |= dev->needs_freset;
817 * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
820 * Assert the PCI #RST line for 1/4 second.
822 static void eeh_reset_pe_once(struct eeh_pe *pe)
824 unsigned int freset = 0;
826 /* Determine type of EEH reset required for
827 * Partitionable Endpoint, a hot-reset (1)
828 * or a fundamental reset (3).
829 * A fundamental reset required by any device under
830 * Partitionable Endpoint trumps hot-reset.
832 eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
835 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
837 eeh_ops->reset(pe, EEH_RESET_HOT);
839 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
843 * eeh_reset_pe - Reset the indicated PE
846 * This routine should be called to reset indicated device, including
847 * PE. A PE might include multiple PCI devices and sometimes PCI bridges
848 * might be involved as well.
850 int eeh_reset_pe(struct eeh_pe *pe)
852 int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
855 /* Mark as reset and block config space */
856 eeh_pe_state_mark(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
858 /* Take three shots at resetting the bus */
859 for (i = 0; i < 3; i++) {
860 eeh_reset_pe_once(pe);
863 * EEH_PE_ISOLATED is expected to be removed after
866 state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
867 if ((state & flags) == flags) {
873 pr_warn("%s: Unrecoverable slot failure on PHB#%d-PE#%x",
874 __func__, pe->phb->global_number, pe->addr);
875 ret = -ENOTRECOVERABLE;
879 /* We might run out of credits */
881 pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n",
882 __func__, state, pe->phb->global_number, pe->addr, (i + 1));
886 eeh_pe_state_clear(pe, EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
891 * eeh_save_bars - Save device bars
892 * @edev: PCI device associated EEH device
894 * Save the values of the device bars. Unlike the restore
895 * routine, this routine is *not* recursive. This is because
896 * PCI devices are added individually; but, for the restore,
897 * an entire slot is reset at a time.
899 void eeh_save_bars(struct eeh_dev *edev)
904 pdn = eeh_dev_to_pdn(edev);
908 for (i = 0; i < 16; i++)
909 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
912 * For PCI bridges including root port, we need enable bus
913 * master explicitly. Otherwise, it can't fetch IODA table
914 * entries correctly. So we cache the bit in advance so that
915 * we can restore it after reset, either PHB range or PE range.
917 if (edev->mode & EEH_DEV_BRIDGE)
918 edev->config_space[1] |= PCI_COMMAND_MASTER;
922 * eeh_ops_register - Register platform dependent EEH operations
923 * @ops: platform dependent EEH operations
925 * Register the platform dependent EEH operation callback
926 * functions. The platform should call this function before
927 * any other EEH operations.
929 int __init eeh_ops_register(struct eeh_ops *ops)
932 pr_warn("%s: Invalid EEH ops name for %p\n",
937 if (eeh_ops && eeh_ops != ops) {
938 pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
939 __func__, eeh_ops->name, ops->name);
949 * eeh_ops_unregister - Unreigster platform dependent EEH operations
950 * @name: name of EEH platform operations
952 * Unregister the platform dependent EEH operation callback
955 int __exit eeh_ops_unregister(const char *name)
957 if (!name || !strlen(name)) {
958 pr_warn("%s: Invalid EEH ops name\n",
963 if (eeh_ops && !strcmp(eeh_ops->name, name)) {
971 static int eeh_reboot_notifier(struct notifier_block *nb,
972 unsigned long action, void *unused)
974 eeh_clear_flag(EEH_ENABLED);
978 static struct notifier_block eeh_reboot_nb = {
979 .notifier_call = eeh_reboot_notifier,
983 * eeh_init - EEH initialization
985 * Initialize EEH by trying to enable it for all of the adapters in the system.
986 * As a side effect we can determine here if eeh is supported at all.
987 * Note that we leave EEH on so failed config cycles won't cause a machine
988 * check. If a user turns off EEH for a particular adapter they are really
989 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
990 * grant access to a slot if EEH isn't enabled, and so we always enable
991 * EEH for all slots/all devices.
993 * The eeh-force-off option disables EEH checking globally, for all slots.
994 * Even if force-off is set, the EEH hardware is still enabled, so that
995 * newer systems can boot.
999 struct pci_controller *hose, *tmp;
1005 * We have to delay the initialization on PowerNV after
1006 * the PCI hierarchy tree has been built because the PEs
1007 * are figured out based on PCI devices instead of device
1010 if (machine_is(powernv) && cnt++ <= 0)
1013 /* Register reboot notifier */
1014 ret = register_reboot_notifier(&eeh_reboot_nb);
1016 pr_warn("%s: Failed to register notifier (%d)\n",
1021 /* call platform initialization function */
1023 pr_warn("%s: Platform EEH operation not found\n",
1026 } else if ((ret = eeh_ops->init()))
1029 /* Initialize EEH event */
1030 ret = eeh_event_init();
1034 /* Enable EEH for all adapters */
1035 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1036 pdn = hose->pci_data;
1037 traverse_pci_dn(pdn, eeh_ops->probe, NULL);
1041 * Call platform post-initialization. Actually, It's good chance
1042 * to inform platform that EEH is ready to supply service if the
1043 * I/O cache stuff has been built up.
1045 if (eeh_ops->post_init) {
1046 ret = eeh_ops->post_init();
1052 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
1054 pr_warn("EEH: No capable adapters found\n");
1059 core_initcall_sync(eeh_init);
1062 * eeh_add_device_early - Enable EEH for the indicated device node
1063 * @pdn: PCI device node for which to set up EEH
1065 * This routine must be used to perform EEH initialization for PCI
1066 * devices that were added after system boot (e.g. hotplug, dlpar).
1067 * This routine must be called before any i/o is performed to the
1068 * adapter (inluding any config-space i/o).
1069 * Whether this actually enables EEH or not for this device depends
1070 * on the CEC architecture, type of the device, on earlier boot
1071 * command-line arguments & etc.
1073 void eeh_add_device_early(struct pci_dn *pdn)
1075 struct pci_controller *phb;
1076 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1078 if (!edev || !eeh_enabled())
1081 if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
1084 /* USB Bus children of PCI devices will not have BUID's */
1087 (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
1090 eeh_ops->probe(pdn, NULL);
1094 * eeh_add_device_tree_early - Enable EEH for the indicated device
1095 * @pdn: PCI device node
1097 * This routine must be used to perform EEH initialization for the
1098 * indicated PCI device that was added after system boot (e.g.
1101 void eeh_add_device_tree_early(struct pci_dn *pdn)
1108 list_for_each_entry(n, &pdn->child_list, list)
1109 eeh_add_device_tree_early(n);
1110 eeh_add_device_early(pdn);
1112 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1115 * eeh_add_device_late - Perform EEH initialization for the indicated pci device
1116 * @dev: pci device for which to set up EEH
1118 * This routine must be used to complete EEH initialization for PCI
1119 * devices that were added after system boot (e.g. hotplug, dlpar).
1121 void eeh_add_device_late(struct pci_dev *dev)
1124 struct eeh_dev *edev;
1126 if (!dev || !eeh_enabled())
1129 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1131 pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
1132 edev = pdn_to_eeh_dev(pdn);
1133 if (edev->pdev == dev) {
1134 pr_debug("EEH: Already referenced !\n");
1139 * The EEH cache might not be removed correctly because of
1140 * unbalanced kref to the device during unplug time, which
1141 * relies on pcibios_release_device(). So we have to remove
1142 * that here explicitly.
1145 eeh_rmv_from_parent_pe(edev);
1146 eeh_addr_cache_rmv_dev(edev->pdev);
1147 eeh_sysfs_remove_device(edev->pdev);
1148 edev->mode &= ~EEH_DEV_SYSFS;
1151 * We definitely should have the PCI device removed
1152 * though it wasn't correctly. So we needn't call
1153 * into error handler afterwards.
1155 edev->mode |= EEH_DEV_NO_HANDLER;
1158 dev->dev.archdata.edev = NULL;
1161 if (eeh_has_flag(EEH_PROBE_MODE_DEV))
1162 eeh_ops->probe(pdn, NULL);
1165 dev->dev.archdata.edev = edev;
1167 eeh_addr_cache_insert_dev(dev);
1171 * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
1174 * This routine must be used to perform EEH initialization for PCI
1175 * devices which are attached to the indicated PCI bus. The PCI bus
1176 * is added after system boot through hotplug or dlpar.
1178 void eeh_add_device_tree_late(struct pci_bus *bus)
1180 struct pci_dev *dev;
1182 list_for_each_entry(dev, &bus->devices, bus_list) {
1183 eeh_add_device_late(dev);
1184 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1185 struct pci_bus *subbus = dev->subordinate;
1187 eeh_add_device_tree_late(subbus);
1191 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1194 * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
1197 * This routine must be used to add EEH sysfs files for PCI
1198 * devices which are attached to the indicated PCI bus. The PCI bus
1199 * is added after system boot through hotplug or dlpar.
1201 void eeh_add_sysfs_files(struct pci_bus *bus)
1203 struct pci_dev *dev;
1205 list_for_each_entry(dev, &bus->devices, bus_list) {
1206 eeh_sysfs_add_device(dev);
1207 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1208 struct pci_bus *subbus = dev->subordinate;
1210 eeh_add_sysfs_files(subbus);
1214 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
1217 * eeh_remove_device - Undo EEH setup for the indicated pci device
1218 * @dev: pci device to be removed
1220 * This routine should be called when a device is removed from
1221 * a running system (e.g. by hotplug or dlpar). It unregisters
1222 * the PCI device from the EEH subsystem. I/O errors affecting
1223 * this device will no longer be detected after this call; thus,
1224 * i/o errors affecting this slot may leave this device unusable.
1226 void eeh_remove_device(struct pci_dev *dev)
1228 struct eeh_dev *edev;
1230 if (!dev || !eeh_enabled())
1232 edev = pci_dev_to_eeh_dev(dev);
1234 /* Unregister the device with the EEH/PCI address search system */
1235 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1237 if (!edev || !edev->pdev || !edev->pe) {
1238 pr_debug("EEH: Not referenced !\n");
1243 * During the hotplug for EEH error recovery, we need the EEH
1244 * device attached to the parent PE in order for BAR restore
1245 * a bit later. So we keep it for BAR restore and remove it
1246 * from the parent PE during the BAR resotre.
1249 dev->dev.archdata.edev = NULL;
1250 if (!(edev->pe->state & EEH_PE_KEEP))
1251 eeh_rmv_from_parent_pe(edev);
1253 edev->mode |= EEH_DEV_DISCONNECTED;
1256 * We're removing from the PCI subsystem, that means
1257 * the PCI device driver can't support EEH or not
1258 * well. So we rely on hotplug completely to do recovery
1259 * for the specific PCI device.
1261 edev->mode |= EEH_DEV_NO_HANDLER;
1263 eeh_addr_cache_rmv_dev(dev);
1264 eeh_sysfs_remove_device(dev);
1265 edev->mode &= ~EEH_DEV_SYSFS;
1268 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)
1272 ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1274 pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
1275 __func__, ret, pe->phb->global_number, pe->addr);
1279 ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1281 pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
1282 __func__, ret, pe->phb->global_number, pe->addr);
1286 /* Clear software isolated state */
1287 if (sw_state && (pe->state & EEH_PE_ISOLATED))
1288 eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
1294 static struct pci_device_id eeh_reset_ids[] = {
1295 { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
1296 { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
1297 { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
1301 static int eeh_pe_change_owner(struct eeh_pe *pe)
1303 struct eeh_dev *edev, *tmp;
1304 struct pci_dev *pdev;
1305 struct pci_device_id *id;
1308 /* Check PE state */
1309 flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1310 ret = eeh_ops->get_state(pe, NULL);
1311 if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
1314 /* Unfrozen PE, nothing to do */
1315 if ((ret & flags) == flags)
1318 /* Frozen PE, check if it needs PE level reset */
1319 eeh_pe_for_each_dev(pe, edev, tmp) {
1320 pdev = eeh_dev_to_pci_dev(edev);
1324 for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
1325 if (id->vendor != PCI_ANY_ID &&
1326 id->vendor != pdev->vendor)
1328 if (id->device != PCI_ANY_ID &&
1329 id->device != pdev->device)
1331 if (id->subvendor != PCI_ANY_ID &&
1332 id->subvendor != pdev->subsystem_vendor)
1334 if (id->subdevice != PCI_ANY_ID &&
1335 id->subdevice != pdev->subsystem_device)
1342 return eeh_unfreeze_pe(pe, true);
1345 return eeh_pe_reset_and_recover(pe);
1349 * eeh_dev_open - Increase count of pass through devices for PE
1352 * Increase count of passed through devices for the indicated
1353 * PE. In the result, the EEH errors detected on the PE won't be
1354 * reported. The PE owner will be responsible for detection
1357 int eeh_dev_open(struct pci_dev *pdev)
1359 struct eeh_dev *edev;
1362 mutex_lock(&eeh_dev_mutex);
1364 /* No PCI device ? */
1368 /* No EEH device or PE ? */
1369 edev = pci_dev_to_eeh_dev(pdev);
1370 if (!edev || !edev->pe)
1374 * The PE might have been put into frozen state, but we
1375 * didn't detect that yet. The passed through PCI devices
1376 * in frozen PE won't work properly. Clear the frozen state
1379 ret = eeh_pe_change_owner(edev->pe);
1383 /* Increase PE's pass through count */
1384 atomic_inc(&edev->pe->pass_dev_cnt);
1385 mutex_unlock(&eeh_dev_mutex);
1389 mutex_unlock(&eeh_dev_mutex);
1392 EXPORT_SYMBOL_GPL(eeh_dev_open);
1395 * eeh_dev_release - Decrease count of pass through devices for PE
1398 * Decrease count of pass through devices for the indicated PE. If
1399 * there is no passed through device in PE, the EEH errors detected
1400 * on the PE will be reported and handled as usual.
1402 void eeh_dev_release(struct pci_dev *pdev)
1404 struct eeh_dev *edev;
1406 mutex_lock(&eeh_dev_mutex);
1408 /* No PCI device ? */
1412 /* No EEH device ? */
1413 edev = pci_dev_to_eeh_dev(pdev);
1414 if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1417 /* Decrease PE's pass through count */
1418 WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1419 eeh_pe_change_owner(edev->pe);
1421 mutex_unlock(&eeh_dev_mutex);
1423 EXPORT_SYMBOL(eeh_dev_release);
1425 #ifdef CONFIG_IOMMU_API
1427 static int dev_has_iommu_table(struct device *dev, void *data)
1429 struct pci_dev *pdev = to_pci_dev(dev);
1430 struct pci_dev **ppdev = data;
1435 if (dev->iommu_group) {
1444 * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
1445 * @group: IOMMU group
1447 * The routine is called to convert IOMMU group to EEH PE.
1449 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
1451 struct pci_dev *pdev = NULL;
1452 struct eeh_dev *edev;
1455 /* No IOMMU group ? */
1459 ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
1463 /* No EEH device or PE ? */
1464 edev = pci_dev_to_eeh_dev(pdev);
1465 if (!edev || !edev->pe)
1470 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
1472 #endif /* CONFIG_IOMMU_API */
1475 * eeh_pe_set_option - Set options for the indicated PE
1477 * @option: requested option
1479 * The routine is called to enable or disable EEH functionality
1480 * on the indicated PE, to enable IO or DMA for the frozen PE.
1482 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1491 * EEH functionality could possibly be disabled, just
1492 * return error for the case. And the EEH functinality
1493 * isn't expected to be disabled on one specific PE.
1496 case EEH_OPT_ENABLE:
1497 if (eeh_enabled()) {
1498 ret = eeh_pe_change_owner(pe);
1503 case EEH_OPT_DISABLE:
1505 case EEH_OPT_THAW_MMIO:
1506 case EEH_OPT_THAW_DMA:
1507 if (!eeh_ops || !eeh_ops->set_option) {
1512 ret = eeh_pci_enable(pe, option);
1515 pr_debug("%s: Option %d out of range (%d, %d)\n",
1516 __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
1522 EXPORT_SYMBOL_GPL(eeh_pe_set_option);
1525 * eeh_pe_get_state - Retrieve PE's state
1528 * Retrieve the PE's state, which includes 3 aspects: enabled
1529 * DMA, enabled IO and asserted reset.
1531 int eeh_pe_get_state(struct eeh_pe *pe)
1533 int result, ret = 0;
1534 bool rst_active, dma_en, mmio_en;
1540 if (!eeh_ops || !eeh_ops->get_state)
1543 result = eeh_ops->get_state(pe, NULL);
1544 rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
1545 dma_en = !!(result & EEH_STATE_DMA_ENABLED);
1546 mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
1549 ret = EEH_PE_STATE_RESET;
1550 else if (dma_en && mmio_en)
1551 ret = EEH_PE_STATE_NORMAL;
1552 else if (!dma_en && !mmio_en)
1553 ret = EEH_PE_STATE_STOPPED_IO_DMA;
1554 else if (!dma_en && mmio_en)
1555 ret = EEH_PE_STATE_STOPPED_DMA;
1557 ret = EEH_PE_STATE_UNAVAIL;
1561 EXPORT_SYMBOL_GPL(eeh_pe_get_state);
1563 static int eeh_pe_reenable_devices(struct eeh_pe *pe)
1565 struct eeh_dev *edev, *tmp;
1566 struct pci_dev *pdev;
1569 /* Restore config space */
1570 eeh_pe_restore_bars(pe);
1573 * Reenable PCI devices as the devices passed
1574 * through are always enabled before the reset.
1576 eeh_pe_for_each_dev(pe, edev, tmp) {
1577 pdev = eeh_dev_to_pci_dev(edev);
1581 ret = pci_reenable_device(pdev);
1583 pr_warn("%s: Failure %d reenabling %s\n",
1584 __func__, ret, pci_name(pdev));
1589 /* The PE is still in frozen state */
1590 return eeh_unfreeze_pe(pe, true);
1594 * eeh_pe_reset - Issue PE reset according to specified type
1596 * @option: reset type
1598 * The routine is called to reset the specified PE with the
1599 * indicated type, either fundamental reset or hot reset.
1600 * PE reset is the most important part for error recovery.
1602 int eeh_pe_reset(struct eeh_pe *pe, int option)
1610 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
1614 case EEH_RESET_DEACTIVATE:
1615 ret = eeh_ops->reset(pe, option);
1616 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
1620 ret = eeh_pe_reenable_devices(pe);
1623 case EEH_RESET_FUNDAMENTAL:
1625 * Proactively freeze the PE to drop all MMIO access
1626 * during reset, which should be banned as it's always
1627 * cause recursive EEH error.
1629 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1631 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1632 ret = eeh_ops->reset(pe, option);
1635 pr_debug("%s: Unsupported option %d\n",
1642 EXPORT_SYMBOL_GPL(eeh_pe_reset);
1645 * eeh_pe_configure - Configure PCI bridges after PE reset
1648 * The routine is called to restore the PCI config space for
1649 * those PCI devices, especially PCI bridges affected by PE
1650 * reset issued previously.
1652 int eeh_pe_configure(struct eeh_pe *pe)
1662 EXPORT_SYMBOL_GPL(eeh_pe_configure);
1665 * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
1666 * @pe: the indicated PE
1668 * @function: error function
1670 * @mask: address mask
1672 * The routine is called to inject the specified PCI error, which
1673 * is determined by @type and @function, to the indicated PE for
1676 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1677 unsigned long addr, unsigned long mask)
1683 /* Unsupported operation ? */
1684 if (!eeh_ops || !eeh_ops->err_inject)
1687 /* Check on PCI error type */
1688 if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
1691 /* Check on PCI error function */
1692 if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
1695 return eeh_ops->err_inject(pe, type, func, addr, mask);
1697 EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
1699 static int proc_eeh_show(struct seq_file *m, void *v)
1701 if (!eeh_enabled()) {
1702 seq_printf(m, "EEH Subsystem is globally disabled\n");
1703 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
1705 seq_printf(m, "EEH Subsystem is enabled\n");
1708 "no device node=%llu\n"
1709 "no config address=%llu\n"
1710 "check not wanted=%llu\n"
1711 "eeh_total_mmio_ffs=%llu\n"
1712 "eeh_false_positives=%llu\n"
1713 "eeh_slot_resets=%llu\n",
1714 eeh_stats.no_device,
1716 eeh_stats.no_cfg_addr,
1717 eeh_stats.ignored_check,
1718 eeh_stats.total_mmio_ffs,
1719 eeh_stats.false_positives,
1720 eeh_stats.slot_resets);
1726 static int proc_eeh_open(struct inode *inode, struct file *file)
1728 return single_open(file, proc_eeh_show, NULL);
1731 static const struct file_operations proc_eeh_operations = {
1732 .open = proc_eeh_open,
1734 .llseek = seq_lseek,
1735 .release = single_release,
1738 #ifdef CONFIG_DEBUG_FS
1739 static int eeh_enable_dbgfs_set(void *data, u64 val)
1742 eeh_clear_flag(EEH_FORCE_DISABLED);
1744 eeh_add_flag(EEH_FORCE_DISABLED);
1746 /* Notify the backend */
1747 if (eeh_ops->post_init)
1748 eeh_ops->post_init();
1753 static int eeh_enable_dbgfs_get(void *data, u64 *val)
1762 static int eeh_freeze_dbgfs_set(void *data, u64 val)
1764 eeh_max_freezes = val;
1768 static int eeh_freeze_dbgfs_get(void *data, u64 *val)
1770 *val = eeh_max_freezes;
1774 DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
1775 eeh_enable_dbgfs_set, "0x%llx\n");
1776 DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
1777 eeh_freeze_dbgfs_set, "0x%llx\n");
1780 static int __init eeh_init_proc(void)
1782 if (machine_is(pseries) || machine_is(powernv)) {
1783 proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
1784 #ifdef CONFIG_DEBUG_FS
1785 debugfs_create_file("eeh_enable", 0600,
1786 powerpc_debugfs_root, NULL,
1787 &eeh_enable_dbgfs_ops);
1788 debugfs_create_file("eeh_max_freezes", 0600,
1789 powerpc_debugfs_root, NULL,
1790 &eeh_freeze_dbgfs_ops);
1796 __initcall(eeh_init_proc);