1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2009 Freescale Semiconductor, Inc.
5 * provides masks and opcode images for use by code generation, emulation
6 * and for instructions that older assemblers might not know about
8 #ifndef _ASM_POWERPC_PPC_OPCODE_H
9 #define _ASM_POWERPC_PPC_OPCODE_H
11 #include <asm/asm-const.h>
56 #define __REGA0_R10 10
57 #define __REGA0_R11 11
58 #define __REGA0_R12 12
59 #define __REGA0_R13 13
60 #define __REGA0_R14 14
61 #define __REGA0_R15 15
62 #define __REGA0_R16 16
63 #define __REGA0_R17 17
64 #define __REGA0_R18 18
65 #define __REGA0_R19 19
66 #define __REGA0_R20 20
67 #define __REGA0_R21 21
68 #define __REGA0_R22 22
69 #define __REGA0_R23 23
70 #define __REGA0_R24 24
71 #define __REGA0_R25 25
72 #define __REGA0_R26 26
73 #define __REGA0_R27 27
74 #define __REGA0_R28 28
75 #define __REGA0_R29 29
76 #define __REGA0_R30 30
77 #define __REGA0_R31 31
79 #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
80 #define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
83 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
84 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
85 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
87 #define IMM_H(i) ((uintptr_t)(i)>>16)
88 #define IMM_HA(i) (((uintptr_t)(i)>>16) + \
89 (((uintptr_t)(i) & 0x8000) >> 15))
92 /* opcode and xopcode for instructions */
96 #define OP_31_XOP_TRAP 4
97 #define OP_31_XOP_LDX 21
98 #define OP_31_XOP_LWZX 23
99 #define OP_31_XOP_LDUX 53
100 #define OP_31_XOP_DCBST 54
101 #define OP_31_XOP_LWZUX 55
102 #define OP_31_XOP_TRAP_64 68
103 #define OP_31_XOP_DCBF 86
104 #define OP_31_XOP_LBZX 87
105 #define OP_31_XOP_STDX 149
106 #define OP_31_XOP_STWX 151
107 #define OP_31_XOP_STDUX 181
108 #define OP_31_XOP_STWUX 183
109 #define OP_31_XOP_STBX 215
110 #define OP_31_XOP_LBZUX 119
111 #define OP_31_XOP_STBUX 247
112 #define OP_31_XOP_LHZX 279
113 #define OP_31_XOP_LHZUX 311
114 #define OP_31_XOP_MSGSNDP 142
115 #define OP_31_XOP_MSGCLRP 174
116 #define OP_31_XOP_TLBIE 306
117 #define OP_31_XOP_MFSPR 339
118 #define OP_31_XOP_LWAX 341
119 #define OP_31_XOP_LHAX 343
120 #define OP_31_XOP_LWAUX 373
121 #define OP_31_XOP_LHAUX 375
122 #define OP_31_XOP_STHX 407
123 #define OP_31_XOP_STHUX 439
124 #define OP_31_XOP_MTSPR 467
125 #define OP_31_XOP_DCBI 470
126 #define OP_31_XOP_LDBRX 532
127 #define OP_31_XOP_LWBRX 534
128 #define OP_31_XOP_TLBSYNC 566
129 #define OP_31_XOP_STDBRX 660
130 #define OP_31_XOP_STWBRX 662
131 #define OP_31_XOP_STFSX 663
132 #define OP_31_XOP_STFSUX 695
133 #define OP_31_XOP_STFDX 727
134 #define OP_31_XOP_STFDUX 759
135 #define OP_31_XOP_LHBRX 790
136 #define OP_31_XOP_LFIWAX 855
137 #define OP_31_XOP_LFIWZX 887
138 #define OP_31_XOP_STHBRX 918
139 #define OP_31_XOP_STFIWX 983
141 /* VSX Scalar Load Instructions */
142 #define OP_31_XOP_LXSDX 588
143 #define OP_31_XOP_LXSSPX 524
144 #define OP_31_XOP_LXSIWAX 76
145 #define OP_31_XOP_LXSIWZX 12
147 /* VSX Scalar Store Instructions */
148 #define OP_31_XOP_STXSDX 716
149 #define OP_31_XOP_STXSSPX 652
150 #define OP_31_XOP_STXSIWX 140
152 /* VSX Vector Load Instructions */
153 #define OP_31_XOP_LXVD2X 844
154 #define OP_31_XOP_LXVW4X 780
156 /* VSX Vector Load and Splat Instruction */
157 #define OP_31_XOP_LXVDSX 332
159 /* VSX Vector Store Instructions */
160 #define OP_31_XOP_STXVD2X 972
161 #define OP_31_XOP_STXVW4X 908
163 #define OP_31_XOP_LFSX 535
164 #define OP_31_XOP_LFSUX 567
165 #define OP_31_XOP_LFDX 599
166 #define OP_31_XOP_LFDUX 631
168 /* VMX Vector Load Instructions */
169 #define OP_31_XOP_LVX 103
171 /* VMX Vector Store Instructions */
172 #define OP_31_XOP_STVX 231
174 /* Prefixed Instructions */
210 /* sorted alphabetically */
211 #define PPC_INST_BCCTR_FLUSH 0x4c400420
212 #define PPC_INST_COPY 0x7c20060c
213 #define PPC_INST_DCBA 0x7c0005ec
214 #define PPC_INST_DCBA_MASK 0xfc0007fe
215 #define PPC_INST_ISEL 0x7c00001e
216 #define PPC_INST_ISEL_MASK 0xfc00003e
217 #define PPC_INST_LSWI 0x7c0004aa
218 #define PPC_INST_LSWX 0x7c00042a
219 #define PPC_INST_LWSYNC 0x7c2004ac
220 #define PPC_INST_SYNC 0x7c0004ac
221 #define PPC_INST_SYNC_MASK 0xfc0007fe
222 #define PPC_INST_ISYNC 0x4c00012c
223 #define PPC_INST_MCRXR 0x7c000400
224 #define PPC_INST_MCRXR_MASK 0xfc0007fe
225 #define PPC_INST_MFSPR_PVR 0x7c1f42a6
226 #define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
227 #define PPC_INST_MTMSRD 0x7c000164
228 #define PPC_INST_NOP 0x60000000
229 #define PPC_INST_POPCNTB 0x7c0000f4
230 #define PPC_INST_POPCNTB_MASK 0xfc0007fe
231 #define PPC_INST_RFEBB 0x4c000124
232 #define PPC_INST_RFID 0x4c000024
233 #define PPC_INST_MFSPR 0x7c0002a6
234 #define PPC_INST_MFSPR_DSCR 0x7c1102a6
235 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
236 #define PPC_INST_MTSPR_DSCR 0x7c1103a6
237 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
238 #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
239 #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
240 #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
241 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
242 #define PPC_INST_SC 0x44000002
243 #define PPC_INST_STRING 0x7c00042a
244 #define PPC_INST_STRING_MASK 0xfc0007fe
245 #define PPC_INST_STRING_GEN_MASK 0xfc00067e
246 #define PPC_INST_STSWI 0x7c0005aa
247 #define PPC_INST_STSWX 0x7c00052a
248 #define PPC_INST_TRECHKPT 0x7c0007dd
249 #define PPC_INST_TRECLAIM 0x7c00075d
250 #define PPC_INST_TSR 0x7c0005dd
251 #define PPC_INST_LD 0xe8000000
252 #define PPC_INST_STD 0xf8000000
253 #define PPC_INST_MFLR 0x7c0802a6
254 #define PPC_INST_MTCTR 0x7c0903a6
255 #define PPC_INST_ADDI 0x38000000
256 #define PPC_INST_ADDIS 0x3c000000
257 #define PPC_INST_ADD 0x7c000214
258 #define PPC_INST_BLR 0x4e800020
259 #define PPC_INST_BCTR 0x4e800420
260 #define PPC_INST_BCTRL 0x4e800421
261 #define PPC_INST_DIVD 0x7c0003d2
262 #define PPC_INST_RLDICR 0x78000004
263 #define PPC_INST_ORI 0x60000000
264 #define PPC_INST_ORIS 0x64000000
265 #define PPC_INST_BRANCH 0x48000000
266 #define PPC_INST_BRANCH_COND 0x40800000
269 #define PPC_INST_LFS 0xc0000000
270 #define PPC_INST_STFS 0xd0000000
271 #define PPC_INST_LFD 0xc8000000
272 #define PPC_INST_STFD 0xd8000000
273 #define PPC_PREFIX_MLS 0x06000000
274 #define PPC_PREFIX_8LS 0x04000000
276 /* Prefixed instructions */
277 #define PPC_INST_PLD 0xe4000000
278 #define PPC_INST_PSTD 0xf4000000
280 /* macros to insert fields into opcodes */
281 #define ___PPC_RA(a) (((a) & 0x1f) << 16)
282 #define ___PPC_RB(b) (((b) & 0x1f) << 11)
283 #define ___PPC_RC(c) (((c) & 0x1f) << 6)
284 #define ___PPC_RS(s) (((s) & 0x1f) << 21)
285 #define ___PPC_RT(t) ___PPC_RS(t)
286 #define ___PPC_R(r) (((r) & 0x1) << 16)
287 #define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
288 #define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
289 #define __PPC_RA(a) ___PPC_RA(__REG_##a)
290 #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
291 #define __PPC_RB(b) ___PPC_RB(__REG_##b)
292 #define __PPC_RS(s) ___PPC_RS(__REG_##s)
293 #define __PPC_RT(t) ___PPC_RT(__REG_##t)
294 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
295 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
296 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
297 #define __PPC_XT(s) __PPC_XS(s)
298 #define __PPC_T_TLB(t) (((t) & 0x3) << 21)
299 #define __PPC_WC(w) (((w) & 0x3) << 21)
300 #define __PPC_WS(w) (((w) & 0x1f) << 11)
301 #define __PPC_SH(s) __PPC_WS(s)
302 #define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
303 #define __PPC_MB(s) ___PPC_RC(s)
304 #define __PPC_ME(s) (((s) & 0x1f) << 1)
305 #define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
306 #define __PPC_ME64(s) __PPC_MB64(s)
307 #define __PPC_BI(s) (((s) & 0x1f) << 16)
308 #define __PPC_CT(t) (((t) & 0x0f) << 21)
309 #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
310 #define __PPC_RC21 (0x1 << 10)
311 #define __PPC_PRFX_R(r) (((r) & 0x1) << 20)
314 * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
315 * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
318 #define PPC_LO(v) ((v) & 0xffff)
319 #define PPC_HI(v) (((v) >> 16) & 0xffff)
320 #define PPC_HA(v) PPC_HI((v) + 0x8000)
323 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
324 * larx with EH set as an illegal instruction.
327 #define __PPC_EH(eh) (((eh) & 0x1) << 0)
329 #define __PPC_EH(eh) 0
332 /* Base instruction encoding */
333 #define PPC_RAW_CP_ABORT (0x7c00068c)
334 #define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
335 #define PPC_RAW_DARN(t, l) (0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
336 #define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
337 #define PPC_RAW_DCBZL(a, b) (0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
338 #define PPC_RAW_LQARX(t, a, b, eh) (0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
339 #define PPC_RAW_LDARX(t, a, b, eh) (0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
340 #define PPC_RAW_LWARX(t, a, b, eh) (0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
341 #define PPC_RAW_PHWSYNC (0x7c8004ac)
342 #define PPC_RAW_PLWSYNC (0x7ca004ac)
343 #define PPC_RAW_STQCX(t, a, b) (0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
344 #define PPC_RAW_MADDHD(t, a, b, c) (0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
345 #define PPC_RAW_MADDHDU(t, a, b, c) (0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
346 #define PPC_RAW_MADDLD(t, a, b, c) (0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
347 #define PPC_RAW_MSGSND(b) (0x7c00019c | ___PPC_RB(b))
348 #define PPC_RAW_MSGSYNC (0x7c0006ec)
349 #define PPC_RAW_MSGCLR(b) (0x7c0001dc | ___PPC_RB(b))
350 #define PPC_RAW_MSGSNDP(b) (0x7c00011c | ___PPC_RB(b))
351 #define PPC_RAW_MSGCLRP(b) (0x7c00015c | ___PPC_RB(b))
352 #define PPC_RAW_PASTE(a, b) (0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
353 #define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
354 #define PPC_RAW_POPCNTD(a, s) (0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
355 #define PPC_RAW_POPCNTW(a, s) (0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
356 #define PPC_RAW_RFCI (0x4c000066)
357 #define PPC_RAW_RFDI (0x4c00004e)
358 #define PPC_RAW_RFMCI (0x4c00004c)
359 #define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
360 #define PPC_RAW_WAIT(w) (0x7c00007c | __PPC_WC(w))
361 #define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
362 #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
363 (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
364 #define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
365 (0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
366 #define PPC_RAW_TLBSRX_DOT(a, b) (0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
367 #define PPC_RAW_TLBIVAX(a, b) (0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
368 #define PPC_RAW_ERATWE(s, a, w) (0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
369 #define PPC_RAW_ERATRE(s, a, w) (0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
370 #define PPC_RAW_ERATILX(t, a, b) (0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
371 #define PPC_RAW_ERATIVAX(s, a, b) (0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
372 #define PPC_RAW_ERATSX(t, a, w) (0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
373 #define PPC_RAW_ERATSX_DOT(t, a, w) (0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
374 #define PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
375 #define __PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
376 #define PPC_RAW_ICBT(c, a, b) (0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
377 #define PPC_RAW_LBZCIX(t, a, b) (0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
378 #define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
379 #define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
380 #define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
382 * Define what the VSX XX1 form instructions will look like, then add
383 * the 128 bit load store instructions based on that.
385 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
386 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
387 #define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b))
388 #define PPC_RAW_LXVD2X(s, a, b) (0x7c000698 | VSX_XX1((s), a, b))
389 #define PPC_RAW_MFVRD(a, t) (0x7c000066 | VSX_XX1((t) + 32, a, R0))
390 #define PPC_RAW_MTVRD(t, a) (0x7c000166 | VSX_XX1((t) + 32, a, R0))
391 #define PPC_RAW_VPMSUMW(t, a, b) (0x10000488 | VSX_XX3((t), a, b))
392 #define PPC_RAW_VPMSUMD(t, a, b) (0x100004c8 | VSX_XX3((t), a, b))
393 #define PPC_RAW_XXLOR(t, a, b) (0xf0000490 | VSX_XX3((t), a, b))
394 #define PPC_RAW_XXSWAPD(t, a) (0xf0000250 | VSX_XX3((t), a, a))
395 #define PPC_RAW_XVCPSGNDP(t, a, b) ((0xf0000780 | VSX_XX3((t), (a), (b))))
396 #define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
397 ((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
398 #define PPC_RAW_NAP (0x4c000364)
399 #define PPC_RAW_SLEEP (0x4c0003a4)
400 #define PPC_RAW_WINKLE (0x4c0003e4)
401 #define PPC_RAW_STOP (0x4c0002e4)
402 #define PPC_RAW_CLRBHRB (0x7c00035c)
403 #define PPC_RAW_MFBHRBE(r, n) (0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
404 #define PPC_RAW_TRECHKPT (PPC_INST_TRECHKPT)
405 #define PPC_RAW_TRECLAIM(r) (PPC_INST_TRECLAIM | __PPC_RA(r))
406 #define PPC_RAW_TABORT(r) (0x7c00071d | __PPC_RA(r))
407 #define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
408 #define PPC_RAW_MTTMR(tmr, r) (0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
409 #define PPC_RAW_MFTMR(tmr, r) (0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
410 #define PPC_RAW_ICSWX(s, a, b) (0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
411 #define PPC_RAW_ICSWEPX(s, a, b) (0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
412 #define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
413 #define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
414 (0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
415 #define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
416 (0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
417 #define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
418 #define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
419 #define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
420 #define PPC_RAW_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
421 #define PPC_RAW_STDCX(s, a, b) (0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
422 #define PPC_RAW_LFSX(t, a, b) (0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
423 #define PPC_RAW_STFSX(s, a, b) (0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
424 #define PPC_RAW_LFDX(t, a, b) (0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
425 #define PPC_RAW_STFDX(s, a, b) (0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
426 #define PPC_RAW_LVX(t, a, b) (0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
427 #define PPC_RAW_STVX(s, a, b) (0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
428 #define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
429 #define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
430 #define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
431 #define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
432 #define PPC_RAW_NOP() (PPC_INST_NOP)
433 #define PPC_RAW_BLR() (PPC_INST_BLR)
434 #define PPC_RAW_BLRL() (0x4e800021)
435 #define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r))
436 #define PPC_RAW_BCTR() (PPC_INST_BCTR)
437 #define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r))
438 #define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
439 #define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i)
440 #define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
441 #define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i)
442 #define PPC_RAW_STDX(r, base, b) (0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
443 #define PPC_RAW_STDU(r, base, i) (0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
444 #define PPC_RAW_STW(r, base, i) (0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
445 #define PPC_RAW_STWU(r, base, i) (0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
446 #define PPC_RAW_STH(r, base, i) (0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
447 #define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
448 #define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
449 #define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
450 #define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
451 #define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
452 #define PPC_RAW_LDBRX(r, base, b) (0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
453 #define PPC_RAW_STWCX(s, a, b) (0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
454 #define PPC_RAW_CMPWI(a, i) (0x2c000000 | ___PPC_RA(a) | IMM_L(i))
455 #define PPC_RAW_CMPDI(a, i) (0x2c200000 | ___PPC_RA(a) | IMM_L(i))
456 #define PPC_RAW_CMPW(a, b) (0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
457 #define PPC_RAW_CMPD(a, b) (0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
458 #define PPC_RAW_CMPLWI(a, i) (0x28000000 | ___PPC_RA(a) | IMM_L(i))
459 #define PPC_RAW_CMPLDI(a, i) (0x28200000 | ___PPC_RA(a) | IMM_L(i))
460 #define PPC_RAW_CMPLW(a, b) (0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
461 #define PPC_RAW_CMPLD(a, b) (0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
462 #define PPC_RAW_SUB(d, a, b) (0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
463 #define PPC_RAW_MULD(d, a, b) (0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
464 #define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
465 #define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
466 #define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
467 #define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
468 #define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
469 #define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
470 #define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
471 #define PPC_RAW_DIVDEU(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
472 #define PPC_RAW_DIVDEU_DOT(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
473 #define PPC_RAW_AND(d, a, b) (0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
474 #define PPC_RAW_ANDI(d, a, i) (0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
475 #define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
476 #define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
477 #define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a)
478 #define PPC_RAW_ORI(d, a, i) (PPC_INST_ORI | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
479 #define PPC_RAW_ORIS(d, a, i) (PPC_INST_ORIS | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
480 #define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
481 #define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
482 #define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
483 #define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
484 #define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
485 #define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
486 #define PPC_RAW_SRW(d, a, s) (0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
487 #define PPC_RAW_SRAW(d, a, s) (0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
488 #define PPC_RAW_SRAWI(d, a, i) (0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
489 #define PPC_RAW_SRD(d, a, s) (0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
490 #define PPC_RAW_SRAD(d, a, s) (0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
491 #define PPC_RAW_SRADI(d, a, i) (0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
492 #define PPC_RAW_RLWINM(d, a, i, mb, me) (0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
493 #define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
494 (0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
495 #define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
496 #define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
497 #define PPC_RAW_RLDICR(d, a, i, me) (PPC_INST_RLDICR | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
499 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */
500 #define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
501 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
502 #define PPC_RAW_SRWI(d, a, i) PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
503 /* sldi = rldicr Rx, Ry, n, 63-n */
504 #define PPC_RAW_SLDI(d, a, i) PPC_RAW_RLDICR(d, a, i, 63-(i))
505 /* sldi = rldicl Rx, Ry, 64-n, n */
506 #define PPC_RAW_SRDI(d, a, i) PPC_RAW_RLDICL(d, a, 64-(i), i)
508 #define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
510 /* Deal with instructions that older assemblers aren't aware of */
511 #define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
512 #define PPC_CP_ABORT stringify_in_c(.long PPC_RAW_CP_ABORT)
513 #define PPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b))
514 #define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l))
515 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b))
516 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b))
517 #define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
518 #define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
519 #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
520 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
521 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
522 #define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
523 #define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
524 #define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
525 #define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
526 #define PPC_MSGSND(b) stringify_in_c(.long PPC_RAW_MSGSND(b))
527 #define PPC_MSGSYNC stringify_in_c(.long PPC_RAW_MSGSYNC)
528 #define PPC_MSGCLR(b) stringify_in_c(.long PPC_RAW_MSGCLR(b))
529 #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_RAW_MSGSNDP(b))
530 #define PPC_MSGCLRP(b) stringify_in_c(.long PPC_RAW_MSGCLRP(b))
531 #define PPC_PASTE(a, b) stringify_in_c(.long PPC_RAW_PASTE(a, b))
532 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
533 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
534 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
535 #define PPC_RFCI stringify_in_c(.long PPC_RAW_RFCI)
536 #define PPC_RFDI stringify_in_c(.long PPC_RAW_RFDI)
537 #define PPC_RFMCI stringify_in_c(.long PPC_RAW_RFMCI)
538 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
539 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
540 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
541 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
542 #define PPC_WAIT(w) stringify_in_c(.long PPC_RAW_WAIT(w))
543 #define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
544 #define PPC_TLBIE_5(rb, rs, ric, prs, r) \
545 stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
546 #define PPC_TLBIEL(rb,rs,ric,prs,r) \
547 stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
548 #define PPC_TLBSRX_DOT(a, b) stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
549 #define PPC_TLBIVAX(a, b) stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
551 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
552 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
553 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
554 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
555 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
556 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
557 #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
558 #define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
559 #define PPC_ICBT(c, a, b) stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
560 /* PASemi instructions */
561 #define LBZCIX(t, a, b) stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
562 #define STBCIX(s, a, b) stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
563 #define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
564 #define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
565 #define PPC_PHWSYNC stringify_in_c(.long PPC_RAW_PHWSYNC)
566 #define PPC_PLWSYNC stringify_in_c(.long PPC_RAW_PLWSYNC)
567 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
568 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
569 #define MFVRD(a, t) stringify_in_c(.long PPC_RAW_MFVRD(a, t))
570 #define MTVRD(t, a) stringify_in_c(.long PPC_RAW_MTVRD(t, a))
571 #define VPMSUMW(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
572 #define VPMSUMD(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
573 #define XXLOR(t, a, b) stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
574 #define XXSWAPD(t, a) stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
575 #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
577 #define VPERMXOR(vrt, vra, vrb, vrc) \
578 stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
580 #define PPC_NAP stringify_in_c(.long PPC_RAW_NAP)
581 #define PPC_SLEEP stringify_in_c(.long PPC_RAW_SLEEP)
582 #define PPC_WINKLE stringify_in_c(.long PPC_RAW_WINKLE)
584 #define PPC_STOP stringify_in_c(.long PPC_RAW_STOP)
586 /* BHRB instructions */
587 #define PPC_CLRBHRB stringify_in_c(.long PPC_RAW_CLRBHRB)
588 #define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
590 /* Transactional memory instructions */
591 #define TRECHKPT stringify_in_c(.long PPC_RAW_TRECHKPT)
592 #define TRECLAIM(r) stringify_in_c(.long PPC_RAW_TRECLAIM(r))
593 #define TABORT(r) stringify_in_c(.long PPC_RAW_TABORT(r))
595 /* book3e thread control instructions */
596 #define MTTMR(tmr, r) stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
597 #define MFTMR(tmr, r) stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
599 /* Coprocessor instructions */
600 #define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
601 #define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
603 #define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
606 * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
607 * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
608 * mode (on HPT these would also invalidate various SLBEs which may not be
611 #define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
612 #define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
613 #define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
615 #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
617 #define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
619 #endif /* _ASM_POWERPC_PPC_OPCODE_H */