1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
3 #define _ASM_POWERPC_PCI_BRIDGE_H
8 #include <linux/list.h>
9 #include <linux/ioport.h>
10 #include <linux/numa.h>
15 * PCI controller operations
17 struct pci_controller_ops {
18 void (*dma_dev_setup)(struct pci_dev *pdev);
19 void (*dma_bus_setup)(struct pci_bus *bus);
20 bool (*iommu_bypass_supported)(struct pci_dev *pdev,
23 int (*probe_mode)(struct pci_bus *bus);
25 /* Called when pci_enable_device() is called. Returns true to
26 * allow assignment/enabling of the device. */
27 bool (*enable_device_hook)(struct pci_dev *pdev);
29 void (*disable_device)(struct pci_dev *pdev);
31 void (*release_device)(struct pci_dev *pdev);
33 /* Called during PCI resource reassignment */
34 resource_size_t (*window_alignment)(struct pci_bus *bus,
36 void (*setup_bridge)(struct pci_bus *bus,
38 void (*reset_secondary_bus)(struct pci_dev *pdev);
41 int (*setup_msi_irqs)(struct pci_dev *pdev,
43 void (*teardown_msi_irqs)(struct pci_dev *pdev);
46 void (*shutdown)(struct pci_controller *hose);
50 * Structure of a PCI controller (host bridge)
52 struct pci_controller {
58 struct device_node *dn;
59 struct list_head list_node;
60 struct device *parent;
67 void __iomem *io_base_virt;
69 void __iomem *io_base_alloc;
71 resource_size_t io_base_phys;
72 resource_size_t pci_io_size;
74 /* Some machines have a special region to forward the ISA
75 * "memory" cycles such as VGA memory regions. Left to 0
78 resource_size_t isa_mem_phys;
79 resource_size_t isa_mem_size;
81 struct pci_controller_ops controller_ops;
83 unsigned int __iomem *cfg_addr;
84 void __iomem *cfg_data;
87 * Used for variants of PCI indirect handling and possible quirks:
88 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
89 * EXT_REG - provides access to PCI-e extended registers
90 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
91 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
92 * to determine which bus number to match on when generating type0
94 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
95 * hanging if we don't have link and try to do config cycles to
96 * anything but the PHB. Only allow talking to the PHB if this is
98 * BIG_ENDIAN - cfg_addr is a big endian register
99 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
100 * the PLB4. Effectively disable MRM commands by setting this.
101 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
102 * link status is in a RC PCIe cfg register (vs being a SoC register)
104 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
105 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
106 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
107 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
108 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
109 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
110 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
112 /* Currently, we limit ourselves to 1 IO range and 3 mem
113 * ranges since the common pci_bus structure can't handle more
115 struct resource io_resource;
116 struct resource mem_resources[3];
117 resource_size_t mem_offset[3];
118 int global_number; /* PCI domain number */
120 resource_size_t dma_window_base_cur;
121 resource_size_t dma_window_size;
125 struct pci_dn *pci_data;
126 #endif /* CONFIG_PPC64 */
131 /* These are used for config access before all the PCI probing
133 extern int early_read_config_byte(struct pci_controller *hose, int bus,
134 int dev_fn, int where, u8 *val);
135 extern int early_read_config_word(struct pci_controller *hose, int bus,
136 int dev_fn, int where, u16 *val);
137 extern int early_read_config_dword(struct pci_controller *hose, int bus,
138 int dev_fn, int where, u32 *val);
139 extern int early_write_config_byte(struct pci_controller *hose, int bus,
140 int dev_fn, int where, u8 val);
141 extern int early_write_config_word(struct pci_controller *hose, int bus,
142 int dev_fn, int where, u16 val);
143 extern int early_write_config_dword(struct pci_controller *hose, int bus,
144 int dev_fn, int where, u32 val);
146 extern int early_find_capability(struct pci_controller *hose, int bus,
147 int dev_fn, int cap);
149 extern void setup_indirect_pci(struct pci_controller* hose,
150 resource_size_t cfg_addr,
151 resource_size_t cfg_data, u32 flags);
153 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
154 int offset, int len, u32 *val);
156 extern int __indirect_read_config(struct pci_controller *hose,
157 unsigned char bus_number, unsigned int devfn,
158 int offset, int len, u32 *val);
160 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
161 int offset, int len, u32 val);
163 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
170 extern int pci_device_from_OF_node(struct device_node *node,
172 extern void pci_create_OF_bus_map(void);
174 #else /* CONFIG_PPC64 */
177 * PCI stuff, for nodes representing PCI devices, pointed to
178 * by device_node->data.
184 #define PCI_DN_FLAG_IOV_VF 0x01
185 #define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
187 int busno; /* pci bus number */
188 int devfn; /* pci device and function number */
189 int vendor_id; /* Vendor ID */
190 int device_id; /* Device ID */
191 int class_code; /* Device class code */
193 struct pci_dn *parent;
194 struct pci_controller *phb; /* for pci devices */
195 struct iommu_table_group *table_group; /* for phb's or bridges */
197 int pci_ext_config_space; /* for pci devices */
199 struct eeh_dev *edev; /* eeh device */
201 #define IODA_INVALID_PE 0xFFFFFFFF
202 unsigned int pe_number;
203 #ifdef CONFIG_PCI_IOV
204 u16 vfs_expanded; /* number of VFs IOV BAR expanded */
205 u16 num_vfs; /* number of VFs enabled*/
206 unsigned int *pe_num_map; /* PE# for the first VF PE or array */
207 bool m64_single_mode; /* Use M64 BAR in Single Mode */
208 #define IODA_INVALID_M64 (-1)
209 int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
210 int last_allow_rc; /* Only used on pseries */
211 #endif /* CONFIG_PCI_IOV */
212 int mps; /* Maximum Payload Size */
213 struct list_head child_list;
214 struct list_head list;
215 struct resource holes[PCI_SRIOV_NUM_BARS];
218 /* Get the pointer to a device_node's pci_dn */
219 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
221 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
223 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
224 extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
225 struct device_node *dn);
226 extern void pci_remove_device_node_info(struct device_node *dn);
228 #ifdef CONFIG_PCI_IOV
229 struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
230 void remove_sriov_vf_pdns(struct pci_dev *pdev);
233 static inline int pci_device_from_OF_node(struct device_node *np,
238 *bus = PCI_DN(np)->busno;
239 *devfn = PCI_DN(np)->devfn;
243 #if defined(CONFIG_EEH)
244 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
246 return pdn ? pdn->edev : NULL;
249 #define pdn_to_eeh_dev(x) (NULL)
252 /** Find the bus corresponding to the indicated device node */
253 extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
255 /** Remove all of the PCI devices under this bus */
256 extern void pci_hp_remove_devices(struct pci_bus *bus);
258 /** Discover new pci devices under this bus, and add them */
259 extern void pci_hp_add_devices(struct pci_bus *bus);
261 extern int pcibios_unmap_io_space(struct pci_bus *bus);
262 extern int pcibios_map_io_space(struct pci_bus *bus);
265 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
267 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
270 #endif /* CONFIG_PPC64 */
272 /* Get the PCI host controller for an OF device */
273 extern struct pci_controller *pci_find_hose_for_OF_device(
274 struct device_node* node);
276 extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
278 /* Fill up host controller resources from the OF node */
279 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
280 struct device_node *dev, int primary);
282 /* Allocate & free a PCI host bridge structure */
283 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
284 extern void pcibios_free_controller(struct pci_controller *phb);
285 extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
288 extern int pcibios_vaddr_is_ioport(void __iomem *address);
290 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
294 #endif /* CONFIG_PCI */
296 #endif /* __KERNEL__ */
297 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */