Merge tag 'fixes-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/brauner...
[linux-2.6-microblaze.git] / arch / powerpc / include / asm / opal-api.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * OPAL API definitions.
4  *
5  * Copyright 2011-2015 IBM Corp.
6  */
7
8 #ifndef __OPAL_API_H
9 #define __OPAL_API_H
10
11 /****** OPAL APIs ******/
12
13 /* Return codes */
14 #define OPAL_SUCCESS            0
15 #define OPAL_PARAMETER          -1
16 #define OPAL_BUSY               -2
17 #define OPAL_PARTIAL            -3
18 #define OPAL_CONSTRAINED        -4
19 #define OPAL_CLOSED             -5
20 #define OPAL_HARDWARE           -6
21 #define OPAL_UNSUPPORTED        -7
22 #define OPAL_PERMISSION         -8
23 #define OPAL_NO_MEM             -9
24 #define OPAL_RESOURCE           -10
25 #define OPAL_INTERNAL_ERROR     -11
26 #define OPAL_BUSY_EVENT         -12
27 #define OPAL_HARDWARE_FROZEN    -13
28 #define OPAL_WRONG_STATE        -14
29 #define OPAL_ASYNC_COMPLETION   -15
30 #define OPAL_EMPTY              -16
31 #define OPAL_I2C_TIMEOUT        -17
32 #define OPAL_I2C_INVALID_CMD    -18
33 #define OPAL_I2C_LBUS_PARITY    -19
34 #define OPAL_I2C_BKEND_OVERRUN  -20
35 #define OPAL_I2C_BKEND_ACCESS   -21
36 #define OPAL_I2C_ARBT_LOST      -22
37 #define OPAL_I2C_NACK_RCVD      -23
38 #define OPAL_I2C_STOP_ERR       -24
39 #define OPAL_XIVE_PROVISIONING  -31
40 #define OPAL_XIVE_FREE_ACTIVE   -32
41 #define OPAL_TIMEOUT            -33
42
43 /* API Tokens (in r0) */
44 #define OPAL_INVALID_CALL                      -1
45 #define OPAL_TEST                               0
46 #define OPAL_CONSOLE_WRITE                      1
47 #define OPAL_CONSOLE_READ                       2
48 #define OPAL_RTC_READ                           3
49 #define OPAL_RTC_WRITE                          4
50 #define OPAL_CEC_POWER_DOWN                     5
51 #define OPAL_CEC_REBOOT                         6
52 #define OPAL_READ_NVRAM                         7
53 #define OPAL_WRITE_NVRAM                        8
54 #define OPAL_HANDLE_INTERRUPT                   9
55 #define OPAL_POLL_EVENTS                        10
56 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
57 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
58 #define OPAL_PCI_CONFIG_READ_BYTE               13
59 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
60 #define OPAL_PCI_CONFIG_READ_WORD               15
61 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
62 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
63 #define OPAL_PCI_CONFIG_WRITE_WORD              18
64 #define OPAL_SET_XIVE                           19
65 #define OPAL_GET_XIVE                           20
66 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
67 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
68 #define OPAL_PCI_EEH_FREEZE_STATUS              23
69 #define OPAL_PCI_SHPC                           24
70 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
71 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
72 #define OPAL_PCI_PHB_MMIO_ENABLE                27
73 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
74 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
75 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
76 #define OPAL_PCI_SET_PE                         31
77 #define OPAL_PCI_SET_PELTV                      32
78 #define OPAL_PCI_SET_MVE                        33
79 #define OPAL_PCI_SET_MVE_ENABLE                 34
80 #define OPAL_PCI_GET_XIVE_REISSUE               35
81 #define OPAL_PCI_SET_XIVE_REISSUE               36
82 #define OPAL_PCI_SET_XIVE_PE                    37
83 #define OPAL_GET_XIVE_SOURCE                    38
84 #define OPAL_GET_MSI_32                         39
85 #define OPAL_GET_MSI_64                         40
86 #define OPAL_START_CPU                          41
87 #define OPAL_QUERY_CPU_STATUS                   42
88 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
89 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
90 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
91 #define OPAL_PCI_RESET                          49
92 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
93 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
94 #define OPAL_PCI_FENCE_PHB                      52
95 #define OPAL_PCI_REINIT                         53
96 #define OPAL_PCI_MASK_PE_ERROR                  54
97 #define OPAL_SET_SLOT_LED_STATUS                55
98 #define OPAL_GET_EPOW_STATUS                    56
99 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
100 #define OPAL_RESERVED1                          58
101 #define OPAL_RESERVED2                          59
102 #define OPAL_PCI_NEXT_ERROR                     60
103 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
104 #define OPAL_PCI_POLL                           62
105 #define OPAL_PCI_MSI_EOI                        63
106 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
107 #define OPAL_XSCOM_READ                         65
108 #define OPAL_XSCOM_WRITE                        66
109 #define OPAL_LPC_READ                           67
110 #define OPAL_LPC_WRITE                          68
111 #define OPAL_RETURN_CPU                         69
112 #define OPAL_REINIT_CPUS                        70
113 #define OPAL_ELOG_READ                          71
114 #define OPAL_ELOG_WRITE                         72
115 #define OPAL_ELOG_ACK                           73
116 #define OPAL_ELOG_RESEND                        74
117 #define OPAL_ELOG_SIZE                          75
118 #define OPAL_FLASH_VALIDATE                     76
119 #define OPAL_FLASH_MANAGE                       77
120 #define OPAL_FLASH_UPDATE                       78
121 #define OPAL_RESYNC_TIMEBASE                    79
122 #define OPAL_CHECK_TOKEN                        80
123 #define OPAL_DUMP_INIT                          81
124 #define OPAL_DUMP_INFO                          82
125 #define OPAL_DUMP_READ                          83
126 #define OPAL_DUMP_ACK                           84
127 #define OPAL_GET_MSG                            85
128 #define OPAL_CHECK_ASYNC_COMPLETION             86
129 #define OPAL_SYNC_HOST_REBOOT                   87
130 #define OPAL_SENSOR_READ                        88
131 #define OPAL_GET_PARAM                          89
132 #define OPAL_SET_PARAM                          90
133 #define OPAL_DUMP_RESEND                        91
134 #define OPAL_ELOG_SEND                          92      /* Deprecated */
135 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
136 #define OPAL_DUMP_INFO2                         94
137 #define OPAL_WRITE_OPPANEL_ASYNC                95
138 #define OPAL_PCI_ERR_INJECT                     96
139 #define OPAL_PCI_EEH_FREEZE_SET                 97
140 #define OPAL_HANDLE_HMI                         98
141 #define OPAL_CONFIG_CPU_IDLE_STATE              99
142 #define OPAL_SLW_SET_REG                        100
143 #define OPAL_REGISTER_DUMP_REGION               101
144 #define OPAL_UNREGISTER_DUMP_REGION             102
145 #define OPAL_WRITE_TPO                          103
146 #define OPAL_READ_TPO                           104
147 #define OPAL_GET_DPO_STATUS                     105
148 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
149 #define OPAL_IPMI_SEND                          107
150 #define OPAL_IPMI_RECV                          108
151 #define OPAL_I2C_REQUEST                        109
152 #define OPAL_FLASH_READ                         110
153 #define OPAL_FLASH_WRITE                        111
154 #define OPAL_FLASH_ERASE                        112
155 #define OPAL_PRD_MSG                            113
156 #define OPAL_LEDS_GET_INDICATOR                 114
157 #define OPAL_LEDS_SET_INDICATOR                 115
158 #define OPAL_CEC_REBOOT2                        116
159 #define OPAL_CONSOLE_FLUSH                      117
160 #define OPAL_GET_DEVICE_TREE                    118
161 #define OPAL_PCI_GET_PRESENCE_STATE             119
162 #define OPAL_PCI_GET_POWER_STATE                120
163 #define OPAL_PCI_SET_POWER_STATE                121
164 #define OPAL_INT_GET_XIRR                       122
165 #define OPAL_INT_SET_CPPR                       123
166 #define OPAL_INT_EOI                            124
167 #define OPAL_INT_SET_MFRR                       125
168 #define OPAL_PCI_TCE_KILL                       126
169 #define OPAL_NMMU_SET_PTCR                      127
170 #define OPAL_XIVE_RESET                         128
171 #define OPAL_XIVE_GET_IRQ_INFO                  129
172 #define OPAL_XIVE_GET_IRQ_CONFIG                130
173 #define OPAL_XIVE_SET_IRQ_CONFIG                131
174 #define OPAL_XIVE_GET_QUEUE_INFO                132
175 #define OPAL_XIVE_SET_QUEUE_INFO                133
176 #define OPAL_XIVE_DONATE_PAGE                   134
177 #define OPAL_XIVE_ALLOCATE_VP_BLOCK             135
178 #define OPAL_XIVE_FREE_VP_BLOCK                 136
179 #define OPAL_XIVE_GET_VP_INFO                   137
180 #define OPAL_XIVE_SET_VP_INFO                   138
181 #define OPAL_XIVE_ALLOCATE_IRQ                  139
182 #define OPAL_XIVE_FREE_IRQ                      140
183 #define OPAL_XIVE_SYNC                          141
184 #define OPAL_XIVE_DUMP                          142
185 #define OPAL_XIVE_GET_QUEUE_STATE               143
186 #define OPAL_XIVE_SET_QUEUE_STATE               144
187 #define OPAL_SIGNAL_SYSTEM_RESET                145
188 #define OPAL_NPU_INIT_CONTEXT                   146
189 #define OPAL_NPU_DESTROY_CONTEXT                147
190 #define OPAL_NPU_MAP_LPAR                       148
191 #define OPAL_IMC_COUNTERS_INIT                  149
192 #define OPAL_IMC_COUNTERS_START                 150
193 #define OPAL_IMC_COUNTERS_STOP                  151
194 #define OPAL_GET_POWERCAP                       152
195 #define OPAL_SET_POWERCAP                       153
196 #define OPAL_GET_POWER_SHIFT_RATIO              154
197 #define OPAL_SET_POWER_SHIFT_RATIO              155
198 #define OPAL_SENSOR_GROUP_CLEAR                 156
199 #define OPAL_PCI_SET_P2P                        157
200 #define OPAL_QUIESCE                            158
201 #define OPAL_NPU_SPA_SETUP                      159
202 #define OPAL_NPU_SPA_CLEAR_CACHE                160
203 #define OPAL_NPU_TL_SET                         161
204 #define OPAL_SENSOR_READ_U64                    162
205 #define OPAL_SENSOR_GROUP_ENABLE                163
206 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR            164
207 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR            165
208 #define OPAL_HANDLE_HMI2                        166
209 #define OPAL_NX_COPROC_INIT                     167
210 #define OPAL_XIVE_GET_VP_STATE                  170
211 #define OPAL_MPIPL_UPDATE                       173
212 #define OPAL_MPIPL_REGISTER_TAG                 174
213 #define OPAL_MPIPL_QUERY_TAG                    175
214 #define OPAL_SECVAR_GET                         176
215 #define OPAL_SECVAR_GET_NEXT                    177
216 #define OPAL_SECVAR_ENQUEUE_UPDATE              178
217 #define OPAL_LAST                               178
218
219 #define QUIESCE_HOLD                    1 /* Spin all calls at entry */
220 #define QUIESCE_REJECT                  2 /* Fail all calls with OPAL_BUSY */
221 #define QUIESCE_LOCK_BREAK              3 /* Set to ignore locks. */
222 #define QUIESCE_RESUME                  4 /* Un-quiesce */
223 #define QUIESCE_RESUME_FAST_REBOOT      5 /* Un-quiesce, fast reboot */
224
225 /* Device tree flags */
226
227 /*
228  * Flags set in power-mgmt nodes in device tree describing
229  * idle states that are supported in the platform.
230  */
231
232 #define OPAL_PM_TIMEBASE_STOP           0x00000002
233 #define OPAL_PM_LOSE_HYP_CONTEXT        0x00002000
234 #define OPAL_PM_LOSE_FULL_CONTEXT       0x00004000
235 #define OPAL_PM_NAP_ENABLED             0x00010000
236 #define OPAL_PM_SLEEP_ENABLED           0x00020000
237 #define OPAL_PM_WINKLE_ENABLED          0x00040000
238 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
239 #define OPAL_PM_STOP_INST_FAST          0x00100000
240 #define OPAL_PM_STOP_INST_DEEP          0x00200000
241
242 /*
243  * OPAL_CONFIG_CPU_IDLE_STATE parameters
244  */
245 #define OPAL_CONFIG_IDLE_FASTSLEEP      1
246 #define OPAL_CONFIG_IDLE_UNDO           0
247 #define OPAL_CONFIG_IDLE_APPLY          1
248
249 #ifndef __ASSEMBLY__
250
251 /* Other enums */
252 enum OpalFreezeState {
253         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
254         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
255         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
256         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
257         OPAL_EEH_STOPPED_RESET = 4,
258         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
259         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
260 };
261
262 enum OpalEehFreezeActionToken {
263         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
264         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
265         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
266
267         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
268         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
269         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
270 };
271
272 enum OpalPciStatusToken {
273         OPAL_EEH_NO_ERROR       = 0,
274         OPAL_EEH_IOC_ERROR      = 1,
275         OPAL_EEH_PHB_ERROR      = 2,
276         OPAL_EEH_PE_ERROR       = 3,
277         OPAL_EEH_PE_MMIO_ERROR  = 4,
278         OPAL_EEH_PE_DMA_ERROR   = 5
279 };
280
281 enum OpalPciErrorSeverity {
282         OPAL_EEH_SEV_NO_ERROR   = 0,
283         OPAL_EEH_SEV_IOC_DEAD   = 1,
284         OPAL_EEH_SEV_PHB_DEAD   = 2,
285         OPAL_EEH_SEV_PHB_FENCED = 3,
286         OPAL_EEH_SEV_PE_ER      = 4,
287         OPAL_EEH_SEV_INF        = 5
288 };
289
290 enum OpalErrinjectType {
291         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
292         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
293 };
294
295 enum OpalErrinjectFunc {
296         /* IOA bus specific errors */
297         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
298         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
299         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
300         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
301         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
302         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
303         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
304         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
305         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
306         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
307         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
308         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
309         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
310         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
311         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
312         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
313         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
314         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
315         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
316         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
317 };
318
319 enum OpalMmioWindowType {
320         OPAL_M32_WINDOW_TYPE = 1,
321         OPAL_M64_WINDOW_TYPE = 2,
322         OPAL_IO_WINDOW_TYPE  = 3
323 };
324
325 enum OpalExceptionHandler {
326         OPAL_MACHINE_CHECK_HANDLER          = 1,
327         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
328         OPAL_SOFTPATCH_HANDLER              = 3
329 };
330
331 enum OpalPendingState {
332         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
333         OPAL_EVENT_NVRAM           = 0x2,
334         OPAL_EVENT_RTC             = 0x4,
335         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
336         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
337         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
338         OPAL_EVENT_ERROR_LOG       = 0x40,
339         OPAL_EVENT_EPOW            = 0x80,
340         OPAL_EVENT_LED_STATUS      = 0x100,
341         OPAL_EVENT_PCI_ERROR       = 0x200,
342         OPAL_EVENT_DUMP_AVAIL      = 0x400,
343         OPAL_EVENT_MSG_PENDING     = 0x800,
344 };
345
346 enum OpalThreadStatus {
347         OPAL_THREAD_INACTIVE = 0x0,
348         OPAL_THREAD_STARTED = 0x1,
349         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
350 };
351
352 enum OpalPciBusCompare {
353         OpalPciBusAny   = 0,    /* Any bus number match */
354         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
355         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
356         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
357         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
358         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
359         OpalPciBusAll   = 7,    /* Match bus number exactly */
360 };
361
362 enum OpalDeviceCompare {
363         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
364         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
365 };
366
367 enum OpalFuncCompare {
368         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
369         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
370 };
371
372 enum OpalPeAction {
373         OPAL_UNMAP_PE = 0,
374         OPAL_MAP_PE = 1
375 };
376
377 enum OpalPeltvAction {
378         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
379         OPAL_ADD_PE_TO_DOMAIN = 1
380 };
381
382 enum OpalMveEnableAction {
383         OPAL_DISABLE_MVE = 0,
384         OPAL_ENABLE_MVE = 1
385 };
386
387 enum OpalM64Action {
388         OPAL_DISABLE_M64 = 0,
389         OPAL_ENABLE_M64_SPLIT = 1,
390         OPAL_ENABLE_M64_NON_SPLIT = 2
391 };
392
393 enum OpalPciResetScope {
394         OPAL_RESET_PHB_COMPLETE         = 1,
395         OPAL_RESET_PCI_LINK             = 2,
396         OPAL_RESET_PHB_ERROR            = 3,
397         OPAL_RESET_PCI_HOT              = 4,
398         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
399         OPAL_RESET_PCI_IODA_TABLE       = 6
400 };
401
402 enum OpalPciReinitScope {
403         /*
404          * Note: we chose values that do not overlap
405          * OpalPciResetScope as OPAL v2 used the same
406          * enum for both
407          */
408         OPAL_REINIT_PCI_DEV = 1000
409 };
410
411 enum OpalPciResetState {
412         OPAL_DEASSERT_RESET = 0,
413         OPAL_ASSERT_RESET   = 1
414 };
415
416 enum OpalPciSlotPresence {
417         OPAL_PCI_SLOT_EMPTY     = 0,
418         OPAL_PCI_SLOT_PRESENT   = 1
419 };
420
421 enum OpalPciSlotPower {
422         OPAL_PCI_SLOT_POWER_OFF = 0,
423         OPAL_PCI_SLOT_POWER_ON  = 1,
424         OPAL_PCI_SLOT_OFFLINE   = 2,
425         OPAL_PCI_SLOT_ONLINE    = 3
426 };
427
428 enum OpalSlotLedType {
429         OPAL_SLOT_LED_TYPE_ID = 0,      /* IDENTIFY LED */
430         OPAL_SLOT_LED_TYPE_FAULT = 1,   /* FAULT LED */
431         OPAL_SLOT_LED_TYPE_ATTN = 2,    /* System Attention LED */
432         OPAL_SLOT_LED_TYPE_MAX = 3
433 };
434
435 enum OpalSlotLedState {
436         OPAL_SLOT_LED_STATE_OFF = 0,    /* LED is OFF */
437         OPAL_SLOT_LED_STATE_ON = 1      /* LED is ON */
438 };
439
440 /*
441  * Address cycle types for LPC accesses. These also correspond
442  * to the content of the first cell of the "reg" property for
443  * device nodes on the LPC bus
444  */
445 enum OpalLPCAddressType {
446         OPAL_LPC_MEM    = 0,
447         OPAL_LPC_IO     = 1,
448         OPAL_LPC_FW     = 2,
449 };
450
451 enum opal_msg_type {
452         OPAL_MSG_ASYNC_COMP     = 0,    /* params[0] = token, params[1] = rc,
453                                          * additional params function-specific
454                                          */
455         OPAL_MSG_MEM_ERR        = 1,
456         OPAL_MSG_EPOW           = 2,
457         OPAL_MSG_SHUTDOWN       = 3,    /* params[0] = 1 reboot, 0 shutdown */
458         OPAL_MSG_HMI_EVT        = 4,
459         OPAL_MSG_DPO            = 5,
460         OPAL_MSG_PRD            = 6,
461         OPAL_MSG_OCC            = 7,
462         OPAL_MSG_PRD2           = 8,
463         OPAL_MSG_TYPE_MAX,
464 };
465
466 struct opal_msg {
467         __be32 msg_type;
468         __be32 reserved;
469         __be64 params[8];
470 };
471
472 /* System parameter permission */
473 enum OpalSysparamPerm {
474         OPAL_SYSPARAM_READ  = 0x1,
475         OPAL_SYSPARAM_WRITE = 0x2,
476         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
477 };
478
479 enum {
480         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
481 };
482
483 struct opal_ipmi_msg {
484         uint8_t version;
485         uint8_t netfn;
486         uint8_t cmd;
487         uint8_t data[];
488 };
489
490 /* FSP memory errors handling */
491 enum OpalMemErr_Version {
492         OpalMemErr_V1 = 1,
493 };
494
495 enum OpalMemErrType {
496         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
497         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
498 };
499
500 /* Memory Reilience error type */
501 enum OpalMemErr_ResilErrType {
502         OPAL_MEM_RESILIENCE_CE          = 0,
503         OPAL_MEM_RESILIENCE_UE,
504         OPAL_MEM_RESILIENCE_UE_SCRUB,
505 };
506
507 /* Dynamic Memory Deallocation type */
508 enum OpalMemErr_DynErrType {
509         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
510 };
511
512 struct OpalMemoryErrorData {
513         enum OpalMemErr_Version version:8;      /* 0x00 */
514         enum OpalMemErrType     type:8;         /* 0x01 */
515         __be16                  flags;          /* 0x02 */
516         uint8_t                 reserved_1[4];  /* 0x04 */
517
518         union {
519                 /* Memory Resilience corrected/uncorrected error info */
520                 struct {
521                         enum OpalMemErr_ResilErrType    resil_err_type:8;
522                         uint8_t                         reserved_1[7];
523                         __be64                          physical_address_start;
524                         __be64                          physical_address_end;
525                 } resilience;
526                 /* Dynamic memory deallocation error info */
527                 struct {
528                         enum OpalMemErr_DynErrType      dyn_err_type:8;
529                         uint8_t                         reserved_1[7];
530                         __be64                          physical_address_start;
531                         __be64                          physical_address_end;
532                 } dyn_dealloc;
533         } u;
534 };
535
536 /* HMI interrupt event */
537 enum OpalHMI_Version {
538         OpalHMIEvt_V1 = 1,
539         OpalHMIEvt_V2 = 2,
540 };
541
542 enum OpalHMI_Severity {
543         OpalHMI_SEV_NO_ERROR = 0,
544         OpalHMI_SEV_WARNING = 1,
545         OpalHMI_SEV_ERROR_SYNC = 2,
546         OpalHMI_SEV_FATAL = 3,
547 };
548
549 enum OpalHMI_Disposition {
550         OpalHMI_DISPOSITION_RECOVERED = 0,
551         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
552 };
553
554 enum OpalHMI_ErrType {
555         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
556         OpalHMI_ERROR_PROC_RECOV_DONE,
557         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
558         OpalHMI_ERROR_PROC_RECOV_MASKED,
559         OpalHMI_ERROR_TFAC,
560         OpalHMI_ERROR_TFMR_PARITY,
561         OpalHMI_ERROR_HA_OVERFLOW_WARN,
562         OpalHMI_ERROR_XSCOM_FAIL,
563         OpalHMI_ERROR_XSCOM_DONE,
564         OpalHMI_ERROR_SCOM_FIR,
565         OpalHMI_ERROR_DEBUG_TRIG_FIR,
566         OpalHMI_ERROR_HYP_RESOURCE,
567         OpalHMI_ERROR_CAPP_RECOVERY,
568 };
569
570 enum OpalHMI_XstopType {
571         CHECKSTOP_TYPE_UNKNOWN  =       0,
572         CHECKSTOP_TYPE_CORE     =       1,
573         CHECKSTOP_TYPE_NX       =       2,
574         CHECKSTOP_TYPE_NPU      =       3
575 };
576
577 enum OpalHMI_CoreXstopReason {
578         CORE_CHECKSTOP_IFU_REGFILE              = 0x00000001,
579         CORE_CHECKSTOP_IFU_LOGIC                = 0x00000002,
580         CORE_CHECKSTOP_PC_DURING_RECOV          = 0x00000004,
581         CORE_CHECKSTOP_ISU_REGFILE              = 0x00000008,
582         CORE_CHECKSTOP_ISU_LOGIC                = 0x00000010,
583         CORE_CHECKSTOP_FXU_LOGIC                = 0x00000020,
584         CORE_CHECKSTOP_VSU_LOGIC                = 0x00000040,
585         CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE   = 0x00000080,
586         CORE_CHECKSTOP_LSU_REGFILE              = 0x00000100,
587         CORE_CHECKSTOP_PC_FWD_PROGRESS          = 0x00000200,
588         CORE_CHECKSTOP_LSU_LOGIC                = 0x00000400,
589         CORE_CHECKSTOP_PC_LOGIC                 = 0x00000800,
590         CORE_CHECKSTOP_PC_HYP_RESOURCE          = 0x00001000,
591         CORE_CHECKSTOP_PC_HANG_RECOV_FAILED     = 0x00002000,
592         CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED    = 0x00004000,
593         CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ    = 0x00008000,
594         CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ      = 0x00010000,
595 };
596
597 enum OpalHMI_NestAccelXstopReason {
598         NX_CHECKSTOP_SHM_INVAL_STATE_ERR        = 0x00000001,
599         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1      = 0x00000002,
600         NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2      = 0x00000004,
601         NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR    = 0x00000008,
602         NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR    = 0x00000010,
603         NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR    = 0x00000020,
604         NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR    = 0x00000040,
605         NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR    = 0x00000080,
606         NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR    = 0x00000100,
607         NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR    = 0x00000200,
608         NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR    = 0x00000400,
609         NX_CHECKSTOP_DMA_CRB_UE                 = 0x00000800,
610         NX_CHECKSTOP_DMA_CRB_SUE                = 0x00001000,
611         NX_CHECKSTOP_PBI_ISN_UE                 = 0x00002000,
612 };
613
614 struct OpalHMIEvent {
615         uint8_t         version;        /* 0x00 */
616         uint8_t         severity;       /* 0x01 */
617         uint8_t         type;           /* 0x02 */
618         uint8_t         disposition;    /* 0x03 */
619         uint8_t         reserved_1[4];  /* 0x04 */
620
621         __be64          hmer;
622         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
623         __be64          tfmr;
624
625         /* version 2 and later */
626         union {
627                 /*
628                  * checkstop info (Core/NX).
629                  * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
630                  */
631                 struct {
632                         uint8_t xstop_type;     /* enum OpalHMI_XstopType */
633                         uint8_t reserved_1[3];
634                         __be32  xstop_reason;
635                         union {
636                                 __be32 pir;     /* for CHECKSTOP_TYPE_CORE */
637                                 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
638                         } u;
639                 } xstop_error;
640         } u;
641 };
642
643 /* OPAL_HANDLE_HMI2 out_flags */
644 enum {
645         OPAL_HMI_FLAGS_TB_RESYNC        = (1ull << 0), /* Timebase has been resynced */
646         OPAL_HMI_FLAGS_DEC_LOST         = (1ull << 1), /* DEC lost, needs to be reprogrammed */
647         OPAL_HMI_FLAGS_HDEC_LOST        = (1ull << 2), /* HDEC lost, needs to be reprogrammed */
648         OPAL_HMI_FLAGS_TOD_TB_FAIL      = (1ull << 3), /* TOD/TB recovery failed. */
649         OPAL_HMI_FLAGS_NEW_EVENT        = (1ull << 63), /* An event has been created */
650 };
651
652 enum {
653         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
654         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
655         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
656         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
657         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
658         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
659         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
660 };
661
662 struct OpalIoP7IOCErrorData {
663         __be16 type;
664
665         /* GEM */
666         __be64 gemXfir;
667         __be64 gemRfir;
668         __be64 gemRirqfir;
669         __be64 gemMask;
670         __be64 gemRwof;
671
672         /* LEM */
673         __be64 lemFir;
674         __be64 lemErrMask;
675         __be64 lemAction0;
676         __be64 lemAction1;
677         __be64 lemWof;
678
679         union {
680                 struct OpalIoP7IOCRgcErrorData {
681                         __be64 rgcStatus;       /* 3E1C10 */
682                         __be64 rgcLdcp;         /* 3E1C18 */
683                 }rgc;
684                 struct OpalIoP7IOCBiErrorData {
685                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
686                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
687                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
688                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
689
690                         uint8_t biDownbound;    /* BI Downbound or Upbound */
691                 }bi;
692                 struct OpalIoP7IOCCiErrorData {
693                         __be64 ciPortStatus;    /* 3Dn008 */
694                         __be64 ciPortLdcp;      /* 3Dn010 */
695
696                         uint8_t ciPort;         /* Index of CI port: 0/1 */
697                 }ci;
698         };
699 };
700
701 /**
702  * This structure defines the overlay which will be used to store PHB error
703  * data upon request.
704  */
705 enum {
706         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
707 };
708
709 enum {
710         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
711         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
712         OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
713 };
714
715 enum {
716         OPAL_P7IOC_NUM_PEST_REGS = 128,
717         OPAL_PHB3_NUM_PEST_REGS = 256,
718         OPAL_PHB4_NUM_PEST_REGS = 512
719 };
720
721 struct OpalIoPhbErrorCommon {
722         __be32 version;
723         __be32 ioType;
724         __be32 len;
725 };
726
727 struct OpalIoP7IOCPhbErrorData {
728         struct OpalIoPhbErrorCommon common;
729
730         __be32 brdgCtl;
731
732         // P7IOC utl regs
733         __be32 portStatusReg;
734         __be32 rootCmplxStatus;
735         __be32 busAgentStatus;
736
737         // P7IOC cfg regs
738         __be32 deviceStatus;
739         __be32 slotStatus;
740         __be32 linkStatus;
741         __be32 devCmdStatus;
742         __be32 devSecStatus;
743
744         // cfg AER regs
745         __be32 rootErrorStatus;
746         __be32 uncorrErrorStatus;
747         __be32 corrErrorStatus;
748         __be32 tlpHdr1;
749         __be32 tlpHdr2;
750         __be32 tlpHdr3;
751         __be32 tlpHdr4;
752         __be32 sourceId;
753
754         __be32 rsv3;
755
756         // Record data about the call to allocate a buffer.
757         __be64 errorClass;
758         __be64 correlator;
759
760         //P7IOC MMIO Error Regs
761         __be64 p7iocPlssr;                // n120
762         __be64 p7iocCsr;                  // n110
763         __be64 lemFir;                    // nC00
764         __be64 lemErrorMask;              // nC18
765         __be64 lemWOF;                    // nC40
766         __be64 phbErrorStatus;            // nC80
767         __be64 phbFirstErrorStatus;       // nC88
768         __be64 phbErrorLog0;              // nCC0
769         __be64 phbErrorLog1;              // nCC8
770         __be64 mmioErrorStatus;           // nD00
771         __be64 mmioFirstErrorStatus;      // nD08
772         __be64 mmioErrorLog0;             // nD40
773         __be64 mmioErrorLog1;             // nD48
774         __be64 dma0ErrorStatus;           // nD80
775         __be64 dma0FirstErrorStatus;      // nD88
776         __be64 dma0ErrorLog0;             // nDC0
777         __be64 dma0ErrorLog1;             // nDC8
778         __be64 dma1ErrorStatus;           // nE00
779         __be64 dma1FirstErrorStatus;      // nE08
780         __be64 dma1ErrorLog0;             // nE40
781         __be64 dma1ErrorLog1;             // nE48
782         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
783         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
784 };
785
786 struct OpalIoPhb3ErrorData {
787         struct OpalIoPhbErrorCommon common;
788
789         __be32 brdgCtl;
790
791         /* PHB3 UTL regs */
792         __be32 portStatusReg;
793         __be32 rootCmplxStatus;
794         __be32 busAgentStatus;
795
796         /* PHB3 cfg regs */
797         __be32 deviceStatus;
798         __be32 slotStatus;
799         __be32 linkStatus;
800         __be32 devCmdStatus;
801         __be32 devSecStatus;
802
803         /* cfg AER regs */
804         __be32 rootErrorStatus;
805         __be32 uncorrErrorStatus;
806         __be32 corrErrorStatus;
807         __be32 tlpHdr1;
808         __be32 tlpHdr2;
809         __be32 tlpHdr3;
810         __be32 tlpHdr4;
811         __be32 sourceId;
812
813         __be32 rsv3;
814
815         /* Record data about the call to allocate a buffer */
816         __be64 errorClass;
817         __be64 correlator;
818
819         /* PHB3 MMIO Error Regs */
820         __be64 nFir;                    /* 000 */
821         __be64 nFirMask;                /* 003 */
822         __be64 nFirWOF;         /* 008 */
823         __be64 phbPlssr;                /* 120 */
824         __be64 phbCsr;          /* 110 */
825         __be64 lemFir;          /* C00 */
826         __be64 lemErrorMask;            /* C18 */
827         __be64 lemWOF;          /* C40 */
828         __be64 phbErrorStatus;  /* C80 */
829         __be64 phbFirstErrorStatus;     /* C88 */
830         __be64 phbErrorLog0;            /* CC0 */
831         __be64 phbErrorLog1;            /* CC8 */
832         __be64 mmioErrorStatus; /* D00 */
833         __be64 mmioFirstErrorStatus;    /* D08 */
834         __be64 mmioErrorLog0;           /* D40 */
835         __be64 mmioErrorLog1;           /* D48 */
836         __be64 dma0ErrorStatus; /* D80 */
837         __be64 dma0FirstErrorStatus;    /* D88 */
838         __be64 dma0ErrorLog0;           /* DC0 */
839         __be64 dma0ErrorLog1;           /* DC8 */
840         __be64 dma1ErrorStatus; /* E00 */
841         __be64 dma1FirstErrorStatus;    /* E08 */
842         __be64 dma1ErrorLog0;           /* E40 */
843         __be64 dma1ErrorLog1;           /* E48 */
844         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
845         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
846 };
847
848 struct OpalIoPhb4ErrorData {
849         struct OpalIoPhbErrorCommon common;
850
851         __be32 brdgCtl;
852
853         /* PHB4 cfg regs */
854         __be32 deviceStatus;
855         __be32 slotStatus;
856         __be32 linkStatus;
857         __be32 devCmdStatus;
858         __be32 devSecStatus;
859
860         /* cfg AER regs */
861         __be32 rootErrorStatus;
862         __be32 uncorrErrorStatus;
863         __be32 corrErrorStatus;
864         __be32 tlpHdr1;
865         __be32 tlpHdr2;
866         __be32 tlpHdr3;
867         __be32 tlpHdr4;
868         __be32 sourceId;
869
870         /* PHB4 ETU Error Regs */
871         __be64 nFir;                            /* 000 */
872         __be64 nFirMask;                        /* 003 */
873         __be64 nFirWOF;                         /* 008 */
874         __be64 phbPlssr;                        /* 120 */
875         __be64 phbCsr;                          /* 110 */
876         __be64 lemFir;                          /* C00 */
877         __be64 lemErrorMask;                    /* C18 */
878         __be64 lemWOF;                          /* C40 */
879         __be64 phbErrorStatus;                  /* C80 */
880         __be64 phbFirstErrorStatus;             /* C88 */
881         __be64 phbErrorLog0;                    /* CC0 */
882         __be64 phbErrorLog1;                    /* CC8 */
883         __be64 phbTxeErrorStatus;               /* D00 */
884         __be64 phbTxeFirstErrorStatus;          /* D08 */
885         __be64 phbTxeErrorLog0;                 /* D40 */
886         __be64 phbTxeErrorLog1;                 /* D48 */
887         __be64 phbRxeArbErrorStatus;            /* D80 */
888         __be64 phbRxeArbFirstErrorStatus;       /* D88 */
889         __be64 phbRxeArbErrorLog0;              /* DC0 */
890         __be64 phbRxeArbErrorLog1;              /* DC8 */
891         __be64 phbRxeMrgErrorStatus;            /* E00 */
892         __be64 phbRxeMrgFirstErrorStatus;       /* E08 */
893         __be64 phbRxeMrgErrorLog0;              /* E40 */
894         __be64 phbRxeMrgErrorLog1;              /* E48 */
895         __be64 phbRxeTceErrorStatus;            /* E80 */
896         __be64 phbRxeTceFirstErrorStatus;       /* E88 */
897         __be64 phbRxeTceErrorLog0;              /* EC0 */
898         __be64 phbRxeTceErrorLog1;              /* EC8 */
899
900         /* PHB4 REGB Error Regs */
901         __be64 phbPblErrorStatus;               /* 1900 */
902         __be64 phbPblFirstErrorStatus;          /* 1908 */
903         __be64 phbPblErrorLog0;                 /* 1940 */
904         __be64 phbPblErrorLog1;                 /* 1948 */
905         __be64 phbPcieDlpErrorLog1;             /* 1AA0 */
906         __be64 phbPcieDlpErrorLog2;             /* 1AA8 */
907         __be64 phbPcieDlpErrorStatus;           /* 1AB0 */
908         __be64 phbRegbErrorStatus;              /* 1C00 */
909         __be64 phbRegbFirstErrorStatus;         /* 1C08 */
910         __be64 phbRegbErrorLog0;                /* 1C40 */
911         __be64 phbRegbErrorLog1;                /* 1C48 */
912
913         __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
914         __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
915 };
916
917 enum {
918         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
919         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
920
921         /* These two define the base MMU mode of the host on P9
922          *
923          * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
924          * create hash guests in "radix" mode with care (full core
925          * switch only).
926          */
927         OPAL_REINIT_CPUS_MMU_HASH       = (1 << 2),
928         OPAL_REINIT_CPUS_MMU_RADIX      = (1 << 3),
929
930         OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
931 };
932
933 typedef struct oppanel_line {
934         __be64 line;
935         __be64 line_len;
936 } oppanel_line_t;
937
938 enum opal_prd_msg_type {
939         OPAL_PRD_MSG_TYPE_INIT = 0,     /* HBRT --> OPAL */
940         OPAL_PRD_MSG_TYPE_FINI,         /* HBRT/kernel --> OPAL */
941         OPAL_PRD_MSG_TYPE_ATTN,         /* HBRT <-- OPAL */
942         OPAL_PRD_MSG_TYPE_ATTN_ACK,     /* HBRT --> OPAL */
943         OPAL_PRD_MSG_TYPE_OCC_ERROR,    /* HBRT <-- OPAL */
944         OPAL_PRD_MSG_TYPE_OCC_RESET,    /* HBRT <-- OPAL */
945 };
946
947 struct opal_prd_msg_header {
948         uint8_t         type;
949         uint8_t         pad[1];
950         __be16          size;
951 };
952
953 struct opal_prd_msg;
954
955 #define OCC_RESET                       0
956 #define OCC_LOAD                        1
957 #define OCC_THROTTLE                    2
958 #define OCC_MAX_THROTTLE_STATUS         5
959
960 struct opal_occ_msg {
961         __be64 type;
962         __be64 chip;
963         __be64 throttle_status;
964 };
965
966 /*
967  * SG entries
968  *
969  * WARNING: The current implementation requires each entry
970  * to represent a block that is 4k aligned *and* each block
971  * size except the last one in the list to be as well.
972  */
973 struct opal_sg_entry {
974         __be64 data;
975         __be64 length;
976 };
977
978 /*
979  * Candidate image SG list.
980  *
981  * length = VER | length
982  */
983 struct opal_sg_list {
984         __be64 length;
985         __be64 next;
986         struct opal_sg_entry entry[];
987 };
988
989 /*
990  * Dump region ID range usable by the OS
991  */
992 #define OPAL_DUMP_REGION_HOST_START             0x80
993 #define OPAL_DUMP_REGION_LOG_BUF                0x80
994 #define OPAL_DUMP_REGION_HOST_END               0xFF
995
996 /* CAPI modes for PHB */
997 enum {
998         OPAL_PHB_CAPI_MODE_PCIE         = 0,
999         OPAL_PHB_CAPI_MODE_CAPI         = 1,
1000         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
1001         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
1002         OPAL_PHB_CAPI_MODE_DMA          = 4,
1003         OPAL_PHB_CAPI_MODE_DMA_TVT1     = 5,
1004 };
1005
1006 /* OPAL I2C request */
1007 struct opal_i2c_request {
1008         uint8_t type;
1009 #define OPAL_I2C_RAW_READ       0
1010 #define OPAL_I2C_RAW_WRITE      1
1011 #define OPAL_I2C_SM_READ        2
1012 #define OPAL_I2C_SM_WRITE       3
1013         uint8_t flags;
1014 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
1015         uint8_t subaddr_sz;             /* Max 4 */
1016         uint8_t reserved;
1017         __be16 addr;                    /* 7 or 10 bit address */
1018         __be16 reserved2;
1019         __be32 subaddr;         /* Sub-address if any */
1020         __be32 size;                    /* Data size */
1021         __be64 buffer_ra;               /* Buffer real address */
1022 };
1023
1024 /*
1025  * EPOW status sharing (OPAL and the host)
1026  *
1027  * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
1028  * with individual elements being 16 bits wide to fetch the system
1029  * wide EPOW status. Each element in the buffer will contain the
1030  * EPOW status in it's bit representation for a particular EPOW sub
1031  * class as defined here. So multiple detailed EPOW status bits
1032  * specific for any sub class can be represented in a single buffer
1033  * element as it's bit representation.
1034  */
1035
1036 /* System EPOW type */
1037 enum OpalSysEpow {
1038         OPAL_SYSEPOW_POWER      = 0,    /* Power EPOW */
1039         OPAL_SYSEPOW_TEMP       = 1,    /* Temperature EPOW */
1040         OPAL_SYSEPOW_COOLING    = 2,    /* Cooling EPOW */
1041         OPAL_SYSEPOW_MAX        = 3,    /* Max EPOW categories */
1042 };
1043
1044 /* Power EPOW */
1045 enum OpalSysPower {
1046         OPAL_SYSPOWER_UPS       = 0x0001, /* System on UPS power */
1047         OPAL_SYSPOWER_CHNG      = 0x0002, /* System power config change */
1048         OPAL_SYSPOWER_FAIL      = 0x0004, /* System impending power failure */
1049         OPAL_SYSPOWER_INCL      = 0x0008, /* System incomplete power */
1050 };
1051
1052 /* Temperature EPOW */
1053 enum OpalSysTemp {
1054         OPAL_SYSTEMP_AMB        = 0x0001, /* System over ambient temperature */
1055         OPAL_SYSTEMP_INT        = 0x0002, /* System over internal temperature */
1056         OPAL_SYSTEMP_HMD        = 0x0004, /* System over ambient humidity */
1057 };
1058
1059 /* Cooling EPOW */
1060 enum OpalSysCooling {
1061         OPAL_SYSCOOL_INSF       = 0x0001, /* System insufficient cooling */
1062 };
1063
1064 /* Argument to OPAL_CEC_REBOOT2() */
1065 enum {
1066         OPAL_REBOOT_NORMAL              = 0,
1067         OPAL_REBOOT_PLATFORM_ERROR      = 1,
1068         OPAL_REBOOT_FULL_IPL            = 2,
1069         OPAL_REBOOT_MPIPL               = 3,
1070         OPAL_REBOOT_FAST                = 4,
1071 };
1072
1073 /* Argument to OPAL_PCI_TCE_KILL */
1074 enum {
1075         OPAL_PCI_TCE_KILL_PAGES,
1076         OPAL_PCI_TCE_KILL_PE,
1077         OPAL_PCI_TCE_KILL_ALL,
1078 };
1079
1080 /* The xive operation mode indicates the active "API" and
1081  * corresponds to the "mode" parameter of the opal_xive_reset()
1082  * call
1083  */
1084 enum {
1085         OPAL_XIVE_MODE_EMU      = 0,
1086         OPAL_XIVE_MODE_EXPL     = 1,
1087 };
1088
1089 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1090 enum {
1091         OPAL_XIVE_IRQ_TRIGGER_PAGE      = 0x00000001,
1092         OPAL_XIVE_IRQ_STORE_EOI         = 0x00000002,
1093         OPAL_XIVE_IRQ_LSI               = 0x00000004,
1094         OPAL_XIVE_IRQ_SHIFT_BUG         = 0x00000008,
1095         OPAL_XIVE_IRQ_MASK_VIA_FW       = 0x00000010,
1096         OPAL_XIVE_IRQ_EOI_VIA_FW        = 0x00000020,
1097 };
1098
1099 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1100 enum {
1101         OPAL_XIVE_EQ_ENABLED            = 0x00000001,
1102         OPAL_XIVE_EQ_ALWAYS_NOTIFY      = 0x00000002,
1103         OPAL_XIVE_EQ_ESCALATE           = 0x00000004,
1104 };
1105
1106 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1107 enum {
1108         OPAL_XIVE_VP_ENABLED            = 0x00000001,
1109         OPAL_XIVE_VP_SINGLE_ESCALATION  = 0x00000002,
1110 };
1111
1112 /* "Any chip" replacement for chip ID for allocation functions */
1113 enum {
1114         OPAL_XIVE_ANY_CHIP              = 0xffffffff,
1115 };
1116
1117 /* Xive sync options */
1118 enum {
1119         /* This bits are cumulative, arg is a girq */
1120         XIVE_SYNC_EAS                   = 0x00000001, /* Sync irq source */
1121         XIVE_SYNC_QUEUE                 = 0x00000002, /* Sync irq target */
1122 };
1123
1124 /* Dump options */
1125 enum {
1126         XIVE_DUMP_TM_HYP        = 0,
1127         XIVE_DUMP_TM_POOL       = 1,
1128         XIVE_DUMP_TM_OS         = 2,
1129         XIVE_DUMP_TM_USER       = 3,
1130         XIVE_DUMP_VP            = 4,
1131         XIVE_DUMP_EMU_STATE     = 5,
1132 };
1133
1134 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
1135 enum {
1136         OPAL_IMC_COUNTERS_NEST = 1,
1137         OPAL_IMC_COUNTERS_CORE = 2,
1138         OPAL_IMC_COUNTERS_TRACE = 3,
1139 };
1140
1141
1142 /* PCI p2p descriptor */
1143 #define OPAL_PCI_P2P_ENABLE             0x1
1144 #define OPAL_PCI_P2P_LOAD               0x2
1145 #define OPAL_PCI_P2P_STORE              0x4
1146
1147 /* MPIPL update operations */
1148 enum opal_mpipl_ops {
1149         OPAL_MPIPL_ADD_RANGE                    = 0,
1150         OPAL_MPIPL_REMOVE_RANGE                 = 1,
1151         OPAL_MPIPL_REMOVE_ALL                   = 2,
1152         OPAL_MPIPL_FREE_PRESERVED_MEMORY        = 3,
1153 };
1154
1155 /* Tag will point to various metadata area. Kernel will
1156  * use tag to get metadata value.
1157  */
1158 enum opal_mpipl_tags {
1159         OPAL_MPIPL_TAG_CPU      = 0,
1160         OPAL_MPIPL_TAG_OPAL     = 1,
1161         OPAL_MPIPL_TAG_KERNEL   = 2,
1162         OPAL_MPIPL_TAG_BOOT_MEM = 3,
1163 };
1164
1165 /* Preserved memory details */
1166 struct opal_mpipl_region {
1167         __be64  src;
1168         __be64  dest;
1169         __be64  size;
1170 };
1171
1172 /* Structure version */
1173 #define OPAL_MPIPL_VERSION              0x01
1174
1175 struct opal_mpipl_fadump {
1176         u8      version;
1177         u8      reserved[7];
1178         __be32  crashing_pir;   /* OPAL crashing CPU PIR */
1179         __be32  cpu_data_version;
1180         __be32  cpu_data_size;
1181         __be32  region_cnt;
1182         struct  opal_mpipl_region region[];
1183 } __packed;
1184
1185 #endif /* __ASSEMBLY__ */
1186
1187 #endif /* __OPAL_API_H */