1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_MMU_H_
3 #define _ASM_POWERPC_MMU_H_
6 #include <linux/types.h>
8 #include <asm/asm-const.h>
11 * MMU features bit definitions
17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
24 /* Radix page table supported and enabled */
25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
28 * Individual features below.
32 * Support for 68 bit VA space. We added that from ISA 2.05
34 #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000)
36 * Kernel read only support.
37 * We added the ppp value 0b110 in ISA 2.04.
39 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
42 * We need to clear top 16bits of va (from the remaining 64 bits )in
45 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
47 /* Enable use of high BAT registers */
48 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
50 /* Enable >32-bit physical addresses on 32-bit processor, only used
51 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
53 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
55 /* Enable use of broadcast TLB invalidations. We don't always set it
56 * on processors that support it due to other constraints with the
57 * use of such invalidations
59 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
61 /* Enable use of tlbilx invalidate instructions.
63 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
65 /* This indicates that the processor cannot handle multiple outstanding
66 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
67 * around such invalidate forms.
69 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
71 /* This indicates that the processor doesn't handle way selection
72 * properly and needs SW to track and update the LRU state. This
73 * is specific to an errata on e300c2/c3/c4 class parts
75 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
77 /* Enable use of TLB reservation. Processor should support tlbsrx.
78 * instruction and MAS0[WQ].
80 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
82 /* Use paired MAS registers (MAS7||MAS3, etc.)
84 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
86 /* Doesn't support the B bit (1T segment) in SLBIE
88 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
90 /* Support 16M large pages
92 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
94 /* Supports TLBIEL variant
96 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
98 /* Supports tlbies w/o locking
100 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
102 /* Large pages can be marked CI
104 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
106 /* 1T segments available
108 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
110 /* MMU feature bit sets for various CPUs */
111 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
112 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
113 #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2
114 #define MMU_FTRS_PPC970 MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA
115 #define MMU_FTRS_POWER5 MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE
116 #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
117 #define MMU_FTRS_POWER7 MMU_FTRS_POWER6
118 #define MMU_FTRS_POWER8 MMU_FTRS_POWER6
119 #define MMU_FTRS_POWER9 MMU_FTRS_POWER6
120 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
121 MMU_FTR_CI_LARGE_PAGE
122 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
123 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
125 #include <linux/bug.h>
126 #include <asm/cputable.h>
128 #ifdef CONFIG_PPC_FSL_BOOK3E
129 #include <asm/percpu.h>
130 DECLARE_PER_CPU(int, next_tlbcam_idx);
135 #ifdef CONFIG_PPC_BOOK3S
138 #ifdef CONFIG_PPC_8xx
147 #if defined(CONFIG_E200) || defined(CONFIG_E500)
148 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
150 #ifdef CONFIG_PPC_47x
151 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
153 #ifdef CONFIG_PPC_BOOK3S_32
154 MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU |
156 #ifdef CONFIG_PPC_BOOK3E_64
157 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
159 #ifdef CONFIG_PPC_BOOK3S_64
160 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
161 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
162 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
163 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
165 #ifdef CONFIG_PPC_RADIX_MMU
171 static inline bool early_mmu_has_feature(unsigned long feature)
173 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
176 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
177 #include <linux/jump_label.h>
179 #define NUM_MMU_FTR_KEYS 32
181 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
183 extern void mmu_feature_keys_init(void);
185 static __always_inline bool mmu_has_feature(unsigned long feature)
189 #ifndef __clang__ /* clang can't cope with this */
190 BUILD_BUG_ON(!__builtin_constant_p(feature));
193 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
194 if (!static_key_initialized) {
195 printk("Warning! mmu_has_feature() used prior to jump label init!\n");
197 return early_mmu_has_feature(feature);
201 if (!(MMU_FTRS_POSSIBLE & feature))
204 i = __builtin_ctzl(feature);
205 return static_branch_likely(&mmu_feature_keys[i]);
208 static inline void mmu_clear_feature(unsigned long feature)
212 i = __builtin_ctzl(feature);
213 cur_cpu_spec->mmu_features &= ~feature;
214 static_branch_disable(&mmu_feature_keys[i]);
218 static inline void mmu_feature_keys_init(void)
223 static inline bool mmu_has_feature(unsigned long feature)
225 return early_mmu_has_feature(feature);
228 static inline void mmu_clear_feature(unsigned long feature)
230 cur_cpu_spec->mmu_features &= ~feature;
232 #endif /* CONFIG_JUMP_LABEL */
234 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
237 /* This is our real memory area size on ppc64 server, on embedded, we
238 * make it match the size our of bolted TLB area
240 extern u64 ppc64_rma_size;
242 /* Cleanup function used by kexec */
243 extern void mmu_cleanup_all(void);
244 extern void radix__mmu_cleanup_all(void);
246 /* Functions for creating and updating partition table on POWER9 */
247 extern void mmu_partition_table_init(void);
248 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
250 #endif /* CONFIG_PPC64 */
253 #ifdef CONFIG_DEBUG_VM
254 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
255 #else /* CONFIG_DEBUG_VM */
256 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
259 #endif /* !CONFIG_DEBUG_VM */
261 #ifdef CONFIG_PPC_RADIX_MMU
262 static inline bool radix_enabled(void)
264 return mmu_has_feature(MMU_FTR_TYPE_RADIX);
267 static inline bool early_radix_enabled(void)
269 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
272 static inline bool radix_enabled(void)
277 static inline bool early_radix_enabled(void)
283 #ifdef CONFIG_PPC_MEM_KEYS
284 extern u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address);
286 static inline u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
290 #endif /* CONFIG_PPC_MEM_KEYS */
292 #endif /* !__ASSEMBLY__ */
294 /* The kernel use the constants below to index in the page sizes array.
295 * The use of fixed constants for this purpose is better for performances
296 * of the low level hash refill handlers.
298 * A non supported page size has a "shift" field set to 0
300 * Any new page size being implemented can get a new entry in here. Whether
301 * the kernel will use it or not is a different matter though. The actual page
302 * size used by hugetlbfs is not defined here and may be made variable
304 * Note: This array ended up being a false good idea as it's growing to the
305 * point where I wonder if we should replace it with something different,
306 * to think about, feedback welcome. --BenH.
309 /* These are #defines as they have to be used in assembly */
310 #define MMU_PAGE_4K 0
311 #define MMU_PAGE_16K 1
312 #define MMU_PAGE_64K 2
313 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
314 #define MMU_PAGE_256K 4
315 #define MMU_PAGE_512K 5
316 #define MMU_PAGE_1M 6
317 #define MMU_PAGE_2M 7
318 #define MMU_PAGE_4M 8
319 #define MMU_PAGE_8M 9
320 #define MMU_PAGE_16M 10
321 #define MMU_PAGE_64M 11
322 #define MMU_PAGE_256M 12
323 #define MMU_PAGE_1G 13
324 #define MMU_PAGE_16G 14
325 #define MMU_PAGE_64G 15
328 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
329 * Also we need to change he type of mm_context.low/high_slices_psize.
331 #define MMU_PAGE_COUNT 16
334 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
335 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
336 * page_to_nid does a page->section->node lookup
337 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
338 * memory requirements with large number of sections.
339 * 51 bits is the max physical real address on POWER9
341 #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \
342 defined (CONFIG_PPC_64K_PAGES)
343 #define MAX_PHYSMEM_BITS 51
345 #define MAX_PHYSMEM_BITS 46
348 #ifdef CONFIG_PPC_BOOK3S_64
349 #include <asm/book3s/64/mmu.h>
350 #else /* CONFIG_PPC_BOOK3S_64 */
353 /* MMU initialization */
354 extern void early_init_mmu(void);
355 extern void early_init_mmu_secondary(void);
356 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
357 phys_addr_t first_memblock_size);
358 static inline void mmu_early_init_devtree(void) { }
359 #endif /* __ASSEMBLY__ */
362 #if defined(CONFIG_PPC_BOOK3S_32)
363 /* 32-bit classic hash table MMU */
364 #include <asm/book3s/32/mmu-hash.h>
365 #elif defined(CONFIG_PPC_MMU_NOHASH)
366 #include <asm/nohash/mmu.h>
369 #endif /* __KERNEL__ */
370 #endif /* _ASM_POWERPC_MMU_H_ */