1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_POWERPC_CPUTABLE_H
3 #define __ASM_POWERPC_CPUTABLE_H
6 #include <linux/types.h>
7 #include <uapi/asm/cputable.h>
8 #include <asm/asm-const.h>
13 * Added to include __machine_check_early_realmode_* functions
17 /* This structure can grow, it's real size is used by head.S code
18 * via the mkdefs mechanism.
22 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
23 typedef void (*cpu_restore_t)(void);
25 enum powerpc_oprofile_type {
26 PPC_OPROFILE_INVALID = 0,
27 PPC_OPROFILE_RS64 = 1,
28 PPC_OPROFILE_POWER4 = 2,
30 PPC_OPROFILE_FSL_EMB = 4,
31 PPC_OPROFILE_CELL = 5,
32 PPC_OPROFILE_PA6T = 6,
35 enum powerpc_pmc_type {
44 extern int machine_check_generic(struct pt_regs *regs);
45 extern int machine_check_4xx(struct pt_regs *regs);
46 extern int machine_check_440A(struct pt_regs *regs);
47 extern int machine_check_e500mc(struct pt_regs *regs);
48 extern int machine_check_e500(struct pt_regs *regs);
49 extern int machine_check_e200(struct pt_regs *regs);
50 extern int machine_check_47x(struct pt_regs *regs);
51 int machine_check_8xx(struct pt_regs *regs);
52 int machine_check_83xx(struct pt_regs *regs);
54 extern void cpu_down_flush_e500v2(void);
55 extern void cpu_down_flush_e500mc(void);
56 extern void cpu_down_flush_e5500(void);
57 extern void cpu_down_flush_e6500(void);
59 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
61 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
62 unsigned int pvr_mask;
63 unsigned int pvr_value;
66 unsigned long cpu_features; /* Kernel features */
67 unsigned int cpu_user_features; /* Userland features */
68 unsigned int cpu_user_features2; /* Userland features v2 */
69 unsigned int mmu_features; /* MMU features */
71 /* cache line sizes */
72 unsigned int icache_bsize;
73 unsigned int dcache_bsize;
75 /* flush caches inside the current cpu */
76 void (*cpu_down_flush)(void);
78 /* number of performance monitor counters */
79 unsigned int num_pmcs;
80 enum powerpc_pmc_type pmc_type;
82 /* this is called to initialize various CPU bits like L1 cache,
83 * BHT, SPD, etc... from head.S before branching to identify_machine
85 cpu_setup_t cpu_setup;
86 /* Used to restore cpu setup on secondary processors and at resume */
87 cpu_restore_t cpu_restore;
89 /* Used by oprofile userspace to select the right counters */
90 char *oprofile_cpu_type;
92 /* Processor specific oprofile operations */
93 enum powerpc_oprofile_type oprofile_type;
95 /* Bit locations inside the mmcra change */
96 unsigned long oprofile_mmcra_sihv;
97 unsigned long oprofile_mmcra_sipr;
99 /* Bits to clear during an oprofile exception */
100 unsigned long oprofile_mmcra_clear;
102 /* Name of processor class, for the ELF AT_PLATFORM entry */
105 /* Processor specific machine check handling. Return negative
106 * if the error is fatal, 1 if it was fully recovered and 0 to
107 * pass up (not CPU originated) */
108 int (*machine_check)(struct pt_regs *regs);
111 * Processor specific early machine check handler which is
112 * called in real mode to handle SLB and TLB errors.
114 long (*machine_check_early)(struct pt_regs *regs);
117 extern struct cpu_spec *cur_cpu_spec;
119 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
121 extern void set_cur_cpu_spec(struct cpu_spec *s);
122 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
123 extern void identify_cpu_name(unsigned int pvr);
124 extern void do_feature_fixups(unsigned long value, void *fixup_start,
127 extern const char *powerpc_base_platform;
129 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
130 extern void cpu_feature_keys_init(void);
132 static inline void cpu_feature_keys_init(void) { }
135 #endif /* __ASSEMBLY__ */
137 /* CPU kernel features */
139 /* Definitions for features that we have on both 32-bit and 64-bit chips */
140 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
141 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
142 #define CPU_FTR_DBELL ASM_CONST(0x00000004)
143 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
144 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
145 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
146 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
147 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
148 #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
149 #define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
151 /* Definitions for features that only exist on 32-bit chips */
153 #define CPU_FTR_L2CR ASM_CONST(0x00002000)
154 #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
155 #define CPU_FTR_TAU ASM_CONST(0x00008000)
156 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
157 #define CPU_FTR_L3CR ASM_CONST(0x00040000)
158 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
159 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
160 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
161 #define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
162 #define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
163 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
164 #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
165 #define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
166 #define CPU_FTR_SPE ASM_CONST(0x10000000)
167 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
168 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
170 #else /* CONFIG_PPC32 */
171 /* Define these to 0 for the sake of tests in common code */
172 #define CPU_FTR_PPC_LE (0)
176 * Definitions for the 64-bit processor unique features;
177 * on 32-bit, make the names available but defined to be 0.
180 #define LONG_ASM_CONST(x) ASM_CONST(x)
182 #define LONG_ASM_CONST(x) 0
185 #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
186 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
187 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
188 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
189 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
190 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
191 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
192 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
193 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
194 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
195 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
196 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
197 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
198 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
199 // Free LONG_ASM_CONST(0x0000000008000000)
200 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
201 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
202 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
203 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
204 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
205 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
206 /* LONG_ASM_CONST(0x0000000400000000) Free */
207 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
208 #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
209 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
210 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
211 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
212 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
213 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
214 #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
215 #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
216 #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
217 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
218 #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
219 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
220 #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
221 #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
222 #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
226 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
228 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
230 /* We only set the altivec features if the kernel was compiled with altivec
233 #ifdef CONFIG_ALTIVEC
234 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
235 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
237 #define CPU_FTR_ALTIVEC_COMP 0
238 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
241 /* We only set the VSX features if the kernel was compiled with VSX
245 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
246 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
248 #define CPU_FTR_VSX_COMP 0
249 #define PPC_FEATURE_HAS_VSX_COMP 0
252 /* We only set the spe features if the kernel was compiled with spe
256 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
257 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
258 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
259 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
261 #define CPU_FTR_SPE_COMP 0
262 #define PPC_FEATURE_HAS_SPE_COMP 0
263 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
264 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
267 /* We only set the TM feature if the kernel was compiled with TM supprt */
268 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
269 #define CPU_FTR_TM_COMP CPU_FTR_TM
270 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
271 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
273 #define CPU_FTR_TM_COMP 0
274 #define PPC_FEATURE2_HTM_COMP 0
275 #define PPC_FEATURE2_HTM_NOSC_COMP 0
278 /* We need to mark all pages as being coherent if we're SMP or we have a
279 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
280 * require it for PCI "streaming/prefetch" to work properly.
281 * This is also required by 52xx family.
283 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
284 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
285 || defined(CONFIG_PPC_MPC52xx)
286 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
288 #define CPU_FTR_COMMON 0
291 /* The powersave features NAP & DOZE seems to confuse BDI when
292 debugging. So if a BDI is used, disable theses
294 #ifndef CONFIG_BDI_SWITCH
295 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
296 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
298 #define CPU_FTR_MAYBE_CAN_DOZE 0
299 #define CPU_FTR_MAYBE_CAN_NAP 0
302 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \
303 CPU_FTR_COHERENT_ICACHE)
304 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
306 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
307 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
308 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
310 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
311 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
312 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
314 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
316 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
318 #define CPU_FTRS_750CL (CPU_FTRS_750)
319 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
320 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
321 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
322 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
323 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
324 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
325 CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
327 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
328 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
329 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
331 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
332 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
333 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
335 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
338 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
339 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
340 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
341 CPU_FTR_NEED_PAIRED_STWCX | \
342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
343 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
345 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
346 CPU_FTR_NEED_PAIRED_STWCX | \
347 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
348 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
349 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
350 CPU_FTR_NEED_PAIRED_STWCX | \
351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
353 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
354 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
355 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
359 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
361 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
362 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
363 CPU_FTR_NEED_PAIRED_STWCX)
364 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
365 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
366 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
367 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
368 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
369 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
370 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
371 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
372 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
373 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
374 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
375 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
376 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
377 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
378 CPU_FTR_MAYBE_CAN_NAP)
379 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
380 CPU_FTR_MAYBE_CAN_NAP | \
381 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
382 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
383 CPU_FTR_MAYBE_CAN_NAP | \
384 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
385 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
386 #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
387 #define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
388 #define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
389 #define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
391 #define CPU_FTRS_47X (CPU_FTRS_440x6)
392 #define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
393 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
394 CPU_FTR_NOEXECUTE | \
395 CPU_FTR_DEBUG_LVL_EXC)
396 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
397 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
399 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
400 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
401 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
402 #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
403 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
404 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
406 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
407 * same workaround as CPU_FTR_CELL_TB_BUG.
409 #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
410 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
411 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
412 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
413 #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
414 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
415 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
416 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
417 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
418 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
421 #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
423 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
424 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
425 CPU_FTR_HVMODE | CPU_FTR_DABRX)
426 #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
428 CPU_FTR_MMCRA | CPU_FTR_SMT | \
429 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
430 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
431 #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
432 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
433 CPU_FTR_MMCRA | CPU_FTR_SMT | \
434 CPU_FTR_COHERENT_ICACHE | \
435 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
436 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
437 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
439 #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
440 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
441 CPU_FTR_MMCRA | CPU_FTR_SMT | \
442 CPU_FTR_COHERENT_ICACHE | \
443 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
444 CPU_FTR_DSCR | CPU_FTR_ASYM_SMT | \
445 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
446 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
447 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
448 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
449 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
450 CPU_FTR_MMCRA | CPU_FTR_SMT | \
451 CPU_FTR_COHERENT_ICACHE | \
452 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
454 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
455 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
456 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
457 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
458 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
459 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
460 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
462 CPU_FTR_COHERENT_ICACHE | \
463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
466 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
468 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
469 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
470 #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
471 #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
472 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
473 CPU_FTR_POWER9_DD2_1)
474 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
475 CPU_FTR_P9_TM_HV_ASSIST | \
476 CPU_FTR_P9_TM_XER_SO_BUG)
477 #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
478 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
479 CPU_FTR_MMCRA | CPU_FTR_SMT | \
480 CPU_FTR_COHERENT_ICACHE | \
481 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
483 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
484 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
485 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
486 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
487 CPU_FTR_DAWR | CPU_FTR_DAWR1)
488 #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
489 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
490 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
491 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
492 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
493 #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
494 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
495 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
496 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
499 #ifdef CONFIG_PPC_BOOK3E
500 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
502 #ifdef CONFIG_CPU_LITTLE_ENDIAN
503 #define CPU_FTRS_POSSIBLE \
504 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
505 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
506 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
508 #define CPU_FTRS_POSSIBLE \
509 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
510 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
511 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
512 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
513 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
514 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
519 #ifdef CONFIG_PPC_BOOK3S_601
521 #elif defined(CONFIG_PPC_BOOK3S_32)
522 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
523 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
524 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
525 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
526 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
527 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
528 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
529 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
532 CPU_FTRS_GENERIC_32 |
534 #ifdef CONFIG_PPC_8xx
541 CPU_FTRS_44X | CPU_FTRS_440x6 |
543 #ifdef CONFIG_PPC_47x
544 CPU_FTRS_47X | CPU_FTR_476_DD2 |
550 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
552 #ifdef CONFIG_PPC_E500MC
553 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
557 #endif /* __powerpc64__ */
560 #ifdef CONFIG_PPC_BOOK3E
561 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
564 #ifdef CONFIG_PPC_DT_CPU_FTRS
565 #define CPU_FTRS_DT_CPU_BASE \
567 CPU_FTR_FPU_UNAVAILABLE | \
568 CPU_FTR_NODSISRALIGN | \
569 CPU_FTR_NOEXECUTE | \
570 CPU_FTR_COHERENT_ICACHE | \
571 CPU_FTR_STCX_CHECKS_ADDRESS | \
572 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
577 #define CPU_FTRS_DT_CPU_BASE (~0ul)
580 #ifdef CONFIG_CPU_LITTLE_ENDIAN
581 #define CPU_FTRS_ALWAYS \
582 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
583 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
584 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
586 #define CPU_FTRS_ALWAYS \
587 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
588 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
589 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
590 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
591 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
592 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
597 #ifdef CONFIG_PPC_BOOK3S_601
599 #elif defined(CONFIG_PPC_BOOK3S_32)
600 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
601 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
602 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
603 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
604 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
605 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
606 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
607 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
610 CPU_FTRS_GENERIC_32 &
612 #ifdef CONFIG_PPC_8xx
619 CPU_FTRS_44X & CPU_FTRS_440x6 &
625 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
627 #ifdef CONFIG_PPC_E500MC
628 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
630 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
633 #endif /* __powerpc64__ */
636 * Maximum number of hw breakpoint supported on powerpc. Number of
637 * breakpoints supported by actual hw might be less than this, which
638 * is decided at run time in nr_wp_slots().
640 #define HBP_NUM_MAX 2
642 #endif /* !__ASSEMBLY__ */
644 #endif /* __ASM_POWERPC_CPUTABLE_H */