1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
5 #include <asm-generic/pgtable-nop4d.h>
8 #include <linux/mmdebug.h>
10 #include <linux/sizes.h>
14 * Common bits between hash and Radix page table
17 #define _PAGE_EXEC 0x00001 /* execute permission */
18 #define _PAGE_WRITE 0x00002 /* write access allowed */
19 #define _PAGE_READ 0x00004 /* read access allowed */
20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
23 #define _PAGE_SAO 0x00010 /* Strong access order */
24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
26 #define _PAGE_DIRTY 0x00080 /* C: page changed */
27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */
31 #define _RPAGE_SW0 0x2000000000000000UL
32 #define _RPAGE_SW1 0x00800
33 #define _RPAGE_SW2 0x00400
34 #define _RPAGE_SW3 0x00200
35 #define _RPAGE_RSV1 0x00040UL
37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL
38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL
39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL
40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL
41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL
43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing
47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to
48 * differentiate between two use a SW field when invalidating.
50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags
52 * This is used only when _PAGE_PRESENT is cleared.
54 #define _PAGE_INVALID _RPAGE_SW0
57 * Top and bottom bits of RPN which can be used by hash
58 * translation mode, because we expect them to be zero
61 #define _RPAGE_RPN0 0x01000
62 #define _RPAGE_RPN1 0x02000
63 #define _RPAGE_RPN43 0x0080000000000000UL
64 #define _RPAGE_RPN42 0x0040000000000000UL
65 #define _RPAGE_RPN41 0x0020000000000000UL
67 /* Max physical address bit as per radix table */
68 #define _RPAGE_PA_MAX 56
71 * Max physical address bit we will use for now.
73 * This is mostly a hardware limitation and for now Power9 has
76 * This is different from the number of physical bit required to address
77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
79 * number of sections we can support (SECTIONS_SHIFT).
81 * This is different from Radix page table limitation above and
82 * should always be less than that. The limit is done such that
83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
84 * for hash linux page table specific bits.
86 * In order to be compatible with future hardware generations we keep
87 * some offsets and limit this for now to 53
89 #define _PAGE_PA_MAX 53
91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
97 * Instead of fixing all of them, add an alternate define which
98 * maps CI pte mapping.
100 #define _PAGE_NO_CACHE _PAGE_TOLERANT
102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
104 * and every thing below PAGE_SHIFT;
106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
107 #define PTE_RPN_SHIFT PAGE_SHIFT
109 * set of bits not changed in pmd_modify. Even though we have hash specific bits
110 * in here, on radix we expect them to be zero.
112 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
113 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
114 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
116 * user access blocked by key
118 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
119 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
120 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC)
121 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
123 * _PAGE_CHG_MASK masks of bits that are to be preserved across
126 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
131 * We define 2 sets of base prot bits, one for basic pages (ie,
132 * cacheable kernel and user pages) and one for non cacheable
133 * pages. We always set _PAGE_COHERENT when SMP is enabled or
134 * the processor might need it for DMA coherency.
136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
137 #define _PAGE_BASE (_PAGE_BASE_NC)
139 /* Permission masks used to generate the __P and __S table,
141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
143 * Write permissions imply read permissions for now (we could make write-only
144 * pages on BookE but we don't bother for now). Execute permission control is
145 * possible on platforms that define _PAGE_EXEC
147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
154 /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */
155 #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC)
157 /* Permission masks used for kernel mappings */
158 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
159 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT)
160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT)
161 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
162 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
163 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
169 extern unsigned long __pte_index_size;
170 extern unsigned long __pmd_index_size;
171 extern unsigned long __pud_index_size;
172 extern unsigned long __pgd_index_size;
173 extern unsigned long __pud_cache_index;
174 #define PTE_INDEX_SIZE __pte_index_size
175 #define PMD_INDEX_SIZE __pmd_index_size
176 #define PUD_INDEX_SIZE __pud_index_size
177 #define PGD_INDEX_SIZE __pgd_index_size
178 /* pmd table use page table fragments */
179 #define PMD_CACHE_INDEX 0
180 #define PUD_CACHE_INDEX __pud_cache_index
182 * Because of use of pte fragments and THP, size of page table
183 * are not always derived out of index size above.
185 extern unsigned long __pte_table_size;
186 extern unsigned long __pmd_table_size;
187 extern unsigned long __pud_table_size;
188 extern unsigned long __pgd_table_size;
189 #define PTE_TABLE_SIZE __pte_table_size
190 #define PMD_TABLE_SIZE __pmd_table_size
191 #define PUD_TABLE_SIZE __pud_table_size
192 #define PGD_TABLE_SIZE __pgd_table_size
194 extern unsigned long __pmd_val_bits;
195 extern unsigned long __pud_val_bits;
196 extern unsigned long __pgd_val_bits;
197 #define PMD_VAL_BITS __pmd_val_bits
198 #define PUD_VAL_BITS __pud_val_bits
199 #define PGD_VAL_BITS __pgd_val_bits
201 extern unsigned long __pte_frag_nr;
202 #define PTE_FRAG_NR __pte_frag_nr
203 extern unsigned long __pte_frag_size_shift;
204 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
205 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
207 extern unsigned long __pmd_frag_nr;
208 #define PMD_FRAG_NR __pmd_frag_nr
209 extern unsigned long __pmd_frag_size_shift;
210 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
211 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
213 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
214 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
215 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
216 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
218 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE)
219 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD)
220 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD)
221 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \
222 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE))
224 /* PMD_SHIFT determines what a second-level page table entry can map */
225 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
226 #define PMD_SIZE (1UL << PMD_SHIFT)
227 #define PMD_MASK (~(PMD_SIZE-1))
229 /* PUD_SHIFT determines what a third-level page table entry can map */
230 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
231 #define PUD_SIZE (1UL << PUD_SHIFT)
232 #define PUD_MASK (~(PUD_SIZE-1))
234 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
235 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
236 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
237 #define PGDIR_MASK (~(PGDIR_SIZE-1))
239 /* Bits to mask out from a PMD to get to the PTE page */
240 #define PMD_MASKED_BITS 0xc0000000000000ffUL
241 /* Bits to mask out from a PUD to get to the PMD page */
242 #define PUD_MASKED_BITS 0xc0000000000000ffUL
243 /* Bits to mask out from a PGD to get to the PUD page */
244 #define P4D_MASKED_BITS 0xc0000000000000ffUL
247 * Used as an indicator for rcu callback functions
255 * Below are used with 4k page size and hugetlb
261 extern unsigned long __vmalloc_start;
262 extern unsigned long __vmalloc_end;
263 #define VMALLOC_START __vmalloc_start
264 #define VMALLOC_END __vmalloc_end
266 static inline unsigned int ioremap_max_order(void)
270 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */
272 #define IOREMAP_MAX_ORDER ioremap_max_order()
274 extern unsigned long __kernel_virt_start;
275 extern unsigned long __kernel_io_start;
276 extern unsigned long __kernel_io_end;
277 #define KERN_VIRT_START __kernel_virt_start
278 #define KERN_IO_START __kernel_io_start
279 #define KERN_IO_END __kernel_io_end
281 extern struct page *vmemmap;
282 extern unsigned long pci_io_base;
283 #endif /* __ASSEMBLY__ */
285 #include <asm/book3s/64/hash.h>
286 #include <asm/book3s/64/radix.h>
288 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS
289 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS
291 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS
295 #ifdef CONFIG_PPC_64K_PAGES
296 #include <asm/book3s/64/pgtable-64k.h>
298 #include <asm/book3s/64/pgtable-4k.h>
301 #include <asm/barrier.h>
303 * IO space itself carved into the PIO region (ISA and PHB IO space) and
306 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
307 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
308 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
310 #define FULL_IO_SIZE 0x80000000ul
311 #define ISA_IO_BASE (KERN_IO_START)
312 #define ISA_IO_END (KERN_IO_START + 0x10000ul)
313 #define PHB_IO_BASE (ISA_IO_END)
314 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
315 #define IOREMAP_BASE (PHB_IO_END)
316 #define IOREMAP_START (ioremap_bot)
317 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE)
318 #define FIXADDR_SIZE SZ_32M
323 * This is the default implementation of various PTE accessors, it's
324 * used in all cases except Book3S with 64K pages where we have a
325 * concept of sub-pages
329 #define __real_pte(e, p, o) ((real_pte_t){(e)})
330 #define __rpte_to_pte(r) ((r).pte)
331 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
333 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
336 shift = mmu_psize_defs[psize].shift; \
338 #define pte_iterate_hashed_end() } while(0)
341 * We expect this to be called only for user addresses or kernel virtual
342 * addresses other than the linear mapping.
344 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
346 #endif /* __real_pte */
348 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
349 pte_t *ptep, unsigned long clr,
350 unsigned long set, int huge)
353 return radix__pte_update(mm, addr, ptep, clr, set, huge);
354 return hash__pte_update(mm, addr, ptep, clr, set, huge);
357 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
358 * We currently remove entries from the hashtable regardless of whether
359 * the entry was young or dirty.
361 * We should be more intelligent about this but for the moment we override
362 * these functions and force a tlb flush unconditionally
363 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
364 * function for both hash and radix.
366 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
367 unsigned long addr, pte_t *ptep)
371 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
373 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
374 return (old & _PAGE_ACCESSED) != 0;
377 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
378 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
380 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
384 * On Book3S CPUs, clearing the accessed bit without a TLB flush
385 * doesn't cause data corruption. [ It could cause incorrect
386 * page aging and the (mistaken) reclaim of hot pages, but the
387 * chance of that should be relatively low. ]
389 * So as a performance optimization don't flush the TLB when
390 * clearing the accessed bit, it will eventually be flushed by
391 * a context switch or a VM operation anyway. [ In the rare
392 * event of it not getting flushed for a long time the delay
393 * shouldn't really matter because there's no real memory
394 * pressure for swapout to react to. ]
396 * Note: this optimisation also exists in pte_needs_flush() and
397 * huge_pmd_needs_flush().
399 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
400 #define ptep_clear_flush_young ptep_test_and_clear_young
402 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
403 #define pmdp_clear_flush_young pmdp_test_and_clear_young
405 static inline int pte_write(pte_t pte)
407 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
410 static inline int pte_read(pte_t pte)
412 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
415 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
416 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
419 if (pte_write(*ptep))
420 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
423 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
424 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
425 unsigned long addr, pte_t *ptep)
427 if (pte_write(*ptep))
428 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
431 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
432 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
433 unsigned long addr, pte_t *ptep)
435 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
439 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
440 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
442 pte_t *ptep, int full)
444 if (full && radix_enabled()) {
446 * We know that this is a full mm pte clear and
447 * hence can be sure there is no parallel set_pte.
449 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
451 return ptep_get_and_clear(mm, addr, ptep);
455 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
458 pte_update(mm, addr, ptep, ~0UL, 0, 0);
461 static inline int pte_dirty(pte_t pte)
463 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
466 static inline int pte_young(pte_t pte)
468 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
471 static inline int pte_special(pte_t pte)
473 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
476 static inline bool pte_exec(pte_t pte)
478 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC));
482 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
483 static inline bool pte_soft_dirty(pte_t pte)
485 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
488 static inline pte_t pte_mksoft_dirty(pte_t pte)
490 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY));
493 static inline pte_t pte_clear_soft_dirty(pte_t pte)
495 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY));
497 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
499 #ifdef CONFIG_NUMA_BALANCING
500 static inline int pte_protnone(pte_t pte)
502 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
503 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
505 #endif /* CONFIG_NUMA_BALANCING */
507 static inline bool pte_hw_valid(pte_t pte)
509 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) ==
510 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
513 static inline int pte_present(pte_t pte)
516 * A pte is considerent present if _PAGE_PRESENT is set.
517 * We also need to consider the pte present which is marked
518 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID
519 * if we find _PAGE_PRESENT cleared.
522 if (pte_hw_valid(pte))
524 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) ==
525 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE);
528 #ifdef CONFIG_PPC_MEM_KEYS
529 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
531 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
535 #endif /* CONFIG_PPC_MEM_KEYS */
537 static inline bool pte_user(pte_t pte)
539 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
542 #define pte_access_permitted pte_access_permitted
543 static inline bool pte_access_permitted(pte_t pte, bool write)
546 * _PAGE_READ is needed for any access and will be
547 * cleared for PROT_NONE
549 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
552 if (write && !pte_write(pte))
555 return arch_pte_access_permitted(pte_val(pte), write, 0);
559 * Conversion functions: convert a page and protection to a page entry,
560 * and a page entry and page directory to the page they refer to.
562 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
565 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
567 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT));
568 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK);
570 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE);
573 /* Generic modifiers for PTE bits */
574 static inline pte_t pte_wrprotect(pte_t pte)
576 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
579 static inline pte_t pte_exprotect(pte_t pte)
581 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC));
584 static inline pte_t pte_mkclean(pte_t pte)
586 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY));
589 static inline pte_t pte_mkold(pte_t pte)
591 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED));
594 static inline pte_t pte_mkexec(pte_t pte)
596 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC));
599 static inline pte_t pte_mkwrite_novma(pte_t pte)
602 * write implies read, hence set both
604 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW));
607 static inline pte_t pte_mkdirty(pte_t pte)
609 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
612 static inline pte_t pte_mkyoung(pte_t pte)
614 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED));
617 static inline pte_t pte_mkspecial(pte_t pte)
619 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL));
622 static inline pte_t pte_mkhuge(pte_t pte)
627 static inline pte_t pte_mkdevmap(pte_t pte)
629 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP));
632 static inline pte_t pte_mkprivileged(pte_t pte)
634 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED));
637 static inline pte_t pte_mkuser(pte_t pte)
639 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED));
643 * This is potentially called with a pmd as the argument, in which case it's not
644 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
645 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
646 * use in page directory entries (ie. non-ptes).
648 static inline int pte_devmap(pte_t pte)
650 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
652 return (pte_raw(pte) & mask) == mask;
655 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
657 /* FIXME!! check whether this need to be a conditional */
658 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) |
659 cpu_to_be64(pgprot_val(newprot)));
662 /* Encode and de-code a swap entry */
663 #define MAX_SWAPFILES_CHECK() do { \
664 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
666 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
667 * We filter HPTEFLAGS on set_pte. \
669 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \
670 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
671 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \
674 #define SWP_TYPE_BITS 5
675 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1)
676 #define __swp_type(x) ((x).val & SWP_TYPE_MASK)
677 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
678 #define __swp_entry(type, offset) ((swp_entry_t) { \
679 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
681 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
682 * swap type and offset we get from swap and convert that to pte to find a
683 * matching pte in linux page table.
684 * Clear bits not found in swap entries here.
686 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
687 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
688 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd)))
689 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x)))
691 #ifdef CONFIG_MEM_SOFT_DIRTY
692 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY
694 #define _PAGE_SWP_SOFT_DIRTY 0UL
695 #endif /* CONFIG_MEM_SOFT_DIRTY */
697 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT
699 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
700 static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
702 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
705 static inline bool pte_swp_soft_dirty(pte_t pte)
707 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
710 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
712 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY));
714 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
716 static inline pte_t pte_swp_mkexclusive(pte_t pte)
718 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
721 static inline int pte_swp_exclusive(pte_t pte)
723 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
726 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
728 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE));
731 static inline bool check_pte_access(unsigned long access, unsigned long ptev)
734 * This check for _PAGE_RWX and _PAGE_PRESENT bits
739 * This check for access to privilege space
741 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
747 * Generic functions with hash/radix callbacks
750 static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
751 pte_t *ptep, pte_t entry,
752 unsigned long address,
756 return radix__ptep_set_access_flags(vma, ptep, entry,
758 return hash__ptep_set_access_flags(ptep, entry);
761 #define __HAVE_ARCH_PTE_SAME
762 static inline int pte_same(pte_t pte_a, pte_t pte_b)
765 return radix__pte_same(pte_a, pte_b);
766 return hash__pte_same(pte_a, pte_b);
769 static inline int pte_none(pte_t pte)
772 return radix__pte_none(pte);
773 return hash__pte_none(pte);
776 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
777 pte_t *ptep, pte_t pte, int percpu)
780 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE)));
782 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE
783 * in all the callers.
785 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE));
788 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
789 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
792 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
794 #define pgprot_noncached pgprot_noncached
795 static inline pgprot_t pgprot_noncached(pgprot_t prot)
797 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
798 _PAGE_NON_IDEMPOTENT);
801 #define pgprot_noncached_wc pgprot_noncached_wc
802 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
804 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
808 #define pgprot_cached pgprot_cached
809 static inline pgprot_t pgprot_cached(pgprot_t prot)
811 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
814 #define pgprot_writecombine pgprot_writecombine
815 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
817 return pgprot_noncached_wc(prot);
820 * check a pte mapping have cache inhibited property
822 static inline bool pte_ci(pte_t pte)
824 __be64 pte_v = pte_raw(pte);
826 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) ||
827 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT)))
832 static inline void pmd_clear(pmd_t *pmdp)
834 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
836 * Don't use this if we can possibly have a hash page table
837 * entry mapping this.
839 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
844 static inline int pmd_none(pmd_t pmd)
846 return !pmd_raw(pmd);
849 static inline int pmd_present(pmd_t pmd)
852 * A pmd is considerent present if _PAGE_PRESENT is set.
853 * We also need to consider the pmd present which is marked
854 * invalid during a split. Hence we look for _PAGE_INVALID
855 * if we find _PAGE_PRESENT cleared.
857 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID))
863 static inline int pmd_is_serializing(pmd_t pmd)
866 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear
867 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate).
869 * This condition may also occur when flushing a pmd while flushing
870 * it (see ptep_modify_prot_start), so callers must ensure this
871 * case is fine as well.
873 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) ==
874 cpu_to_be64(_PAGE_INVALID))
880 static inline int pmd_bad(pmd_t pmd)
883 return radix__pmd_bad(pmd);
884 return hash__pmd_bad(pmd);
887 static inline void pud_clear(pud_t *pudp)
889 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
891 * Don't use this if we can possibly have a hash page table
892 * entry mapping this.
894 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
899 static inline int pud_none(pud_t pud)
901 return !pud_raw(pud);
904 static inline int pud_present(pud_t pud)
906 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
909 extern struct page *pud_page(pud_t pud);
910 extern struct page *pmd_page(pmd_t pmd);
911 static inline pte_t pud_pte(pud_t pud)
913 return __pte_raw(pud_raw(pud));
916 static inline pud_t pte_pud(pte_t pte)
918 return __pud_raw(pte_raw(pte));
921 static inline pte_t *pudp_ptep(pud_t *pud)
926 #define pud_pfn(pud) pte_pfn(pud_pte(pud))
927 #define pud_dirty(pud) pte_dirty(pud_pte(pud))
928 #define pud_young(pud) pte_young(pud_pte(pud))
929 #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud)))
930 #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud)))
931 #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud)))
932 #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud)))
933 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
934 #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud)))
935 #define pud_write(pud) pte_write(pud_pte(pud))
937 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
938 #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud))
939 #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud)))
940 #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud)))
941 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
943 static inline int pud_bad(pud_t pud)
946 return radix__pud_bad(pud);
947 return hash__pud_bad(pud);
950 #define pud_access_permitted pud_access_permitted
951 static inline bool pud_access_permitted(pud_t pud, bool write)
953 return pte_access_permitted(pud_pte(pud), write);
956 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) })
957 static inline __be64 p4d_raw(p4d_t x)
959 return pgd_raw(x.pgd);
962 #define p4d_write(p4d) pte_write(p4d_pte(p4d))
964 static inline void p4d_clear(p4d_t *p4dp)
969 static inline int p4d_none(p4d_t p4d)
971 return !p4d_raw(p4d);
974 static inline int p4d_present(p4d_t p4d)
976 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT));
979 static inline pte_t p4d_pte(p4d_t p4d)
981 return __pte_raw(p4d_raw(p4d));
984 static inline p4d_t pte_p4d(pte_t pte)
986 return __p4d_raw(pte_raw(pte));
989 static inline int p4d_bad(p4d_t p4d)
992 return radix__p4d_bad(p4d);
993 return hash__p4d_bad(p4d);
996 #define p4d_access_permitted p4d_access_permitted
997 static inline bool p4d_access_permitted(p4d_t p4d, bool write)
999 return pte_access_permitted(p4d_pte(p4d), write);
1002 extern struct page *p4d_page(p4d_t p4d);
1004 /* Pointers in the page table tree are physical addresses */
1005 #define __pgtable_ptr_val(ptr) __pa(ptr)
1007 static inline pud_t *p4d_pgtable(p4d_t p4d)
1009 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS);
1012 static inline pmd_t *pud_pgtable(pud_t pud)
1014 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS);
1017 #define pte_ERROR(e) \
1018 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
1019 #define pmd_ERROR(e) \
1020 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
1021 #define pud_ERROR(e) \
1022 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
1023 #define pgd_ERROR(e) \
1024 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1026 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
1028 if (radix_enabled()) {
1029 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1030 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1031 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1033 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE);
1035 return hash__map_kernel_page(ea, pa, prot);
1038 void unmap_kernel_page(unsigned long va);
1040 static inline int __meminit vmemmap_create_mapping(unsigned long start,
1041 unsigned long page_size,
1044 if (radix_enabled())
1045 return radix__vmemmap_create_mapping(start, page_size, phys);
1046 return hash__vmemmap_create_mapping(start, page_size, phys);
1049 #ifdef CONFIG_MEMORY_HOTPLUG
1050 static inline void vmemmap_remove_mapping(unsigned long start,
1051 unsigned long page_size)
1053 if (radix_enabled())
1054 return radix__vmemmap_remove_mapping(start, page_size);
1055 return hash__vmemmap_remove_mapping(start, page_size);
1059 #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE)
1060 static inline void __kernel_map_pages(struct page *page, int numpages, int enable)
1062 if (radix_enabled())
1063 radix__kernel_map_pages(page, numpages, enable);
1065 hash__kernel_map_pages(page, numpages, enable);
1069 static inline pte_t pmd_pte(pmd_t pmd)
1071 return __pte_raw(pmd_raw(pmd));
1074 static inline pmd_t pte_pmd(pte_t pte)
1076 return __pmd_raw(pte_raw(pte));
1079 static inline pte_t *pmdp_ptep(pmd_t *pmd)
1081 return (pte_t *)pmd;
1083 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1084 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1085 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
1086 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1087 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1088 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
1089 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
1090 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1091 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
1093 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1094 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1095 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1096 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1098 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1099 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)))
1100 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd))
1101 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)))
1103 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1105 #ifdef CONFIG_NUMA_BALANCING
1106 static inline int pmd_protnone(pmd_t pmd)
1108 return pte_protnone(pmd_pte(pmd));
1110 #endif /* CONFIG_NUMA_BALANCING */
1112 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
1114 #define pmd_access_permitted pmd_access_permitted
1115 static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1118 * pmdp_invalidate sets this combination (which is not caught by
1119 * !pte_present() check in pte_access_permitted), to prevent
1120 * lock-free lookups, as part of the serialize_against_pte_lookup()
1123 * This also catches the case where the PTE's hardware PRESENT bit is
1124 * cleared while TLB is flushed, which is suboptimal but should not
1127 if (pmd_is_serializing(pmd))
1130 return pte_access_permitted(pmd_pte(pmd), write);
1133 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1134 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1135 extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot);
1136 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1137 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1138 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1139 pmd_t *pmdp, pmd_t pmd);
1140 extern void set_pud_at(struct mm_struct *mm, unsigned long addr,
1141 pud_t *pudp, pud_t pud);
1143 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
1144 unsigned long addr, pmd_t *pmd)
1148 static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
1149 unsigned long addr, pud_t *pud)
1153 extern int hash__has_transparent_hugepage(void);
1154 static inline int has_transparent_hugepage(void)
1156 if (radix_enabled())
1157 return radix__has_transparent_hugepage();
1158 return hash__has_transparent_hugepage();
1160 #define has_transparent_hugepage has_transparent_hugepage
1162 static inline int has_transparent_pud_hugepage(void)
1164 if (radix_enabled())
1165 return radix__has_transparent_pud_hugepage();
1168 #define has_transparent_pud_hugepage has_transparent_pud_hugepage
1170 static inline unsigned long
1171 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1172 unsigned long clr, unsigned long set)
1174 if (radix_enabled())
1175 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1176 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1179 static inline unsigned long
1180 pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp,
1181 unsigned long clr, unsigned long set)
1183 if (radix_enabled())
1184 return radix__pud_hugepage_update(mm, addr, pudp, clr, set);
1186 return pud_val(*pudp);
1190 * returns true for pmd migration entries, THP, devmap, hugetlb
1191 * But compile time dependent on THP config
1193 static inline int pmd_large(pmd_t pmd)
1195 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
1198 static inline int pud_large(pud_t pud)
1200 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
1204 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1205 * the below will work for radix too
1207 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1208 unsigned long addr, pmd_t *pmdp)
1212 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1214 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1215 return ((old & _PAGE_ACCESSED) != 0);
1218 static inline int __pudp_test_and_clear_young(struct mm_struct *mm,
1219 unsigned long addr, pud_t *pudp)
1223 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1225 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0);
1226 return ((old & _PAGE_ACCESSED) != 0);
1229 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1230 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1233 if (pmd_write(*pmdp))
1234 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1237 #define __HAVE_ARCH_PUDP_SET_WRPROTECT
1238 static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1241 if (pud_write(*pudp))
1242 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0);
1246 * Only returns true for a THP. False for pmd migration entry.
1247 * We also need to return true when we come across a pte that
1248 * in between a thp split. While splitting THP, we mark the pmd
1249 * invalid (pmdp_invalidate()) before we set it with pte page
1250 * address. A pmd_trans_huge() check against a pmd entry during that time
1251 * should return true.
1252 * We should not call this on a hugetlb entry. We should check for HugeTLB
1253 * entry using vma->vm_flags
1254 * The page table walk rule is explained in Documentation/mm/transhuge.rst
1256 static inline int pmd_trans_huge(pmd_t pmd)
1258 if (!pmd_present(pmd))
1261 if (radix_enabled())
1262 return radix__pmd_trans_huge(pmd);
1263 return hash__pmd_trans_huge(pmd);
1266 static inline int pud_trans_huge(pud_t pud)
1268 if (!pud_present(pud))
1271 if (radix_enabled())
1272 return radix__pud_trans_huge(pud);
1277 #define __HAVE_ARCH_PMD_SAME
1278 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1280 if (radix_enabled())
1281 return radix__pmd_same(pmd_a, pmd_b);
1282 return hash__pmd_same(pmd_a, pmd_b);
1285 #define pud_same pud_same
1286 static inline int pud_same(pud_t pud_a, pud_t pud_b)
1288 if (radix_enabled())
1289 return radix__pud_same(pud_a, pud_b);
1290 return hash__pud_same(pud_a, pud_b);
1294 static inline pmd_t __pmd_mkhuge(pmd_t pmd)
1296 if (radix_enabled())
1297 return radix__pmd_mkhuge(pmd);
1298 return hash__pmd_mkhuge(pmd);
1301 static inline pud_t __pud_mkhuge(pud_t pud)
1303 if (radix_enabled())
1304 return radix__pud_mkhuge(pud);
1310 * pfn_pmd return a pmd_t that can be used as pmd pte entry.
1312 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1314 #ifdef CONFIG_DEBUG_VM
1315 if (radix_enabled())
1316 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0);
1318 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) !=
1319 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE));
1324 static inline pud_t pud_mkhuge(pud_t pud)
1326 #ifdef CONFIG_DEBUG_VM
1327 if (radix_enabled())
1328 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0);
1336 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1337 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1338 unsigned long address, pmd_t *pmdp,
1339 pmd_t entry, int dirty);
1340 #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS
1341 extern int pudp_set_access_flags(struct vm_area_struct *vma,
1342 unsigned long address, pud_t *pudp,
1343 pud_t entry, int dirty);
1345 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1346 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1347 unsigned long address, pmd_t *pmdp);
1348 #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG
1349 extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
1350 unsigned long address, pud_t *pudp);
1353 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1354 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1355 unsigned long addr, pmd_t *pmdp)
1357 if (radix_enabled())
1358 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
1359 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1362 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
1363 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
1364 unsigned long addr, pud_t *pudp)
1366 if (radix_enabled())
1367 return radix__pudp_huge_get_and_clear(mm, addr, pudp);
1372 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1373 unsigned long address, pmd_t *pmdp)
1375 if (radix_enabled())
1376 return radix__pmdp_collapse_flush(vma, address, pmdp);
1377 return hash__pmdp_collapse_flush(vma, address, pmdp);
1379 #define pmdp_collapse_flush pmdp_collapse_flush
1381 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1382 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
1384 pmd_t *pmdp, int full);
1386 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
1387 pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
1389 pud_t *pudp, int full);
1391 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1392 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1393 pmd_t *pmdp, pgtable_t pgtable)
1395 if (radix_enabled())
1396 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1397 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1400 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1401 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1404 if (radix_enabled())
1405 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
1406 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1409 #define __HAVE_ARCH_PMDP_INVALIDATE
1410 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1413 #define pmd_move_must_withdraw pmd_move_must_withdraw
1415 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1416 struct spinlock *old_pmd_ptl,
1417 struct vm_area_struct *vma);
1419 * Hash translation mode use the deposited table to store hash pte
1422 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1423 static inline bool arch_needs_pgtable_deposit(void)
1425 if (radix_enabled())
1429 extern void serialize_against_pte_lookup(struct mm_struct *mm);
1432 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1434 if (radix_enabled())
1435 return radix__pmd_mkdevmap(pmd);
1436 return hash__pmd_mkdevmap(pmd);
1439 static inline pud_t pud_mkdevmap(pud_t pud)
1441 if (radix_enabled())
1442 return radix__pud_mkdevmap(pud);
1447 static inline int pmd_devmap(pmd_t pmd)
1449 return pte_devmap(pmd_pte(pmd));
1452 static inline int pud_devmap(pud_t pud)
1454 return pte_devmap(pud_pte(pud));
1457 static inline int pgd_devmap(pgd_t pgd)
1461 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1463 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1464 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
1465 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1466 pte_t *, pte_t, pte_t);
1469 * Returns true for a R -> RW upgrade of pte
1471 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val)
1473 if (!(old_val & _PAGE_READ))
1476 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE))
1483 * Like pmd_huge() and pmd_large(), but works regardless of config options
1485 #define pmd_is_leaf pmd_is_leaf
1486 #define pmd_leaf pmd_is_leaf
1487 static inline bool pmd_is_leaf(pmd_t pmd)
1489 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
1492 #define pud_is_leaf pud_is_leaf
1493 #define pud_leaf pud_is_leaf
1494 static inline bool pud_is_leaf(pud_t pud)
1496 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
1499 #endif /* __ASSEMBLY__ */
1500 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */