1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
5 #ifndef _ASM_POWERPC_BARRIER_H
6 #define _ASM_POWERPC_BARRIER_H
8 #include <asm/asm-const.h>
11 #include <asm/ppc-opcode.h>
16 * The sync instruction guarantees that all memory accesses initiated
17 * by this processor have been performed (with respect to all other
18 * mechanisms that access memory). The eieio instruction is a barrier
19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
26 * *mb() variants without smp_ prefix must order all types of memory
27 * operations with one another. sync is the only instruction sufficient
30 * For the smp_ barriers, ordering is for cacheable memory operations
31 * only. We have to use the sync instruction for smp_mb(), since lwsync
32 * doesn't order loads with respect to previous stores. Lwsync can be
33 * used for smp_rmb() and smp_wmb().
35 * However, on CPUs that don't support lwsync, lwsync actually maps to a
36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
38 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
39 #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
40 #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
42 /* The sub-arch has lwsync */
43 #if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
44 # define SMPWMB LWSYNC
49 #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
50 #define dma_rmb() __lwsync()
51 #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
53 #define __smp_lwsync() __lwsync()
55 #define __smp_mb() mb()
56 #define __smp_rmb() __lwsync()
57 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
60 * This is a barrier which prevents following instructions from being
61 * started until the value of the argument x is known. For example, if
62 * x is a variable loaded from memory, this prevents following
63 * instructions from being executed until the load has been performed.
65 #define data_barrier(x) \
66 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
68 #define __smp_store_release(p, v) \
70 compiletime_assert_atomic_type(*p); \
75 #define __smp_load_acquire(p) \
77 typeof(*p) ___p1 = READ_ONCE(*p); \
78 compiletime_assert_atomic_type(*p); \
83 #ifdef CONFIG_PPC_BOOK3S_64
84 #define NOSPEC_BARRIER_SLOT nop
85 #elif defined(CONFIG_PPC_FSL_BOOK3E)
86 #define NOSPEC_BARRIER_SLOT nop; nop
89 #ifdef CONFIG_PPC_BARRIER_NOSPEC
91 * Prevent execution of subsequent instructions until preceding branches have
92 * been fully resolved and are no longer executing speculatively.
94 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
96 // This also acts as a compiler barrier due to the memory clobber.
97 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
99 #else /* !CONFIG_PPC_BARRIER_NOSPEC */
100 #define barrier_nospec_asm
101 #define barrier_nospec()
102 #endif /* CONFIG_PPC_BARRIER_NOSPEC */
105 * pmem_wmb() ensures that all stores for which the modification
106 * are written to persistent storage by preceding dcbfps/dcbstps
107 * instructions have updated persistent storage before any data
108 * access or data transfer caused by subsequent instructions is
111 #define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory")
113 #include <asm-generic/barrier.h>
115 #endif /* _ASM_POWERPC_BARRIER_H */