1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Unaligned memory access handler
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Significantly tweaked by LaMont Jones <lamont@debian.org>
9 #include <linux/jiffies.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched/signal.h>
13 #include <linux/sched/debug.h>
14 #include <linux/signal.h>
15 #include <linux/ratelimit.h>
16 #include <linux/uaccess.h>
17 #include <asm/hardirq.h>
18 #include <asm/traps.h>
20 /* #define DEBUG_UNALIGNED 1 */
22 #ifdef DEBUG_UNALIGNED
23 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
25 #define DPRINTF(fmt, args...)
34 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
35 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
36 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
37 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
38 #define OPCODE4(a) ((a)<<26)
39 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
40 #define OPCODE2_MASK OPCODE2(0x3f,1)
41 #define OPCODE3_MASK OPCODE3(0x3f,1)
42 #define OPCODE4_MASK OPCODE4(0x3f)
44 /* skip LDB - never unaligned (index) */
45 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
46 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
47 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
48 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
49 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
50 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
51 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
52 /* skip LDB - never unaligned (short) */
53 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
54 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
55 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
56 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
57 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
58 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
59 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
60 /* skip STB - never unaligned */
61 #define OPCODE_STH OPCODE1(0x03,1,0x9)
62 #define OPCODE_STW OPCODE1(0x03,1,0xa)
63 #define OPCODE_STD OPCODE1(0x03,1,0xb)
64 /* skip STBY - never unaligned */
65 /* skip STDBY - never unaligned */
66 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
67 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
69 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
70 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
71 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
72 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
73 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
74 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
75 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
76 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
77 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
78 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
79 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
80 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
82 #define OPCODE_LDD_L OPCODE2(0x14,0)
83 #define OPCODE_FLDD_L OPCODE2(0x14,1)
84 #define OPCODE_STD_L OPCODE2(0x1c,0)
85 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
87 #define OPCODE_LDW_M OPCODE3(0x17,1)
88 #define OPCODE_FLDW_L OPCODE3(0x17,0)
89 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
90 #define OPCODE_STW_M OPCODE3(0x1f,1)
92 #define OPCODE_LDH_L OPCODE4(0x11)
93 #define OPCODE_LDW_L OPCODE4(0x12)
94 #define OPCODE_LDWM OPCODE4(0x13)
95 #define OPCODE_STH_L OPCODE4(0x19)
96 #define OPCODE_STW_L OPCODE4(0x1A)
97 #define OPCODE_STWM OPCODE4(0x1B)
99 #define MAJOR_OP(i) (((i)>>26)&0x3f)
100 #define R1(i) (((i)>>21)&0x1f)
101 #define R2(i) (((i)>>16)&0x1f)
102 #define R3(i) ((i)&0x1f)
103 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
104 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
105 #define IM5_2(i) IM((i)>>16,5)
106 #define IM5_3(i) IM((i),5)
107 #define IM14(i) IM((i),14)
109 #define ERR_NOTHANDLED -1
111 int unaligned_enabled __read_mostly = 1;
113 static int emulate_ldh(struct pt_regs *regs, int toreg)
115 unsigned long saddr = regs->ior;
116 unsigned long val = 0, temp1;
117 ASM_EXCEPTIONTABLE_VAR(ret);
119 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
120 regs->isr, regs->ior, toreg);
122 __asm__ __volatile__ (
124 "1: ldbs 0(%%sr1,%3), %2\n"
125 "2: ldbs 1(%%sr1,%3), %0\n"
126 " depw %2, 23, 24, %0\n"
128 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
129 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
130 : "+r" (val), "+r" (ret), "=&r" (temp1)
131 : "r" (saddr), "r" (regs->isr) );
133 DPRINTF("val = 0x" RFMT "\n", val);
136 regs->gr[toreg] = val;
141 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
143 unsigned long saddr = regs->ior;
144 unsigned long val = 0;
145 ASM_EXCEPTIONTABLE_VAR(ret);
147 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
148 regs->isr, regs->ior, toreg);
150 __asm__ __volatile__ (
151 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */
153 " depw %%r0,31,2,%3\n"
154 "1: ldw 0(%%sr1,%3),%0\n"
155 "2: ldw 4(%%sr1,%3),%%r20\n"
156 " subi 32,%%r19,%%r19\n"
158 " vshd %0,%%r20,%0\n"
160 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
161 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
162 : "=r" (val), "+r" (ret)
163 : "0" (val), "r" (saddr), "r" (regs->isr)
166 DPRINTF("val = 0x" RFMT "\n", val);
169 ((__u32*)(regs->fr))[toreg] = val;
171 regs->gr[toreg] = val;
175 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
177 unsigned long saddr = regs->ior;
179 ASM_EXCEPTIONTABLE_VAR(ret);
181 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
182 regs->isr, regs->ior, toreg);
184 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
185 return ERR_NOTHANDLED;
188 __asm__ __volatile__ (
189 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
191 " depd %%r0,63,3,%3\n"
192 "1: ldd 0(%%sr1,%3),%0\n"
193 "2: ldd 8(%%sr1,%3),%%r20\n"
194 " subi 64,%%r19,%%r19\n"
196 " shrpd %0,%%r20,%%sar,%0\n"
198 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
199 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
200 : "=r" (val), "+r" (ret)
201 : "0" (val), "r" (saddr), "r" (regs->isr)
205 unsigned long valh=0,vall=0;
206 __asm__ __volatile__ (
207 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */
209 " dep %%r0,31,2,%5\n"
210 "1: ldw 0(%%sr1,%5),%0\n"
211 "2: ldw 4(%%sr1,%5),%1\n"
212 "3: ldw 8(%%sr1,%5),%%r20\n"
213 " subi 32,%%r19,%%r19\n"
216 " vshd %1,%%r20,%1\n"
218 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b)
219 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b)
220 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b)
221 : "=r" (valh), "=r" (vall), "+r" (ret)
222 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr)
224 val=((__u64)valh<<32)|(__u64)vall;
228 DPRINTF("val = 0x%llx\n", val);
231 regs->fr[toreg] = val;
233 regs->gr[toreg] = val;
238 static int emulate_sth(struct pt_regs *regs, int frreg)
240 unsigned long val = regs->gr[frreg];
241 ASM_EXCEPTIONTABLE_VAR(ret);
246 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
247 val, regs->isr, regs->ior);
249 __asm__ __volatile__ (
251 " extrw,u %1, 23, 8, %%r19\n"
252 "1: stb %1, 1(%%sr1, %2)\n"
253 "2: stb %%r19, 0(%%sr1, %2)\n"
255 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
256 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
258 : "r" (val), "r" (regs->ior), "r" (regs->isr)
264 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
267 ASM_EXCEPTIONTABLE_VAR(ret);
270 val = ((__u32*)(regs->fr))[frreg];
272 val = regs->gr[frreg];
276 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
277 val, regs->isr, regs->ior);
280 __asm__ __volatile__ (
282 " zdep %2, 28, 2, %%r19\n"
283 " dep %%r0, 31, 2, %2\n"
285 " depwi,z -2, %%sar, 32, %%r19\n"
286 "1: ldw 0(%%sr1,%2),%%r20\n"
287 "2: ldw 4(%%sr1,%2),%%r21\n"
288 " vshd %%r0, %1, %%r22\n"
289 " vshd %1, %%r0, %%r1\n"
290 " and %%r20, %%r19, %%r20\n"
291 " andcm %%r21, %%r19, %%r21\n"
292 " or %%r22, %%r20, %%r20\n"
293 " or %%r1, %%r21, %%r21\n"
294 " stw %%r20,0(%%sr1,%2)\n"
295 " stw %%r21,4(%%sr1,%2)\n"
297 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b)
298 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b)
300 : "r" (val), "r" (regs->ior), "r" (regs->isr)
301 : "r19", "r20", "r21", "r22", "r1" );
305 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
308 ASM_EXCEPTIONTABLE_VAR(ret);
311 val = regs->fr[frreg];
313 val = regs->gr[frreg];
317 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
318 val, regs->isr, regs->ior);
320 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
321 return ERR_NOTHANDLED;
324 __asm__ __volatile__ (
326 " depd,z %2, 60, 3, %%r19\n"
327 " depd %%r0, 63, 3, %2\n"
329 " depdi,z -2, %%sar, 64, %%r19\n"
330 "1: ldd 0(%%sr1,%2),%%r20\n"
331 "2: ldd 8(%%sr1,%2),%%r21\n"
332 " shrpd %%r0, %1, %%sar, %%r22\n"
333 " shrpd %1, %%r0, %%sar, %%r1\n"
334 " and %%r20, %%r19, %%r20\n"
335 " andcm %%r21, %%r19, %%r21\n"
336 " or %%r22, %%r20, %%r20\n"
337 " or %%r1, %%r21, %%r21\n"
338 "3: std %%r20,0(%%sr1,%2)\n"
339 "4: std %%r21,8(%%sr1,%2)\n"
341 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b)
342 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b)
343 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b)
344 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b)
346 : "r" (val), "r" (regs->ior), "r" (regs->isr)
347 : "r19", "r20", "r21", "r22", "r1" );
350 unsigned long valh=(val>>32),vall=(val&0xffffffffl);
351 __asm__ __volatile__ (
353 " zdep %2, 29, 2, %%r19\n"
354 " dep %%r0, 31, 2, %3\n"
356 " zvdepi -2, 32, %%r19\n"
357 "1: ldw 0(%%sr1,%3),%%r20\n"
358 "2: ldw 8(%%sr1,%3),%%r21\n"
359 " vshd %1, %2, %%r1\n"
360 " vshd %%r0, %1, %1\n"
361 " vshd %2, %%r0, %2\n"
362 " and %%r20, %%r19, %%r20\n"
363 " andcm %%r21, %%r19, %%r21\n"
364 " or %1, %%r20, %1\n"
365 " or %2, %%r21, %2\n"
366 "3: stw %1,0(%%sr1,%3)\n"
367 "4: stw %%r1,4(%%sr1,%3)\n"
368 "5: stw %2,8(%%sr1,%3)\n"
370 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b)
371 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b)
372 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b)
373 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b)
374 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b)
376 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr)
377 : "r19", "r20", "r21", "r1" );
384 void handle_unaligned(struct pt_regs *regs)
386 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
387 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
389 int ret = ERR_NOTHANDLED;
390 register int flop=0; /* true if this is a flop */
392 __inc_irq_stat(irq_unaligned_count);
394 /* log a message with pacing */
395 if (user_mode(regs)) {
396 if (current->thread.flags & PARISC_UAC_SIGBUS) {
400 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
401 __ratelimit(&ratelimit)) {
403 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n",
404 current->comm, task_pid_nr(current), regs->ior, regs->iaoq[0]);
405 printk(KERN_WARNING "%s", buf);
406 #ifdef DEBUG_UNALIGNED
411 if (!unaligned_enabled)
415 /* handle modification - OK, it's ugly, see the instruction manual */
416 switch (MAJOR_OP(regs->iir))
424 if (regs->iir&0x1000) /* short loads */
426 newbase += IM5_3(regs->iir);
428 newbase += IM5_2(regs->iir);
429 else if (regs->iir&0x2000) /* scaled indexed */
432 switch (regs->iir & OPCODE1_MASK)
442 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
443 } else /* simple indexed */
444 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
450 newbase += IM14(regs->iir);
457 newbase += IM14(regs->iir&~0xe);
463 newbase += IM14(regs->iir&6);
470 newbase += IM14(regs->iir&~4);
475 /* TODO: make this cleaner... */
476 switch (regs->iir & OPCODE1_MASK)
480 ret = emulate_ldh(regs, R3(regs->iir));
487 ret = emulate_ldw(regs, R3(regs->iir),0);
491 ret = emulate_sth(regs, R2(regs->iir));
496 ret = emulate_stw(regs, R2(regs->iir),0);
504 ret = emulate_ldd(regs, R3(regs->iir),0);
509 ret = emulate_std(regs, R2(regs->iir),0);
518 ret = emulate_ldw(regs,FR3(regs->iir),1);
524 ret = emulate_ldd(regs,R3(regs->iir),1);
532 ret = emulate_stw(regs,FR3(regs->iir),1);
538 ret = emulate_std(regs,R3(regs->iir),1);
545 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
548 switch (regs->iir & OPCODE2_MASK)
552 ret = emulate_ldd(regs,R2(regs->iir),1);
556 ret = emulate_std(regs, R2(regs->iir),1);
560 ret = emulate_ldd(regs, R2(regs->iir),0);
563 ret = emulate_std(regs, R2(regs->iir),0);
567 switch (regs->iir & OPCODE3_MASK)
571 ret = emulate_ldw(regs, R2(regs->iir), 1);
574 ret = emulate_ldw(regs, R2(regs->iir), 0);
579 ret = emulate_stw(regs, R2(regs->iir),1);
582 ret = emulate_stw(regs, R2(regs->iir),0);
585 switch (regs->iir & OPCODE4_MASK)
588 ret = emulate_ldh(regs, R2(regs->iir));
592 ret = emulate_ldw(regs, R2(regs->iir),0);
595 ret = emulate_sth(regs, R2(regs->iir));
599 ret = emulate_stw(regs, R2(regs->iir),0);
603 if (ret == 0 && modify && R1(regs->iir))
604 regs->gr[R1(regs->iir)] = newbase;
607 if (ret == ERR_NOTHANDLED)
608 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
610 DPRINTF("ret = %d\n", ret);
615 * The unaligned handler failed.
616 * If we were called by __get_user() or __put_user() jump
617 * to it's exception fixup handler instead of crashing.
619 if (!user_mode(regs) && fixup_exception(regs))
622 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
623 die_if_kernel("Unaligned data reference", regs, 28);
627 force_sig_fault(SIGSEGV, SEGV_MAPERR,
628 (void __user *)regs->ior);
633 /* couldn't handle it ... */
634 force_sig_fault(SIGBUS, BUS_ADRALN,
635 (void __user *)regs->ior);
641 /* else we handled it, let life go on. */
646 * NB: check_unaligned() is only used for PCXS processors right
647 * now, so we only check for PA1.1 encodings at this point.
651 check_unaligned(struct pt_regs *regs)
653 unsigned long align_mask;
655 /* Get alignment mask */
658 switch (regs->iir & OPCODE1_MASK) {
676 switch (regs->iir & OPCODE4_MASK) {
691 return (int)(regs->ior & align_mask);