2 * PARISC TLB and cache flushing support
3 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
4 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
5 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * NOTE: fdc,fic, and pdc instructions that use base register modification
24 * should only use index and base registers that are not shadowed,
25 * so that the fast path emulation in the non access miss handler
36 #include <asm/assembly.h>
37 #include <asm/pgtable.h>
38 #include <asm/cache.h>
40 #include <asm/alternative.h>
41 #include <linux/linkage.h>
42 #include <linux/init.h>
47 ENTRY_CFI(flush_tlb_all_local)
49 * The pitlbe and pdtlbe instructions should only be used to
50 * flush the entire tlb. Also, there needs to be no intervening
51 * tlb operations, e.g. tlb misses, so the operation needs
52 * to happen in real mode with all interruptions disabled.
55 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
56 rsm PSW_SM_I, %r19 /* save I-bit state */
64 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
65 mtctl %r0, %cr17 /* Clear IIASQ tail */
66 mtctl %r0, %cr17 /* Clear IIASQ head */
67 mtctl %r1, %cr18 /* IIAOQ head */
69 mtctl %r1, %cr18 /* IIAOQ tail */
70 load32 REAL_MODE_PSW, %r1
75 1: load32 PA(cache_info), %r1
77 /* Flush Instruction Tlb */
79 LDREG ITLB_SID_BASE(%r1), %r20
80 LDREG ITLB_SID_STRIDE(%r1), %r21
81 LDREG ITLB_SID_COUNT(%r1), %r22
82 LDREG ITLB_OFF_BASE(%r1), %arg0
83 LDREG ITLB_OFF_STRIDE(%r1), %arg1
84 LDREG ITLB_OFF_COUNT(%r1), %arg2
85 LDREG ITLB_LOOP(%r1), %arg3
87 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
88 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
89 copy %arg0, %r28 /* Init base addr */
91 fitmanyloop: /* Loop if LOOP >= 2 */
93 add %r21, %r20, %r20 /* increment space */
94 copy %arg2, %r29 /* Init middle loop count */
96 fitmanymiddle: /* Loop if LOOP >= 2 */
97 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
98 pitlbe %r0(%sr1, %r28)
99 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
100 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
101 copy %arg3, %r31 /* Re-init inner loop count */
103 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
104 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
106 fitoneloop: /* Loop if LOOP = 1 */
108 copy %arg0, %r28 /* init base addr */
109 copy %arg2, %r29 /* init middle loop count */
111 fitonemiddle: /* Loop if LOOP = 1 */
112 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
113 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
115 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
116 add %r21, %r20, %r20 /* increment space */
122 LDREG DTLB_SID_BASE(%r1), %r20
123 LDREG DTLB_SID_STRIDE(%r1), %r21
124 LDREG DTLB_SID_COUNT(%r1), %r22
125 LDREG DTLB_OFF_BASE(%r1), %arg0
126 LDREG DTLB_OFF_STRIDE(%r1), %arg1
127 LDREG DTLB_OFF_COUNT(%r1), %arg2
128 LDREG DTLB_LOOP(%r1), %arg3
130 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
131 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
132 copy %arg0, %r28 /* Init base addr */
134 fdtmanyloop: /* Loop if LOOP >= 2 */
136 add %r21, %r20, %r20 /* increment space */
137 copy %arg2, %r29 /* Init middle loop count */
139 fdtmanymiddle: /* Loop if LOOP >= 2 */
140 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
141 pdtlbe %r0(%sr1, %r28)
142 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
143 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
144 copy %arg3, %r31 /* Re-init inner loop count */
146 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
147 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
149 fdtoneloop: /* Loop if LOOP = 1 */
151 copy %arg0, %r28 /* init base addr */
152 copy %arg2, %r29 /* init middle loop count */
154 fdtonemiddle: /* Loop if LOOP = 1 */
155 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
156 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
158 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
159 add %r21, %r20, %r20 /* increment space */
164 * Switch back to virtual mode
175 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
176 mtctl %r0, %cr17 /* Clear IIASQ tail */
177 mtctl %r0, %cr17 /* Clear IIASQ head */
178 mtctl %r1, %cr18 /* IIAOQ head */
180 mtctl %r1, %cr18 /* IIAOQ tail */
181 load32 KERNEL_PSW, %r1
182 or %r1, %r19, %r1 /* I-bit to state on entry */
183 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
189 ENDPROC_CFI(flush_tlb_all_local)
191 .import cache_info,data
193 ENTRY_CFI(flush_instruction_cache_local)
194 88: load32 cache_info, %r1
196 /* Flush Instruction Cache */
198 LDREG ICACHE_BASE(%r1), %arg0
199 LDREG ICACHE_STRIDE(%r1), %arg1
200 LDREG ICACHE_COUNT(%r1), %arg2
201 LDREG ICACHE_LOOP(%r1), %arg3
202 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
204 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
205 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
207 fimanyloop: /* Loop if LOOP >= 2 */
208 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
209 fice %r0(%sr1, %arg0)
210 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
211 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
212 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
214 fioneloop: /* Loop if LOOP = 1 */
215 /* Some implementations may flush with a single fice instruction */
216 cmpib,COND(>>=),n 15, %arg2, fioneloop2
219 fice,m %arg1(%sr1, %arg0)
220 fice,m %arg1(%sr1, %arg0)
221 fice,m %arg1(%sr1, %arg0)
222 fice,m %arg1(%sr1, %arg0)
223 fice,m %arg1(%sr1, %arg0)
224 fice,m %arg1(%sr1, %arg0)
225 fice,m %arg1(%sr1, %arg0)
226 fice,m %arg1(%sr1, %arg0)
227 fice,m %arg1(%sr1, %arg0)
228 fice,m %arg1(%sr1, %arg0)
229 fice,m %arg1(%sr1, %arg0)
230 fice,m %arg1(%sr1, %arg0)
231 fice,m %arg1(%sr1, %arg0)
232 fice,m %arg1(%sr1, %arg0)
233 fice,m %arg1(%sr1, %arg0)
234 addib,COND(>) -16, %arg2, fioneloop1
235 fice,m %arg1(%sr1, %arg0)
238 cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
241 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
242 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
246 mtsm %r22 /* restore I-bit */
247 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
250 ENDPROC_CFI(flush_instruction_cache_local)
253 .import cache_info, data
254 ENTRY_CFI(flush_data_cache_local)
255 88: load32 cache_info, %r1
257 /* Flush Data Cache */
259 LDREG DCACHE_BASE(%r1), %arg0
260 LDREG DCACHE_STRIDE(%r1), %arg1
261 LDREG DCACHE_COUNT(%r1), %arg2
262 LDREG DCACHE_LOOP(%r1), %arg3
263 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
265 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
266 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
268 fdmanyloop: /* Loop if LOOP >= 2 */
269 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
270 fdce %r0(%sr1, %arg0)
271 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
272 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
273 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
275 fdoneloop: /* Loop if LOOP = 1 */
276 /* Some implementations may flush with a single fdce instruction */
277 cmpib,COND(>>=),n 15, %arg2, fdoneloop2
280 fdce,m %arg1(%sr1, %arg0)
281 fdce,m %arg1(%sr1, %arg0)
282 fdce,m %arg1(%sr1, %arg0)
283 fdce,m %arg1(%sr1, %arg0)
284 fdce,m %arg1(%sr1, %arg0)
285 fdce,m %arg1(%sr1, %arg0)
286 fdce,m %arg1(%sr1, %arg0)
287 fdce,m %arg1(%sr1, %arg0)
288 fdce,m %arg1(%sr1, %arg0)
289 fdce,m %arg1(%sr1, %arg0)
290 fdce,m %arg1(%sr1, %arg0)
291 fdce,m %arg1(%sr1, %arg0)
292 fdce,m %arg1(%sr1, %arg0)
293 fdce,m %arg1(%sr1, %arg0)
294 fdce,m %arg1(%sr1, %arg0)
295 addib,COND(>) -16, %arg2, fdoneloop1
296 fdce,m %arg1(%sr1, %arg0)
299 cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
302 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
303 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
308 mtsm %r22 /* restore I-bit */
309 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
312 ENDPROC_CFI(flush_data_cache_local)
314 /* Clear page using kernel mapping. */
316 ENTRY_CFI(clear_page_asm)
319 /* Unroll the loop. */
320 ldi (PAGE_SIZE / 128), %r1
340 /* Note reverse branch hint for addib is taken. */
341 addib,COND(>),n -1, %r1, 1b
347 * Note that until (if) we start saving the full 64-bit register
348 * values on interrupt, we can't use std on a 32 bit kernel.
350 ldi (PAGE_SIZE / 64), %r1
370 addib,COND(>),n -1, %r1, 1b
375 ENDPROC_CFI(clear_page_asm)
377 /* Copy page using kernel mapping. */
379 ENTRY_CFI(copy_page_asm)
381 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
382 * Unroll the loop by hand and arrange insn appropriately.
383 * Prefetch doesn't improve performance on rp3440.
384 * GCC probably can do this just as well...
387 ldi (PAGE_SIZE / 128), %r1
431 /* Note reverse branch hint for addib is taken. */
432 addib,COND(>),n -1, %r1, 1b
438 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
439 * bundles (very restricted rules for bundling).
440 * Note that until (if) we start saving
441 * the full 64 bit register values on interrupt, we can't
442 * use ldd/std on a 32 bit kernel.
445 ldi (PAGE_SIZE / 64), %r1
481 addib,COND(>),n -1, %r1, 1b
486 ENDPROC_CFI(copy_page_asm)
489 * NOTE: Code in clear_user_page has a hard coded dependency on the
490 * maximum alias boundary being 4 Mb. We've been assured by the
491 * parisc chip designers that there will not ever be a parisc
492 * chip with a larger alias boundary (Never say never :-) ).
494 * Subtle: the dtlb miss handlers support the temp alias region by
495 * "knowing" that if a dtlb miss happens within the temp alias
496 * region it must have occurred while in clear_user_page. Since
497 * this routine makes use of processor local translations, we
498 * don't want to insert them into the kernel page table. Instead,
499 * we load up some general registers (they need to be registers
500 * which aren't shadowed) with the physical page numbers (preshifted
501 * for tlb insertion) needed to insert the translations. When we
502 * miss on the translation, the dtlb miss handler inserts the
503 * translation into the tlb using these values:
505 * %r26 physical page (shifted for tlb insert) of "to" translation
506 * %r23 physical page (shifted for tlb insert) of "from" translation
509 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
510 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
511 .macro convert_phys_for_tlb_insert20 phys
512 extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
513 #if _PAGE_SIZE_ENCODING_DEFAULT
514 depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
519 * copy_user_page_asm() performs a page copy using mappings
520 * equivalent to the user page mappings. It can be used to
521 * implement copy_user_page() but unfortunately both the `from'
522 * and `to' pages need to be flushed through mappings equivalent
523 * to the user mappings after the copy because the kernel accesses
524 * the `from' page through the kmap kernel mapping and the `to'
525 * page needs to be flushed since code can be copied. As a
526 * result, this implementation is less efficient than the simpler
527 * copy using the kernel mapping. It only needs the `from' page
528 * to flushed via the user mapping. The kunmap routines handle
529 * the flushes needed for the kernel mapping.
531 * I'm still keeping this around because it may be possible to
532 * use it if more information is passed into copy_user_page().
533 * Have to do some measurements to see if it is worthwhile to
534 * lobby for such a change.
538 ENTRY_CFI(copy_user_page_asm)
539 /* Convert virtual `to' and `from' addresses to physical addresses.
540 Move `from' physical address to non shadowed register. */
541 ldil L%(__PAGE_OFFSET), %r1
545 ldil L%(TMPALIAS_MAP_START), %r28
547 #if (TMPALIAS_MAP_START >= 0x80000000)
548 depdi 0, 31,32, %r28 /* clear any sign extension */
550 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
551 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
552 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
553 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
555 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
557 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
558 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
559 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
560 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
562 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
565 /* Purge any old translations */
573 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
574 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
578 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
579 * Unroll the loop by hand and arrange insn appropriately.
580 * GCC probably can do this just as well.
584 ldi (PAGE_SIZE / 128), %r1
628 /* conditional branches nullify on forward taken branch, and on
629 * non-taken backward branch. Note that .+4 is a backwards branch.
630 * The ldd should only get executed if the branch is taken.
632 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
633 ldd 0(%r29), %r19 /* start next loads */
636 ldi (PAGE_SIZE / 64), %r1
639 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
640 * bundles (very restricted rules for bundling). It probably
641 * does OK on PCXU and better, but we could do better with
642 * ldd/std instructions. Note that until (if) we start saving
643 * the full 64 bit register values on interrupt, we can't
644 * use ldd/std on a 32 bit kernel.
681 addib,COND(>) -1, %r1,1b
687 ENDPROC_CFI(copy_user_page_asm)
689 ENTRY_CFI(clear_user_page_asm)
692 ldil L%(TMPALIAS_MAP_START), %r28
694 #if (TMPALIAS_MAP_START >= 0x80000000)
695 depdi 0, 31,32, %r28 /* clear any sign extension */
697 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
698 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
699 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
701 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
702 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
703 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
706 /* Purge any old translation */
712 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
716 ldi (PAGE_SIZE / 128), %r1
718 /* PREFETCH (Write) has not (yet) been proven to help here */
719 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
737 addib,COND(>) -1, %r1, 1b
740 #else /* ! CONFIG_64BIT */
741 ldi (PAGE_SIZE / 64), %r1
759 addib,COND(>) -1, %r1, 1b
761 #endif /* CONFIG_64BIT */
765 ENDPROC_CFI(clear_user_page_asm)
767 ENTRY_CFI(flush_dcache_page_asm)
768 ldil L%(TMPALIAS_MAP_START), %r28
770 #if (TMPALIAS_MAP_START >= 0x80000000)
771 depdi 0, 31,32, %r28 /* clear any sign extension */
773 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
774 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
775 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
777 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
778 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
779 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
782 /* Purge any old translation */
788 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
791 88: ldil L%dcache_stride, %r1
792 ldw R%dcache_stride(%r1), r31
795 depdi,z 1, 63-PAGE_SHIFT,1, %r25
797 depwi,z 1, 31-PAGE_SHIFT,1, %r25
817 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
820 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
824 ENDPROC_CFI(flush_dcache_page_asm)
826 ENTRY_CFI(purge_dcache_page_asm)
827 ldil L%(TMPALIAS_MAP_START), %r28
829 #if (TMPALIAS_MAP_START >= 0x80000000)
830 depdi 0, 31,32, %r28 /* clear any sign extension */
832 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
833 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
834 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
836 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
837 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
838 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
841 /* Purge any old translation */
847 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
850 88: ldil L%dcache_stride, %r1
851 ldw R%dcache_stride(%r1), r31
854 depdi,z 1, 63-PAGE_SHIFT,1, %r25
856 depwi,z 1, 31-PAGE_SHIFT,1, %r25
876 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
879 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
883 ENDPROC_CFI(purge_dcache_page_asm)
885 ENTRY_CFI(flush_icache_page_asm)
886 ldil L%(TMPALIAS_MAP_START), %r28
888 #if (TMPALIAS_MAP_START >= 0x80000000)
889 depdi 0, 31,32, %r28 /* clear any sign extension */
891 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
892 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
893 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
895 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
896 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
897 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
900 /* Purge any old translation. Note that the FIC instruction
901 * may use either the instruction or data TLB. Given that we
902 * have a flat address space, it's not clear which TLB will be
903 * used. So, we purge both entries. */
907 1: pitlb,l %r0(%sr4,%r28)
908 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
911 1: pitlb %r0(%sr4,%r28)
912 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
913 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
914 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
917 88: ldil L%icache_stride, %r1
918 ldw R%icache_stride(%r1), %r31
921 depdi,z 1, 63-PAGE_SHIFT,1, %r25
923 depwi,z 1, 31-PAGE_SHIFT,1, %r25
928 /* fic only has the type 26 form on PA1.1, requiring an
929 * explicit space specification, so use %sr4 */
930 1: fic,m %r31(%sr4,%r28)
931 fic,m %r31(%sr4,%r28)
932 fic,m %r31(%sr4,%r28)
933 fic,m %r31(%sr4,%r28)
934 fic,m %r31(%sr4,%r28)
935 fic,m %r31(%sr4,%r28)
936 fic,m %r31(%sr4,%r28)
937 fic,m %r31(%sr4,%r28)
938 fic,m %r31(%sr4,%r28)
939 fic,m %r31(%sr4,%r28)
940 fic,m %r31(%sr4,%r28)
941 fic,m %r31(%sr4,%r28)
942 fic,m %r31(%sr4,%r28)
943 fic,m %r31(%sr4,%r28)
944 fic,m %r31(%sr4,%r28)
945 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
946 fic,m %r31(%sr4,%r28)
948 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
952 ENDPROC_CFI(flush_icache_page_asm)
954 ENTRY_CFI(flush_kernel_dcache_page_asm)
955 88: ldil L%dcache_stride, %r1
956 ldw R%dcache_stride(%r1), %r23
959 depdi,z 1, 63-PAGE_SHIFT,1, %r25
961 depwi,z 1, 31-PAGE_SHIFT,1, %r25
981 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
984 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
988 ENDPROC_CFI(flush_kernel_dcache_page_asm)
990 ENTRY_CFI(purge_kernel_dcache_page_asm)
991 88: ldil L%dcache_stride, %r1
992 ldw R%dcache_stride(%r1), %r23
995 depdi,z 1, 63-PAGE_SHIFT,1, %r25
997 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1000 sub %r25, %r23, %r25
1017 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1020 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1024 ENDPROC_CFI(purge_kernel_dcache_page_asm)
1026 ENTRY_CFI(flush_user_dcache_range_asm)
1027 88: ldil L%dcache_stride, %r1
1028 ldw R%dcache_stride(%r1), %r23
1030 ANDCM %r26, %r21, %r26
1033 depd,z %r23, 59, 60, %r21
1035 depw,z %r23, 27, 28, %r21
1037 add %r26, %r21, %r22
1038 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1039 1: add %r22, %r21, %r22
1040 fdc,m %r23(%sr3, %r26)
1041 fdc,m %r23(%sr3, %r26)
1042 fdc,m %r23(%sr3, %r26)
1043 fdc,m %r23(%sr3, %r26)
1044 fdc,m %r23(%sr3, %r26)
1045 fdc,m %r23(%sr3, %r26)
1046 fdc,m %r23(%sr3, %r26)
1047 fdc,m %r23(%sr3, %r26)
1048 fdc,m %r23(%sr3, %r26)
1049 fdc,m %r23(%sr3, %r26)
1050 fdc,m %r23(%sr3, %r26)
1051 fdc,m %r23(%sr3, %r26)
1052 fdc,m %r23(%sr3, %r26)
1053 fdc,m %r23(%sr3, %r26)
1054 fdc,m %r23(%sr3, %r26)
1055 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1056 fdc,m %r23(%sr3, %r26)
1058 2: cmpb,COND(>>),n %r25, %r26, 2b
1059 fdc,m %r23(%sr3, %r26)
1061 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1065 ENDPROC_CFI(flush_user_dcache_range_asm)
1067 ENTRY_CFI(flush_kernel_dcache_range_asm)
1068 88: ldil L%dcache_stride, %r1
1069 ldw R%dcache_stride(%r1), %r23
1071 ANDCM %r26, %r21, %r26
1074 depd,z %r23, 59, 60, %r21
1076 depw,z %r23, 27, 28, %r21
1078 add %r26, %r21, %r22
1079 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1080 1: add %r22, %r21, %r22
1096 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1099 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1103 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1107 ENDPROC_CFI(flush_kernel_dcache_range_asm)
1109 ENTRY_CFI(purge_kernel_dcache_range_asm)
1110 88: ldil L%dcache_stride, %r1
1111 ldw R%dcache_stride(%r1), %r23
1113 ANDCM %r26, %r21, %r26
1116 depd,z %r23, 59, 60, %r21
1118 depw,z %r23, 27, 28, %r21
1120 add %r26, %r21, %r22
1121 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1122 1: add %r22, %r21, %r22
1138 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1141 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1145 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1149 ENDPROC_CFI(purge_kernel_dcache_range_asm)
1151 ENTRY_CFI(flush_user_icache_range_asm)
1152 88: ldil L%icache_stride, %r1
1153 ldw R%icache_stride(%r1), %r23
1155 ANDCM %r26, %r21, %r26
1158 depd,z %r23, 59, 60, %r21
1160 depw,z %r23, 27, 28, %r21
1162 add %r26, %r21, %r22
1163 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1164 1: add %r22, %r21, %r22
1165 fic,m %r23(%sr3, %r26)
1166 fic,m %r23(%sr3, %r26)
1167 fic,m %r23(%sr3, %r26)
1168 fic,m %r23(%sr3, %r26)
1169 fic,m %r23(%sr3, %r26)
1170 fic,m %r23(%sr3, %r26)
1171 fic,m %r23(%sr3, %r26)
1172 fic,m %r23(%sr3, %r26)
1173 fic,m %r23(%sr3, %r26)
1174 fic,m %r23(%sr3, %r26)
1175 fic,m %r23(%sr3, %r26)
1176 fic,m %r23(%sr3, %r26)
1177 fic,m %r23(%sr3, %r26)
1178 fic,m %r23(%sr3, %r26)
1179 fic,m %r23(%sr3, %r26)
1180 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1181 fic,m %r23(%sr3, %r26)
1183 2: cmpb,COND(>>),n %r25, %r26, 2b
1184 fic,m %r23(%sr3, %r26)
1186 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1190 ENDPROC_CFI(flush_user_icache_range_asm)
1192 ENTRY_CFI(flush_kernel_icache_page)
1193 88: ldil L%icache_stride, %r1
1194 ldw R%icache_stride(%r1), %r23
1197 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1199 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1201 add %r26, %r25, %r25
1202 sub %r25, %r23, %r25
1205 1: fic,m %r23(%sr4, %r26)
1206 fic,m %r23(%sr4, %r26)
1207 fic,m %r23(%sr4, %r26)
1208 fic,m %r23(%sr4, %r26)
1209 fic,m %r23(%sr4, %r26)
1210 fic,m %r23(%sr4, %r26)
1211 fic,m %r23(%sr4, %r26)
1212 fic,m %r23(%sr4, %r26)
1213 fic,m %r23(%sr4, %r26)
1214 fic,m %r23(%sr4, %r26)
1215 fic,m %r23(%sr4, %r26)
1216 fic,m %r23(%sr4, %r26)
1217 fic,m %r23(%sr4, %r26)
1218 fic,m %r23(%sr4, %r26)
1219 fic,m %r23(%sr4, %r26)
1220 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1221 fic,m %r23(%sr4, %r26)
1223 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1227 ENDPROC_CFI(flush_kernel_icache_page)
1229 ENTRY_CFI(flush_kernel_icache_range_asm)
1230 88: ldil L%icache_stride, %r1
1231 ldw R%icache_stride(%r1), %r23
1233 ANDCM %r26, %r21, %r26
1236 depd,z %r23, 59, 60, %r21
1238 depw,z %r23, 27, 28, %r21
1240 add %r26, %r21, %r22
1241 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1242 1: add %r22, %r21, %r22
1243 fic,m %r23(%sr4, %r26)
1244 fic,m %r23(%sr4, %r26)
1245 fic,m %r23(%sr4, %r26)
1246 fic,m %r23(%sr4, %r26)
1247 fic,m %r23(%sr4, %r26)
1248 fic,m %r23(%sr4, %r26)
1249 fic,m %r23(%sr4, %r26)
1250 fic,m %r23(%sr4, %r26)
1251 fic,m %r23(%sr4, %r26)
1252 fic,m %r23(%sr4, %r26)
1253 fic,m %r23(%sr4, %r26)
1254 fic,m %r23(%sr4, %r26)
1255 fic,m %r23(%sr4, %r26)
1256 fic,m %r23(%sr4, %r26)
1257 fic,m %r23(%sr4, %r26)
1258 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1259 fic,m %r23(%sr4, %r26)
1261 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1262 fic,m %r23(%sr4, %r26)
1264 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1268 ENDPROC_CFI(flush_kernel_icache_range_asm)
1272 /* align should cover use of rfi in disable_sr_hashing_asm and
1276 ENTRY_CFI(disable_sr_hashing_asm)
1278 * Switch to real mode
1289 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1290 mtctl %r0, %cr17 /* Clear IIASQ tail */
1291 mtctl %r0, %cr17 /* Clear IIASQ head */
1292 mtctl %r1, %cr18 /* IIAOQ head */
1294 mtctl %r1, %cr18 /* IIAOQ tail */
1295 load32 REAL_MODE_PSW, %r1
1300 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1301 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1302 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1307 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1309 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1310 .word 0x141c1a00 /* must issue twice */
1311 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1312 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1313 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1314 .word 0x141c1600 /* must issue twice */
1319 /* Disable Space Register Hashing for PCXL */
1321 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1322 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1323 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1328 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1330 .word 0x144008bc /* mfdiag %dr2, %r28 */
1331 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1332 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1336 /* Switch back to virtual mode */
1337 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1345 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1346 mtctl %r0, %cr17 /* Clear IIASQ tail */
1347 mtctl %r0, %cr17 /* Clear IIASQ head */
1348 mtctl %r1, %cr18 /* IIAOQ head */
1350 mtctl %r1, %cr18 /* IIAOQ tail */
1351 load32 KERNEL_PSW, %r1
1358 ENDPROC_CFI(disable_sr_hashing_asm)