1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PARISC TLB and cache flushing support
4 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
5 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
6 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
10 * NOTE: fdc,fic, and pdc instructions that use base register modification
11 * should only use index and base registers that are not shadowed,
12 * so that the fast path emulation in the non access miss handler
23 #include <asm/assembly.h>
24 #include <asm/pgtable.h>
25 #include <asm/cache.h>
27 #include <asm/alternative.h>
28 #include <linux/linkage.h>
29 #include <linux/init.h>
34 ENTRY_CFI(flush_tlb_all_local)
36 * The pitlbe and pdtlbe instructions should only be used to
37 * flush the entire tlb. Also, there needs to be no intervening
38 * tlb operations, e.g. tlb misses, so the operation needs
39 * to happen in real mode with all interruptions disabled.
42 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
43 rsm PSW_SM_I, %r19 /* save I-bit state */
51 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
52 mtctl %r0, %cr17 /* Clear IIASQ tail */
53 mtctl %r0, %cr17 /* Clear IIASQ head */
54 mtctl %r1, %cr18 /* IIAOQ head */
56 mtctl %r1, %cr18 /* IIAOQ tail */
57 load32 REAL_MODE_PSW, %r1
62 1: load32 PA(cache_info), %r1
64 /* Flush Instruction Tlb */
66 LDREG ITLB_SID_BASE(%r1), %r20
67 LDREG ITLB_SID_STRIDE(%r1), %r21
68 LDREG ITLB_SID_COUNT(%r1), %r22
69 LDREG ITLB_OFF_BASE(%r1), %arg0
70 LDREG ITLB_OFF_STRIDE(%r1), %arg1
71 LDREG ITLB_OFF_COUNT(%r1), %arg2
72 LDREG ITLB_LOOP(%r1), %arg3
74 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
75 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
76 copy %arg0, %r28 /* Init base addr */
78 fitmanyloop: /* Loop if LOOP >= 2 */
80 add %r21, %r20, %r20 /* increment space */
81 copy %arg2, %r29 /* Init middle loop count */
83 fitmanymiddle: /* Loop if LOOP >= 2 */
84 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
85 pitlbe %r0(%sr1, %r28)
86 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
87 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
88 copy %arg3, %r31 /* Re-init inner loop count */
90 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
91 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
93 fitoneloop: /* Loop if LOOP = 1 */
95 copy %arg0, %r28 /* init base addr */
96 copy %arg2, %r29 /* init middle loop count */
98 fitonemiddle: /* Loop if LOOP = 1 */
99 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
100 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
102 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
103 add %r21, %r20, %r20 /* increment space */
109 LDREG DTLB_SID_BASE(%r1), %r20
110 LDREG DTLB_SID_STRIDE(%r1), %r21
111 LDREG DTLB_SID_COUNT(%r1), %r22
112 LDREG DTLB_OFF_BASE(%r1), %arg0
113 LDREG DTLB_OFF_STRIDE(%r1), %arg1
114 LDREG DTLB_OFF_COUNT(%r1), %arg2
115 LDREG DTLB_LOOP(%r1), %arg3
117 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
118 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
119 copy %arg0, %r28 /* Init base addr */
121 fdtmanyloop: /* Loop if LOOP >= 2 */
123 add %r21, %r20, %r20 /* increment space */
124 copy %arg2, %r29 /* Init middle loop count */
126 fdtmanymiddle: /* Loop if LOOP >= 2 */
127 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
128 pdtlbe %r0(%sr1, %r28)
129 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
130 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
131 copy %arg3, %r31 /* Re-init inner loop count */
133 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
134 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
136 fdtoneloop: /* Loop if LOOP = 1 */
138 copy %arg0, %r28 /* init base addr */
139 copy %arg2, %r29 /* init middle loop count */
141 fdtonemiddle: /* Loop if LOOP = 1 */
142 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
143 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
145 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
146 add %r21, %r20, %r20 /* increment space */
151 * Switch back to virtual mode
162 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
163 mtctl %r0, %cr17 /* Clear IIASQ tail */
164 mtctl %r0, %cr17 /* Clear IIASQ head */
165 mtctl %r1, %cr18 /* IIAOQ head */
167 mtctl %r1, %cr18 /* IIAOQ tail */
168 load32 KERNEL_PSW, %r1
169 or %r1, %r19, %r1 /* I-bit to state on entry */
170 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
176 ENDPROC_CFI(flush_tlb_all_local)
178 .import cache_info,data
180 ENTRY_CFI(flush_instruction_cache_local)
181 88: load32 cache_info, %r1
183 /* Flush Instruction Cache */
185 LDREG ICACHE_BASE(%r1), %arg0
186 LDREG ICACHE_STRIDE(%r1), %arg1
187 LDREG ICACHE_COUNT(%r1), %arg2
188 LDREG ICACHE_LOOP(%r1), %arg3
189 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
191 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
192 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
194 fimanyloop: /* Loop if LOOP >= 2 */
195 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
196 fice %r0(%sr1, %arg0)
197 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
198 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
199 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
201 fioneloop: /* Loop if LOOP = 1 */
202 /* Some implementations may flush with a single fice instruction */
203 cmpib,COND(>>=),n 15, %arg2, fioneloop2
206 fice,m %arg1(%sr1, %arg0)
207 fice,m %arg1(%sr1, %arg0)
208 fice,m %arg1(%sr1, %arg0)
209 fice,m %arg1(%sr1, %arg0)
210 fice,m %arg1(%sr1, %arg0)
211 fice,m %arg1(%sr1, %arg0)
212 fice,m %arg1(%sr1, %arg0)
213 fice,m %arg1(%sr1, %arg0)
214 fice,m %arg1(%sr1, %arg0)
215 fice,m %arg1(%sr1, %arg0)
216 fice,m %arg1(%sr1, %arg0)
217 fice,m %arg1(%sr1, %arg0)
218 fice,m %arg1(%sr1, %arg0)
219 fice,m %arg1(%sr1, %arg0)
220 fice,m %arg1(%sr1, %arg0)
221 addib,COND(>) -16, %arg2, fioneloop1
222 fice,m %arg1(%sr1, %arg0)
225 cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
228 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
229 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
233 mtsm %r22 /* restore I-bit */
234 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
237 ENDPROC_CFI(flush_instruction_cache_local)
240 .import cache_info, data
241 ENTRY_CFI(flush_data_cache_local)
242 88: load32 cache_info, %r1
244 /* Flush Data Cache */
246 LDREG DCACHE_BASE(%r1), %arg0
247 LDREG DCACHE_STRIDE(%r1), %arg1
248 LDREG DCACHE_COUNT(%r1), %arg2
249 LDREG DCACHE_LOOP(%r1), %arg3
250 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
252 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
253 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
255 fdmanyloop: /* Loop if LOOP >= 2 */
256 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
257 fdce %r0(%sr1, %arg0)
258 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
259 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
260 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
262 fdoneloop: /* Loop if LOOP = 1 */
263 /* Some implementations may flush with a single fdce instruction */
264 cmpib,COND(>>=),n 15, %arg2, fdoneloop2
267 fdce,m %arg1(%sr1, %arg0)
268 fdce,m %arg1(%sr1, %arg0)
269 fdce,m %arg1(%sr1, %arg0)
270 fdce,m %arg1(%sr1, %arg0)
271 fdce,m %arg1(%sr1, %arg0)
272 fdce,m %arg1(%sr1, %arg0)
273 fdce,m %arg1(%sr1, %arg0)
274 fdce,m %arg1(%sr1, %arg0)
275 fdce,m %arg1(%sr1, %arg0)
276 fdce,m %arg1(%sr1, %arg0)
277 fdce,m %arg1(%sr1, %arg0)
278 fdce,m %arg1(%sr1, %arg0)
279 fdce,m %arg1(%sr1, %arg0)
280 fdce,m %arg1(%sr1, %arg0)
281 fdce,m %arg1(%sr1, %arg0)
282 addib,COND(>) -16, %arg2, fdoneloop1
283 fdce,m %arg1(%sr1, %arg0)
286 cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
289 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
290 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
295 mtsm %r22 /* restore I-bit */
296 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
299 ENDPROC_CFI(flush_data_cache_local)
301 /* Clear page using kernel mapping. */
303 ENTRY_CFI(clear_page_asm)
306 /* Unroll the loop. */
307 ldi (PAGE_SIZE / 128), %r1
327 /* Note reverse branch hint for addib is taken. */
328 addib,COND(>),n -1, %r1, 1b
334 * Note that until (if) we start saving the full 64-bit register
335 * values on interrupt, we can't use std on a 32 bit kernel.
337 ldi (PAGE_SIZE / 64), %r1
357 addib,COND(>),n -1, %r1, 1b
362 ENDPROC_CFI(clear_page_asm)
364 /* Copy page using kernel mapping. */
366 ENTRY_CFI(copy_page_asm)
368 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
369 * Unroll the loop by hand and arrange insn appropriately.
370 * Prefetch doesn't improve performance on rp3440.
371 * GCC probably can do this just as well...
374 ldi (PAGE_SIZE / 128), %r1
418 /* Note reverse branch hint for addib is taken. */
419 addib,COND(>),n -1, %r1, 1b
425 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
426 * bundles (very restricted rules for bundling).
427 * Note that until (if) we start saving
428 * the full 64 bit register values on interrupt, we can't
429 * use ldd/std on a 32 bit kernel.
432 ldi (PAGE_SIZE / 64), %r1
468 addib,COND(>),n -1, %r1, 1b
473 ENDPROC_CFI(copy_page_asm)
476 * NOTE: Code in clear_user_page has a hard coded dependency on the
477 * maximum alias boundary being 4 Mb. We've been assured by the
478 * parisc chip designers that there will not ever be a parisc
479 * chip with a larger alias boundary (Never say never :-) ).
481 * Subtle: the dtlb miss handlers support the temp alias region by
482 * "knowing" that if a dtlb miss happens within the temp alias
483 * region it must have occurred while in clear_user_page. Since
484 * this routine makes use of processor local translations, we
485 * don't want to insert them into the kernel page table. Instead,
486 * we load up some general registers (they need to be registers
487 * which aren't shadowed) with the physical page numbers (preshifted
488 * for tlb insertion) needed to insert the translations. When we
489 * miss on the translation, the dtlb miss handler inserts the
490 * translation into the tlb using these values:
492 * %r26 physical page (shifted for tlb insert) of "to" translation
493 * %r23 physical page (shifted for tlb insert) of "from" translation
496 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
497 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
498 .macro convert_phys_for_tlb_insert20 phys
499 extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
500 #if _PAGE_SIZE_ENCODING_DEFAULT
501 depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
506 * copy_user_page_asm() performs a page copy using mappings
507 * equivalent to the user page mappings. It can be used to
508 * implement copy_user_page() but unfortunately both the `from'
509 * and `to' pages need to be flushed through mappings equivalent
510 * to the user mappings after the copy because the kernel accesses
511 * the `from' page through the kmap kernel mapping and the `to'
512 * page needs to be flushed since code can be copied. As a
513 * result, this implementation is less efficient than the simpler
514 * copy using the kernel mapping. It only needs the `from' page
515 * to flushed via the user mapping. The kunmap routines handle
516 * the flushes needed for the kernel mapping.
518 * I'm still keeping this around because it may be possible to
519 * use it if more information is passed into copy_user_page().
520 * Have to do some measurements to see if it is worthwhile to
521 * lobby for such a change.
525 ENTRY_CFI(copy_user_page_asm)
526 /* Convert virtual `to' and `from' addresses to physical addresses.
527 Move `from' physical address to non shadowed register. */
528 ldil L%(__PAGE_OFFSET), %r1
532 ldil L%(TMPALIAS_MAP_START), %r28
534 #if (TMPALIAS_MAP_START >= 0x80000000)
535 depdi 0, 31,32, %r28 /* clear any sign extension */
537 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
538 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
539 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
540 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
542 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
544 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
545 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
546 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
547 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
549 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
552 /* Purge any old translations */
560 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
561 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
565 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
566 * Unroll the loop by hand and arrange insn appropriately.
567 * GCC probably can do this just as well.
571 ldi (PAGE_SIZE / 128), %r1
615 /* conditional branches nullify on forward taken branch, and on
616 * non-taken backward branch. Note that .+4 is a backwards branch.
617 * The ldd should only get executed if the branch is taken.
619 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
620 ldd 0(%r29), %r19 /* start next loads */
623 ldi (PAGE_SIZE / 64), %r1
626 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
627 * bundles (very restricted rules for bundling). It probably
628 * does OK on PCXU and better, but we could do better with
629 * ldd/std instructions. Note that until (if) we start saving
630 * the full 64 bit register values on interrupt, we can't
631 * use ldd/std on a 32 bit kernel.
668 addib,COND(>) -1, %r1,1b
674 ENDPROC_CFI(copy_user_page_asm)
676 ENTRY_CFI(clear_user_page_asm)
679 ldil L%(TMPALIAS_MAP_START), %r28
681 #if (TMPALIAS_MAP_START >= 0x80000000)
682 depdi 0, 31,32, %r28 /* clear any sign extension */
684 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
685 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
686 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
688 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
689 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
690 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
693 /* Purge any old translation */
699 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
703 ldi (PAGE_SIZE / 128), %r1
705 /* PREFETCH (Write) has not (yet) been proven to help here */
706 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
724 addib,COND(>) -1, %r1, 1b
727 #else /* ! CONFIG_64BIT */
728 ldi (PAGE_SIZE / 64), %r1
746 addib,COND(>) -1, %r1, 1b
748 #endif /* CONFIG_64BIT */
752 ENDPROC_CFI(clear_user_page_asm)
754 ENTRY_CFI(flush_dcache_page_asm)
755 ldil L%(TMPALIAS_MAP_START), %r28
757 #if (TMPALIAS_MAP_START >= 0x80000000)
758 depdi 0, 31,32, %r28 /* clear any sign extension */
760 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
761 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
762 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
764 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
765 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
766 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
769 /* Purge any old translation */
775 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
778 88: ldil L%dcache_stride, %r1
779 ldw R%dcache_stride(%r1), r31
782 depdi,z 1, 63-PAGE_SHIFT,1, %r25
784 depwi,z 1, 31-PAGE_SHIFT,1, %r25
804 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
807 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
811 ENDPROC_CFI(flush_dcache_page_asm)
813 ENTRY_CFI(purge_dcache_page_asm)
814 ldil L%(TMPALIAS_MAP_START), %r28
816 #if (TMPALIAS_MAP_START >= 0x80000000)
817 depdi 0, 31,32, %r28 /* clear any sign extension */
819 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
820 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
821 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
823 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
824 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
825 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
828 /* Purge any old translation */
834 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
837 88: ldil L%dcache_stride, %r1
838 ldw R%dcache_stride(%r1), r31
841 depdi,z 1, 63-PAGE_SHIFT,1, %r25
843 depwi,z 1, 31-PAGE_SHIFT,1, %r25
863 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
866 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
870 ENDPROC_CFI(purge_dcache_page_asm)
872 ENTRY_CFI(flush_icache_page_asm)
873 ldil L%(TMPALIAS_MAP_START), %r28
875 #if (TMPALIAS_MAP_START >= 0x80000000)
876 depdi 0, 31,32, %r28 /* clear any sign extension */
878 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
879 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
880 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
882 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
883 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
884 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
887 /* Purge any old translation. Note that the FIC instruction
888 * may use either the instruction or data TLB. Given that we
889 * have a flat address space, it's not clear which TLB will be
890 * used. So, we purge both entries. */
894 1: pitlb,l %r0(%sr4,%r28)
895 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
898 1: pitlb %r0(%sr4,%r28)
899 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
900 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
901 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
904 88: ldil L%icache_stride, %r1
905 ldw R%icache_stride(%r1), %r31
908 depdi,z 1, 63-PAGE_SHIFT,1, %r25
910 depwi,z 1, 31-PAGE_SHIFT,1, %r25
915 /* fic only has the type 26 form on PA1.1, requiring an
916 * explicit space specification, so use %sr4 */
917 1: fic,m %r31(%sr4,%r28)
918 fic,m %r31(%sr4,%r28)
919 fic,m %r31(%sr4,%r28)
920 fic,m %r31(%sr4,%r28)
921 fic,m %r31(%sr4,%r28)
922 fic,m %r31(%sr4,%r28)
923 fic,m %r31(%sr4,%r28)
924 fic,m %r31(%sr4,%r28)
925 fic,m %r31(%sr4,%r28)
926 fic,m %r31(%sr4,%r28)
927 fic,m %r31(%sr4,%r28)
928 fic,m %r31(%sr4,%r28)
929 fic,m %r31(%sr4,%r28)
930 fic,m %r31(%sr4,%r28)
931 fic,m %r31(%sr4,%r28)
932 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
933 fic,m %r31(%sr4,%r28)
935 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
939 ENDPROC_CFI(flush_icache_page_asm)
941 ENTRY_CFI(flush_kernel_dcache_page_asm)
942 88: ldil L%dcache_stride, %r1
943 ldw R%dcache_stride(%r1), %r23
946 depdi,z 1, 63-PAGE_SHIFT,1, %r25
948 depwi,z 1, 31-PAGE_SHIFT,1, %r25
968 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
971 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
975 ENDPROC_CFI(flush_kernel_dcache_page_asm)
977 ENTRY_CFI(purge_kernel_dcache_page_asm)
978 88: ldil L%dcache_stride, %r1
979 ldw R%dcache_stride(%r1), %r23
982 depdi,z 1, 63-PAGE_SHIFT,1, %r25
984 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1004 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1007 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1011 ENDPROC_CFI(purge_kernel_dcache_page_asm)
1013 ENTRY_CFI(flush_user_dcache_range_asm)
1014 88: ldil L%dcache_stride, %r1
1015 ldw R%dcache_stride(%r1), %r23
1017 ANDCM %r26, %r21, %r26
1020 depd,z %r23, 59, 60, %r21
1022 depw,z %r23, 27, 28, %r21
1024 add %r26, %r21, %r22
1025 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1026 1: add %r22, %r21, %r22
1027 fdc,m %r23(%sr3, %r26)
1028 fdc,m %r23(%sr3, %r26)
1029 fdc,m %r23(%sr3, %r26)
1030 fdc,m %r23(%sr3, %r26)
1031 fdc,m %r23(%sr3, %r26)
1032 fdc,m %r23(%sr3, %r26)
1033 fdc,m %r23(%sr3, %r26)
1034 fdc,m %r23(%sr3, %r26)
1035 fdc,m %r23(%sr3, %r26)
1036 fdc,m %r23(%sr3, %r26)
1037 fdc,m %r23(%sr3, %r26)
1038 fdc,m %r23(%sr3, %r26)
1039 fdc,m %r23(%sr3, %r26)
1040 fdc,m %r23(%sr3, %r26)
1041 fdc,m %r23(%sr3, %r26)
1042 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1043 fdc,m %r23(%sr3, %r26)
1045 2: cmpb,COND(>>),n %r25, %r26, 2b
1046 fdc,m %r23(%sr3, %r26)
1048 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1052 ENDPROC_CFI(flush_user_dcache_range_asm)
1054 ENTRY_CFI(flush_kernel_dcache_range_asm)
1055 88: ldil L%dcache_stride, %r1
1056 ldw R%dcache_stride(%r1), %r23
1058 ANDCM %r26, %r21, %r26
1061 depd,z %r23, 59, 60, %r21
1063 depw,z %r23, 27, 28, %r21
1065 add %r26, %r21, %r22
1066 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1067 1: add %r22, %r21, %r22
1083 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1086 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1090 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1094 ENDPROC_CFI(flush_kernel_dcache_range_asm)
1096 ENTRY_CFI(purge_kernel_dcache_range_asm)
1097 88: ldil L%dcache_stride, %r1
1098 ldw R%dcache_stride(%r1), %r23
1100 ANDCM %r26, %r21, %r26
1103 depd,z %r23, 59, 60, %r21
1105 depw,z %r23, 27, 28, %r21
1107 add %r26, %r21, %r22
1108 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1109 1: add %r22, %r21, %r22
1125 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1128 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1132 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1136 ENDPROC_CFI(purge_kernel_dcache_range_asm)
1138 ENTRY_CFI(flush_user_icache_range_asm)
1139 88: ldil L%icache_stride, %r1
1140 ldw R%icache_stride(%r1), %r23
1142 ANDCM %r26, %r21, %r26
1145 depd,z %r23, 59, 60, %r21
1147 depw,z %r23, 27, 28, %r21
1149 add %r26, %r21, %r22
1150 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1151 1: add %r22, %r21, %r22
1152 fic,m %r23(%sr3, %r26)
1153 fic,m %r23(%sr3, %r26)
1154 fic,m %r23(%sr3, %r26)
1155 fic,m %r23(%sr3, %r26)
1156 fic,m %r23(%sr3, %r26)
1157 fic,m %r23(%sr3, %r26)
1158 fic,m %r23(%sr3, %r26)
1159 fic,m %r23(%sr3, %r26)
1160 fic,m %r23(%sr3, %r26)
1161 fic,m %r23(%sr3, %r26)
1162 fic,m %r23(%sr3, %r26)
1163 fic,m %r23(%sr3, %r26)
1164 fic,m %r23(%sr3, %r26)
1165 fic,m %r23(%sr3, %r26)
1166 fic,m %r23(%sr3, %r26)
1167 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1168 fic,m %r23(%sr3, %r26)
1170 2: cmpb,COND(>>),n %r25, %r26, 2b
1171 fic,m %r23(%sr3, %r26)
1173 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1177 ENDPROC_CFI(flush_user_icache_range_asm)
1179 ENTRY_CFI(flush_kernel_icache_page)
1180 88: ldil L%icache_stride, %r1
1181 ldw R%icache_stride(%r1), %r23
1184 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1186 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1188 add %r26, %r25, %r25
1189 sub %r25, %r23, %r25
1192 1: fic,m %r23(%sr4, %r26)
1193 fic,m %r23(%sr4, %r26)
1194 fic,m %r23(%sr4, %r26)
1195 fic,m %r23(%sr4, %r26)
1196 fic,m %r23(%sr4, %r26)
1197 fic,m %r23(%sr4, %r26)
1198 fic,m %r23(%sr4, %r26)
1199 fic,m %r23(%sr4, %r26)
1200 fic,m %r23(%sr4, %r26)
1201 fic,m %r23(%sr4, %r26)
1202 fic,m %r23(%sr4, %r26)
1203 fic,m %r23(%sr4, %r26)
1204 fic,m %r23(%sr4, %r26)
1205 fic,m %r23(%sr4, %r26)
1206 fic,m %r23(%sr4, %r26)
1207 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1208 fic,m %r23(%sr4, %r26)
1210 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1214 ENDPROC_CFI(flush_kernel_icache_page)
1216 ENTRY_CFI(flush_kernel_icache_range_asm)
1217 88: ldil L%icache_stride, %r1
1218 ldw R%icache_stride(%r1), %r23
1220 ANDCM %r26, %r21, %r26
1223 depd,z %r23, 59, 60, %r21
1225 depw,z %r23, 27, 28, %r21
1227 add %r26, %r21, %r22
1228 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1229 1: add %r22, %r21, %r22
1230 fic,m %r23(%sr4, %r26)
1231 fic,m %r23(%sr4, %r26)
1232 fic,m %r23(%sr4, %r26)
1233 fic,m %r23(%sr4, %r26)
1234 fic,m %r23(%sr4, %r26)
1235 fic,m %r23(%sr4, %r26)
1236 fic,m %r23(%sr4, %r26)
1237 fic,m %r23(%sr4, %r26)
1238 fic,m %r23(%sr4, %r26)
1239 fic,m %r23(%sr4, %r26)
1240 fic,m %r23(%sr4, %r26)
1241 fic,m %r23(%sr4, %r26)
1242 fic,m %r23(%sr4, %r26)
1243 fic,m %r23(%sr4, %r26)
1244 fic,m %r23(%sr4, %r26)
1245 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1246 fic,m %r23(%sr4, %r26)
1248 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1249 fic,m %r23(%sr4, %r26)
1251 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1255 ENDPROC_CFI(flush_kernel_icache_range_asm)
1259 /* align should cover use of rfi in disable_sr_hashing_asm and
1263 ENTRY_CFI(disable_sr_hashing_asm)
1265 * Switch to real mode
1276 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1277 mtctl %r0, %cr17 /* Clear IIASQ tail */
1278 mtctl %r0, %cr17 /* Clear IIASQ head */
1279 mtctl %r1, %cr18 /* IIAOQ head */
1281 mtctl %r1, %cr18 /* IIAOQ tail */
1282 load32 REAL_MODE_PSW, %r1
1287 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1288 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1289 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1294 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1296 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1297 .word 0x141c1a00 /* must issue twice */
1298 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1299 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1300 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1301 .word 0x141c1600 /* must issue twice */
1306 /* Disable Space Register Hashing for PCXL */
1308 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1309 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1310 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1315 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1317 .word 0x144008bc /* mfdiag %dr2, %r28 */
1318 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1319 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1323 /* Switch back to virtual mode */
1324 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1332 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1333 mtctl %r0, %cr17 /* Clear IIASQ tail */
1334 mtctl %r0, %cr17 /* Clear IIASQ head */
1335 mtctl %r1, %cr18 /* IIAOQ head */
1337 mtctl %r1, %cr18 /* IIAOQ tail */
1338 load32 KERNEL_PSW, %r1
1345 ENDPROC_CFI(disable_sr_hashing_asm)