1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PARISC TLB and cache flushing support
4 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
5 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
6 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
10 * NOTE: fdc,fic, and pdc instructions that use base register modification
11 * should only use index and base registers that are not shadowed,
12 * so that the fast path emulation in the non access miss handler
23 #include <asm/assembly.h>
24 #include <asm/pgtable.h>
25 #include <asm/cache.h>
27 #include <asm/alternative.h>
28 #include <linux/linkage.h>
29 #include <linux/init.h>
34 ENTRY_CFI(flush_tlb_all_local)
36 * The pitlbe and pdtlbe instructions should only be used to
37 * flush the entire tlb. Also, there needs to be no intervening
38 * tlb operations, e.g. tlb misses, so the operation needs
39 * to happen in real mode with all interruptions disabled.
42 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
43 rsm PSW_SM_I, %r19 /* save I-bit state */
51 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
52 mtctl %r0, %cr17 /* Clear IIASQ tail */
53 mtctl %r0, %cr17 /* Clear IIASQ head */
54 mtctl %r1, %cr18 /* IIAOQ head */
56 mtctl %r1, %cr18 /* IIAOQ tail */
57 load32 REAL_MODE_PSW, %r1
62 1: load32 PA(cache_info), %r1
64 /* Flush Instruction Tlb */
66 88: LDREG ITLB_SID_BASE(%r1), %r20
67 LDREG ITLB_SID_STRIDE(%r1), %r21
68 LDREG ITLB_SID_COUNT(%r1), %r22
69 LDREG ITLB_OFF_BASE(%r1), %arg0
70 LDREG ITLB_OFF_STRIDE(%r1), %arg1
71 LDREG ITLB_OFF_COUNT(%r1), %arg2
72 LDREG ITLB_LOOP(%r1), %arg3
74 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
75 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
76 copy %arg0, %r28 /* Init base addr */
78 fitmanyloop: /* Loop if LOOP >= 2 */
80 add %r21, %r20, %r20 /* increment space */
81 copy %arg2, %r29 /* Init middle loop count */
83 fitmanymiddle: /* Loop if LOOP >= 2 */
84 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
85 pitlbe %r0(%sr1, %r28)
86 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
87 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
88 copy %arg3, %r31 /* Re-init inner loop count */
90 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
91 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
93 fitoneloop: /* Loop if LOOP = 1 */
95 copy %arg0, %r28 /* init base addr */
96 copy %arg2, %r29 /* init middle loop count */
98 fitonemiddle: /* Loop if LOOP = 1 */
99 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
100 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
102 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
103 add %r21, %r20, %r20 /* increment space */
106 ALTERNATIVE(88b, fitdone, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
110 LDREG DTLB_SID_BASE(%r1), %r20
111 LDREG DTLB_SID_STRIDE(%r1), %r21
112 LDREG DTLB_SID_COUNT(%r1), %r22
113 LDREG DTLB_OFF_BASE(%r1), %arg0
114 LDREG DTLB_OFF_STRIDE(%r1), %arg1
115 LDREG DTLB_OFF_COUNT(%r1), %arg2
116 LDREG DTLB_LOOP(%r1), %arg3
118 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
119 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
120 copy %arg0, %r28 /* Init base addr */
122 fdtmanyloop: /* Loop if LOOP >= 2 */
124 add %r21, %r20, %r20 /* increment space */
125 copy %arg2, %r29 /* Init middle loop count */
127 fdtmanymiddle: /* Loop if LOOP >= 2 */
128 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
129 pdtlbe %r0(%sr1, %r28)
130 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
131 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
132 copy %arg3, %r31 /* Re-init inner loop count */
134 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
135 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
137 fdtoneloop: /* Loop if LOOP = 1 */
139 copy %arg0, %r28 /* init base addr */
140 copy %arg2, %r29 /* init middle loop count */
142 fdtonemiddle: /* Loop if LOOP = 1 */
143 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
144 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
146 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
147 add %r21, %r20, %r20 /* increment space */
152 * Switch back to virtual mode
163 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
164 mtctl %r0, %cr17 /* Clear IIASQ tail */
165 mtctl %r0, %cr17 /* Clear IIASQ head */
166 mtctl %r1, %cr18 /* IIAOQ head */
168 mtctl %r1, %cr18 /* IIAOQ tail */
169 load32 KERNEL_PSW, %r1
170 or %r1, %r19, %r1 /* I-bit to state on entry */
171 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
177 ENDPROC_CFI(flush_tlb_all_local)
179 .import cache_info,data
181 ENTRY_CFI(flush_instruction_cache_local)
182 88: load32 cache_info, %r1
184 /* Flush Instruction Cache */
186 LDREG ICACHE_BASE(%r1), %arg0
187 LDREG ICACHE_STRIDE(%r1), %arg1
188 LDREG ICACHE_COUNT(%r1), %arg2
189 LDREG ICACHE_LOOP(%r1), %arg3
190 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
192 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
193 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
195 fimanyloop: /* Loop if LOOP >= 2 */
196 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
197 fice %r0(%sr1, %arg0)
198 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
199 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
200 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
202 fioneloop: /* Loop if LOOP = 1 */
203 /* Some implementations may flush with a single fice instruction */
204 cmpib,COND(>>=),n 15, %arg2, fioneloop2
207 fice,m %arg1(%sr1, %arg0)
208 fice,m %arg1(%sr1, %arg0)
209 fice,m %arg1(%sr1, %arg0)
210 fice,m %arg1(%sr1, %arg0)
211 fice,m %arg1(%sr1, %arg0)
212 fice,m %arg1(%sr1, %arg0)
213 fice,m %arg1(%sr1, %arg0)
214 fice,m %arg1(%sr1, %arg0)
215 fice,m %arg1(%sr1, %arg0)
216 fice,m %arg1(%sr1, %arg0)
217 fice,m %arg1(%sr1, %arg0)
218 fice,m %arg1(%sr1, %arg0)
219 fice,m %arg1(%sr1, %arg0)
220 fice,m %arg1(%sr1, %arg0)
221 fice,m %arg1(%sr1, %arg0)
222 addib,COND(>) -16, %arg2, fioneloop1
223 fice,m %arg1(%sr1, %arg0)
226 cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
229 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
230 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
234 mtsm %r22 /* restore I-bit */
235 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
238 ENDPROC_CFI(flush_instruction_cache_local)
241 .import cache_info, data
242 ENTRY_CFI(flush_data_cache_local)
243 88: load32 cache_info, %r1
245 /* Flush Data Cache */
247 LDREG DCACHE_BASE(%r1), %arg0
248 LDREG DCACHE_STRIDE(%r1), %arg1
249 LDREG DCACHE_COUNT(%r1), %arg2
250 LDREG DCACHE_LOOP(%r1), %arg3
251 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
253 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
254 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
256 fdmanyloop: /* Loop if LOOP >= 2 */
257 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
258 fdce %r0(%sr1, %arg0)
259 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
260 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
261 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
263 fdoneloop: /* Loop if LOOP = 1 */
264 /* Some implementations may flush with a single fdce instruction */
265 cmpib,COND(>>=),n 15, %arg2, fdoneloop2
268 fdce,m %arg1(%sr1, %arg0)
269 fdce,m %arg1(%sr1, %arg0)
270 fdce,m %arg1(%sr1, %arg0)
271 fdce,m %arg1(%sr1, %arg0)
272 fdce,m %arg1(%sr1, %arg0)
273 fdce,m %arg1(%sr1, %arg0)
274 fdce,m %arg1(%sr1, %arg0)
275 fdce,m %arg1(%sr1, %arg0)
276 fdce,m %arg1(%sr1, %arg0)
277 fdce,m %arg1(%sr1, %arg0)
278 fdce,m %arg1(%sr1, %arg0)
279 fdce,m %arg1(%sr1, %arg0)
280 fdce,m %arg1(%sr1, %arg0)
281 fdce,m %arg1(%sr1, %arg0)
282 fdce,m %arg1(%sr1, %arg0)
283 addib,COND(>) -16, %arg2, fdoneloop1
284 fdce,m %arg1(%sr1, %arg0)
287 cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
290 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
291 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
296 mtsm %r22 /* restore I-bit */
297 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
300 ENDPROC_CFI(flush_data_cache_local)
302 /* Clear page using kernel mapping. */
304 ENTRY_CFI(clear_page_asm)
307 /* Unroll the loop. */
308 ldi (PAGE_SIZE / 128), %r1
328 /* Note reverse branch hint for addib is taken. */
329 addib,COND(>),n -1, %r1, 1b
335 * Note that until (if) we start saving the full 64-bit register
336 * values on interrupt, we can't use std on a 32 bit kernel.
338 ldi (PAGE_SIZE / 64), %r1
358 addib,COND(>),n -1, %r1, 1b
363 ENDPROC_CFI(clear_page_asm)
365 /* Copy page using kernel mapping. */
367 ENTRY_CFI(copy_page_asm)
369 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
370 * Unroll the loop by hand and arrange insn appropriately.
371 * Prefetch doesn't improve performance on rp3440.
372 * GCC probably can do this just as well...
375 ldi (PAGE_SIZE / 128), %r1
419 /* Note reverse branch hint for addib is taken. */
420 addib,COND(>),n -1, %r1, 1b
426 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
427 * bundles (very restricted rules for bundling).
428 * Note that until (if) we start saving
429 * the full 64 bit register values on interrupt, we can't
430 * use ldd/std on a 32 bit kernel.
433 ldi (PAGE_SIZE / 64), %r1
469 addib,COND(>),n -1, %r1, 1b
474 ENDPROC_CFI(copy_page_asm)
477 * NOTE: Code in clear_user_page has a hard coded dependency on the
478 * maximum alias boundary being 4 Mb. We've been assured by the
479 * parisc chip designers that there will not ever be a parisc
480 * chip with a larger alias boundary (Never say never :-) ).
482 * Subtle: the dtlb miss handlers support the temp alias region by
483 * "knowing" that if a dtlb miss happens within the temp alias
484 * region it must have occurred while in clear_user_page. Since
485 * this routine makes use of processor local translations, we
486 * don't want to insert them into the kernel page table. Instead,
487 * we load up some general registers (they need to be registers
488 * which aren't shadowed) with the physical page numbers (preshifted
489 * for tlb insertion) needed to insert the translations. When we
490 * miss on the translation, the dtlb miss handler inserts the
491 * translation into the tlb using these values:
493 * %r26 physical page (shifted for tlb insert) of "to" translation
494 * %r23 physical page (shifted for tlb insert) of "from" translation
497 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
498 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
499 .macro convert_phys_for_tlb_insert20 phys
500 extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
501 #if _PAGE_SIZE_ENCODING_DEFAULT
502 depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
507 * copy_user_page_asm() performs a page copy using mappings
508 * equivalent to the user page mappings. It can be used to
509 * implement copy_user_page() but unfortunately both the `from'
510 * and `to' pages need to be flushed through mappings equivalent
511 * to the user mappings after the copy because the kernel accesses
512 * the `from' page through the kmap kernel mapping and the `to'
513 * page needs to be flushed since code can be copied. As a
514 * result, this implementation is less efficient than the simpler
515 * copy using the kernel mapping. It only needs the `from' page
516 * to flushed via the user mapping. The kunmap routines handle
517 * the flushes needed for the kernel mapping.
519 * I'm still keeping this around because it may be possible to
520 * use it if more information is passed into copy_user_page().
521 * Have to do some measurements to see if it is worthwhile to
522 * lobby for such a change.
526 ENTRY_CFI(copy_user_page_asm)
527 /* Convert virtual `to' and `from' addresses to physical addresses.
528 Move `from' physical address to non shadowed register. */
529 ldil L%(__PAGE_OFFSET), %r1
533 ldil L%(TMPALIAS_MAP_START), %r28
535 #if (TMPALIAS_MAP_START >= 0x80000000)
536 depdi 0, 31,32, %r28 /* clear any sign extension */
538 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
539 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
540 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
541 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
543 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
545 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
546 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
547 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
548 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
550 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
553 /* Purge any old translations */
561 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
562 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
566 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
567 * Unroll the loop by hand and arrange insn appropriately.
568 * GCC probably can do this just as well.
572 ldi (PAGE_SIZE / 128), %r1
616 /* conditional branches nullify on forward taken branch, and on
617 * non-taken backward branch. Note that .+4 is a backwards branch.
618 * The ldd should only get executed if the branch is taken.
620 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
621 ldd 0(%r29), %r19 /* start next loads */
624 ldi (PAGE_SIZE / 64), %r1
627 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
628 * bundles (very restricted rules for bundling). It probably
629 * does OK on PCXU and better, but we could do better with
630 * ldd/std instructions. Note that until (if) we start saving
631 * the full 64 bit register values on interrupt, we can't
632 * use ldd/std on a 32 bit kernel.
669 addib,COND(>) -1, %r1,1b
675 ENDPROC_CFI(copy_user_page_asm)
677 ENTRY_CFI(clear_user_page_asm)
680 ldil L%(TMPALIAS_MAP_START), %r28
682 #if (TMPALIAS_MAP_START >= 0x80000000)
683 depdi 0, 31,32, %r28 /* clear any sign extension */
685 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
686 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
687 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
689 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
690 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
691 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
694 /* Purge any old translation */
700 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
704 ldi (PAGE_SIZE / 128), %r1
706 /* PREFETCH (Write) has not (yet) been proven to help here */
707 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
725 addib,COND(>) -1, %r1, 1b
728 #else /* ! CONFIG_64BIT */
729 ldi (PAGE_SIZE / 64), %r1
747 addib,COND(>) -1, %r1, 1b
749 #endif /* CONFIG_64BIT */
753 ENDPROC_CFI(clear_user_page_asm)
755 ENTRY_CFI(flush_dcache_page_asm)
756 ldil L%(TMPALIAS_MAP_START), %r28
758 #if (TMPALIAS_MAP_START >= 0x80000000)
759 depdi 0, 31,32, %r28 /* clear any sign extension */
761 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
762 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
763 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
765 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
766 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
767 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
770 /* Purge any old translation */
776 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
779 88: ldil L%dcache_stride, %r1
780 ldw R%dcache_stride(%r1), r31
783 depdi,z 1, 63-PAGE_SHIFT,1, %r25
785 depwi,z 1, 31-PAGE_SHIFT,1, %r25
805 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
808 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
812 ENDPROC_CFI(flush_dcache_page_asm)
814 ENTRY_CFI(purge_dcache_page_asm)
815 ldil L%(TMPALIAS_MAP_START), %r28
817 #if (TMPALIAS_MAP_START >= 0x80000000)
818 depdi 0, 31,32, %r28 /* clear any sign extension */
820 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
821 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
822 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
824 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
825 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
826 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
829 /* Purge any old translation */
835 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
838 88: ldil L%dcache_stride, %r1
839 ldw R%dcache_stride(%r1), r31
842 depdi,z 1, 63-PAGE_SHIFT,1, %r25
844 depwi,z 1, 31-PAGE_SHIFT,1, %r25
864 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
867 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
871 ENDPROC_CFI(purge_dcache_page_asm)
873 ENTRY_CFI(flush_icache_page_asm)
874 ldil L%(TMPALIAS_MAP_START), %r28
876 #if (TMPALIAS_MAP_START >= 0x80000000)
877 depdi 0, 31,32, %r28 /* clear any sign extension */
879 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
880 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
881 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
883 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
884 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
885 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
888 /* Purge any old translation. Note that the FIC instruction
889 * may use either the instruction or data TLB. Given that we
890 * have a flat address space, it's not clear which TLB will be
891 * used. So, we purge both entries. */
895 1: pitlb,l %r0(%sr4,%r28)
896 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
899 1: pitlb %r0(%sr4,%r28)
900 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
901 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
902 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
905 88: ldil L%icache_stride, %r1
906 ldw R%icache_stride(%r1), %r31
909 depdi,z 1, 63-PAGE_SHIFT,1, %r25
911 depwi,z 1, 31-PAGE_SHIFT,1, %r25
916 /* fic only has the type 26 form on PA1.1, requiring an
917 * explicit space specification, so use %sr4 */
918 1: fic,m %r31(%sr4,%r28)
919 fic,m %r31(%sr4,%r28)
920 fic,m %r31(%sr4,%r28)
921 fic,m %r31(%sr4,%r28)
922 fic,m %r31(%sr4,%r28)
923 fic,m %r31(%sr4,%r28)
924 fic,m %r31(%sr4,%r28)
925 fic,m %r31(%sr4,%r28)
926 fic,m %r31(%sr4,%r28)
927 fic,m %r31(%sr4,%r28)
928 fic,m %r31(%sr4,%r28)
929 fic,m %r31(%sr4,%r28)
930 fic,m %r31(%sr4,%r28)
931 fic,m %r31(%sr4,%r28)
932 fic,m %r31(%sr4,%r28)
933 cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
934 fic,m %r31(%sr4,%r28)
936 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
940 ENDPROC_CFI(flush_icache_page_asm)
942 ENTRY_CFI(flush_kernel_dcache_page_asm)
943 88: ldil L%dcache_stride, %r1
944 ldw R%dcache_stride(%r1), %r23
947 depdi,z 1, 63-PAGE_SHIFT,1, %r25
949 depwi,z 1, 31-PAGE_SHIFT,1, %r25
969 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
972 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
976 ENDPROC_CFI(flush_kernel_dcache_page_asm)
978 ENTRY_CFI(purge_kernel_dcache_page_asm)
979 88: ldil L%dcache_stride, %r1
980 ldw R%dcache_stride(%r1), %r23
983 depdi,z 1, 63-PAGE_SHIFT,1, %r25
985 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1005 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1008 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1012 ENDPROC_CFI(purge_kernel_dcache_page_asm)
1014 ENTRY_CFI(flush_user_dcache_range_asm)
1015 88: ldil L%dcache_stride, %r1
1016 ldw R%dcache_stride(%r1), %r23
1018 ANDCM %r26, %r21, %r26
1021 depd,z %r23, 59, 60, %r21
1023 depw,z %r23, 27, 28, %r21
1025 add %r26, %r21, %r22
1026 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1027 1: add %r22, %r21, %r22
1028 fdc,m %r23(%sr3, %r26)
1029 fdc,m %r23(%sr3, %r26)
1030 fdc,m %r23(%sr3, %r26)
1031 fdc,m %r23(%sr3, %r26)
1032 fdc,m %r23(%sr3, %r26)
1033 fdc,m %r23(%sr3, %r26)
1034 fdc,m %r23(%sr3, %r26)
1035 fdc,m %r23(%sr3, %r26)
1036 fdc,m %r23(%sr3, %r26)
1037 fdc,m %r23(%sr3, %r26)
1038 fdc,m %r23(%sr3, %r26)
1039 fdc,m %r23(%sr3, %r26)
1040 fdc,m %r23(%sr3, %r26)
1041 fdc,m %r23(%sr3, %r26)
1042 fdc,m %r23(%sr3, %r26)
1043 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1044 fdc,m %r23(%sr3, %r26)
1046 2: cmpb,COND(>>),n %r25, %r26, 2b
1047 fdc,m %r23(%sr3, %r26)
1049 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1053 ENDPROC_CFI(flush_user_dcache_range_asm)
1055 ENTRY_CFI(flush_kernel_dcache_range_asm)
1056 88: ldil L%dcache_stride, %r1
1057 ldw R%dcache_stride(%r1), %r23
1059 ANDCM %r26, %r21, %r26
1062 depd,z %r23, 59, 60, %r21
1064 depw,z %r23, 27, 28, %r21
1066 add %r26, %r21, %r22
1067 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1068 1: add %r22, %r21, %r22
1084 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1087 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1091 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1095 ENDPROC_CFI(flush_kernel_dcache_range_asm)
1097 ENTRY_CFI(purge_kernel_dcache_range_asm)
1098 88: ldil L%dcache_stride, %r1
1099 ldw R%dcache_stride(%r1), %r23
1101 ANDCM %r26, %r21, %r26
1104 depd,z %r23, 59, 60, %r21
1106 depw,z %r23, 27, 28, %r21
1108 add %r26, %r21, %r22
1109 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1110 1: add %r22, %r21, %r22
1126 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1129 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1133 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1137 ENDPROC_CFI(purge_kernel_dcache_range_asm)
1139 ENTRY_CFI(flush_user_icache_range_asm)
1140 88: ldil L%icache_stride, %r1
1141 ldw R%icache_stride(%r1), %r23
1143 ANDCM %r26, %r21, %r26
1146 depd,z %r23, 59, 60, %r21
1148 depw,z %r23, 27, 28, %r21
1150 add %r26, %r21, %r22
1151 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1152 1: add %r22, %r21, %r22
1153 fic,m %r23(%sr3, %r26)
1154 fic,m %r23(%sr3, %r26)
1155 fic,m %r23(%sr3, %r26)
1156 fic,m %r23(%sr3, %r26)
1157 fic,m %r23(%sr3, %r26)
1158 fic,m %r23(%sr3, %r26)
1159 fic,m %r23(%sr3, %r26)
1160 fic,m %r23(%sr3, %r26)
1161 fic,m %r23(%sr3, %r26)
1162 fic,m %r23(%sr3, %r26)
1163 fic,m %r23(%sr3, %r26)
1164 fic,m %r23(%sr3, %r26)
1165 fic,m %r23(%sr3, %r26)
1166 fic,m %r23(%sr3, %r26)
1167 fic,m %r23(%sr3, %r26)
1168 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1169 fic,m %r23(%sr3, %r26)
1171 2: cmpb,COND(>>),n %r25, %r26, 2b
1172 fic,m %r23(%sr3, %r26)
1174 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1178 ENDPROC_CFI(flush_user_icache_range_asm)
1180 ENTRY_CFI(flush_kernel_icache_page)
1181 88: ldil L%icache_stride, %r1
1182 ldw R%icache_stride(%r1), %r23
1185 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1187 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1189 add %r26, %r25, %r25
1190 sub %r25, %r23, %r25
1193 1: fic,m %r23(%sr4, %r26)
1194 fic,m %r23(%sr4, %r26)
1195 fic,m %r23(%sr4, %r26)
1196 fic,m %r23(%sr4, %r26)
1197 fic,m %r23(%sr4, %r26)
1198 fic,m %r23(%sr4, %r26)
1199 fic,m %r23(%sr4, %r26)
1200 fic,m %r23(%sr4, %r26)
1201 fic,m %r23(%sr4, %r26)
1202 fic,m %r23(%sr4, %r26)
1203 fic,m %r23(%sr4, %r26)
1204 fic,m %r23(%sr4, %r26)
1205 fic,m %r23(%sr4, %r26)
1206 fic,m %r23(%sr4, %r26)
1207 fic,m %r23(%sr4, %r26)
1208 cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
1209 fic,m %r23(%sr4, %r26)
1211 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1215 ENDPROC_CFI(flush_kernel_icache_page)
1217 ENTRY_CFI(flush_kernel_icache_range_asm)
1218 88: ldil L%icache_stride, %r1
1219 ldw R%icache_stride(%r1), %r23
1221 ANDCM %r26, %r21, %r26
1224 depd,z %r23, 59, 60, %r21
1226 depw,z %r23, 27, 28, %r21
1228 add %r26, %r21, %r22
1229 cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
1230 1: add %r22, %r21, %r22
1231 fic,m %r23(%sr4, %r26)
1232 fic,m %r23(%sr4, %r26)
1233 fic,m %r23(%sr4, %r26)
1234 fic,m %r23(%sr4, %r26)
1235 fic,m %r23(%sr4, %r26)
1236 fic,m %r23(%sr4, %r26)
1237 fic,m %r23(%sr4, %r26)
1238 fic,m %r23(%sr4, %r26)
1239 fic,m %r23(%sr4, %r26)
1240 fic,m %r23(%sr4, %r26)
1241 fic,m %r23(%sr4, %r26)
1242 fic,m %r23(%sr4, %r26)
1243 fic,m %r23(%sr4, %r26)
1244 fic,m %r23(%sr4, %r26)
1245 fic,m %r23(%sr4, %r26)
1246 cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
1247 fic,m %r23(%sr4, %r26)
1249 2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
1250 fic,m %r23(%sr4, %r26)
1252 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1256 ENDPROC_CFI(flush_kernel_icache_range_asm)
1260 /* align should cover use of rfi in disable_sr_hashing_asm and
1264 ENTRY_CFI(disable_sr_hashing_asm)
1266 * Switch to real mode
1277 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1278 mtctl %r0, %cr17 /* Clear IIASQ tail */
1279 mtctl %r0, %cr17 /* Clear IIASQ head */
1280 mtctl %r1, %cr18 /* IIAOQ head */
1282 mtctl %r1, %cr18 /* IIAOQ tail */
1283 load32 REAL_MODE_PSW, %r1
1288 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1289 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1290 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1295 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1297 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1298 .word 0x141c1a00 /* must issue twice */
1299 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1300 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1301 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1302 .word 0x141c1600 /* must issue twice */
1307 /* Disable Space Register Hashing for PCXL */
1309 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1310 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1311 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1316 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1318 .word 0x144008bc /* mfdiag %dr2, %r28 */
1319 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1320 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1324 /* Switch back to virtual mode */
1325 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1333 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1334 mtctl %r0, %cr17 /* Clear IIASQ tail */
1335 mtctl %r0, %cr17 /* Clear IIASQ head */
1336 mtctl %r1, %cr18 /* IIAOQ head */
1338 mtctl %r1, %cr18 /* IIAOQ tail */
1339 load32 KERNEL_PSW, %r1
1346 ENDPROC_CFI(disable_sr_hashing_asm)