1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _PARISC_PGTABLE_H
3 #define _PARISC_PGTABLE_H
5 #include <asm-generic/4level-fixup.h>
7 #include <asm/fixmap.h>
11 * we simulate an x86-style page table for the linux mm code
14 #include <linux/bitops.h>
15 #include <linux/spinlock.h>
16 #include <linux/mm_types.h>
17 #include <asm/processor.h>
18 #include <asm/cache.h>
20 static inline spinlock_t *pgd_spinlock(pgd_t *);
23 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
24 * memory. For the return value to be meaningful, ADDR must be >=
25 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
26 * require a hash-, or multi-level tree-lookup or something of that
27 * sort) but it guarantees to return TRUE only if accessing the page
28 * at that address does not cause an error. Note that there may be
29 * addresses for which kern_addr_valid() returns FALSE even though an
30 * access would not cause an error (e.g., this is typically true for
31 * memory mapped I/O regions.
33 * XXX Need to implement this for parisc.
35 #define kern_addr_valid(addr) (1)
37 /* This is for the serialization of PxTLB broadcasts. At least on the N class
38 * systems, only one PxTLB inter processor broadcast can be active at any one
39 * time on the Merced bus.
41 * PTE updates are protected by locks in the PMD.
43 extern spinlock_t pa_tlb_flush_lock;
44 extern spinlock_t pa_swapper_pg_lock;
45 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
46 extern int pa_serialize_tlb_flushes;
48 #define pa_serialize_tlb_flushes (0)
51 #define purge_tlb_start(flags) do { \
52 if (pa_serialize_tlb_flushes) \
53 spin_lock_irqsave(&pa_tlb_flush_lock, flags); \
55 local_irq_save(flags); \
57 #define purge_tlb_end(flags) do { \
58 if (pa_serialize_tlb_flushes) \
59 spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \
61 local_irq_restore(flags); \
64 /* Purge data and instruction TLB entries. The TLB purge instructions
65 * are slow on SMP machines since the purge must be broadcast to all CPUs.
68 static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
72 purge_tlb_start(flags);
79 /* Certain architectures need to do special things when PTEs
80 * within a page table are directly modified. Thus, the following
81 * hook is made available.
83 #define set_pte(pteptr, pteval) \
85 *(pteptr) = (pteval); \
88 #define set_pte_at(mm, addr, ptep, pteval) \
91 unsigned long flags; \
92 spin_lock_irqsave(pgd_spinlock((mm)->pgd), flags);\
94 set_pte(ptep, pteval); \
95 purge_tlb_entries(mm, addr); \
96 spin_unlock_irqrestore(pgd_spinlock((mm)->pgd), flags);\
99 #endif /* !__ASSEMBLY__ */
101 #include <asm/page.h>
103 #define pte_ERROR(e) \
104 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
105 #define pmd_ERROR(e) \
106 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
107 #define pgd_ERROR(e) \
108 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
110 /* This is the size of the initially mapped kernel memory */
111 #if defined(CONFIG_64BIT)
112 #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
114 #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
116 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
118 #if CONFIG_PGTABLE_LEVELS == 3
119 #define PGD_ORDER 1 /* Number of pages per pgd */
120 #define PMD_ORDER 1 /* Number of pages per pmd */
121 #define PGD_ALLOC_ORDER (2 + 1) /* first pgd contains pmd */
123 #define PGD_ORDER 1 /* Number of pages per pgd */
124 #define PGD_ALLOC_ORDER (PGD_ORDER + 1)
127 /* Definitions for 3rd level (we use PLD here for Page Lower directory
128 * because PTE_SHIFT is used lower down to mean shift that has to be
129 * done to get usable bits out of the PTE) */
130 #define PLD_SHIFT PAGE_SHIFT
131 #define PLD_SIZE PAGE_SIZE
132 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
133 #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
135 /* Definitions for 2nd level */
136 #define pgtable_cache_init() do { } while (0)
138 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
139 #define PMD_SIZE (1UL << PMD_SHIFT)
140 #define PMD_MASK (~(PMD_SIZE-1))
141 #if CONFIG_PGTABLE_LEVELS == 3
142 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
144 #define __PAGETABLE_PMD_FOLDED 1
145 #define BITS_PER_PMD 0
147 #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
149 /* Definitions for 1st level */
150 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
151 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
152 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
154 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
156 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
157 #define PGDIR_MASK (~(PGDIR_SIZE-1))
158 #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
159 #define USER_PTRS_PER_PGD PTRS_PER_PGD
162 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
163 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
164 #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
166 #define MAX_ADDRBITS (BITS_PER_LONG)
167 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
168 #define SPACEID_SHIFT 0
171 /* This calculates the number of initial pages we need for the initial
173 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
174 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
176 # define PT_INITIAL (1) /* all initial PTEs fit into one page */
180 * pgd entries used up by user/kernel:
183 #define FIRST_USER_ADDRESS 0UL
185 /* NB: The tlb miss handlers make certain assumptions about the order */
186 /* of the following bits, so be careful (One example, bits 25-31 */
187 /* are moved together in one instruction). */
189 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
190 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
191 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
192 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
193 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
194 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
195 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
196 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
197 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
198 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
199 #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
200 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
202 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
203 /* following macro is ok for both 32 and 64 bit. */
205 #define xlate_pabit(x) (31 - x)
207 /* this defines the shift to the usable bits in the PTE it is set so
208 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
210 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
212 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
213 #define PFN_PTE_SHIFT 12
215 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
216 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
217 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
218 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
219 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
220 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
221 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
222 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
223 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
224 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
225 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
226 #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
227 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
229 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
230 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
231 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
232 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
233 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
234 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
236 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
237 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
238 * for a few meta-information bits, so we shift the address to be
239 * able to effectively address 40/42/44-bits of physical address space
240 * depending on 4k/16k/64k PAGE_SIZE */
241 #define _PxD_PRESENT_BIT 31
242 #define _PxD_ATTACHED_BIT 30
243 #define _PxD_VALID_BIT 29
245 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
246 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
247 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
248 #define PxD_FLAG_MASK (0xf)
249 #define PxD_FLAG_SHIFT (4)
250 #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
254 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
255 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
256 /* Others seem to make this executable, I don't know if that's correct
257 or not. The stack is mapped this way though so this is necessary
258 in the short term - dhd@linuxcare.com, 2000-08-08 */
259 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
260 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
261 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
262 #define PAGE_COPY PAGE_EXECREAD
263 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
264 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
265 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
266 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
267 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
268 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
269 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
273 * We could have an execute only page using "gateway - promote to priv
274 * level 3", but that is kind of silly. So, the way things are defined
275 * now, we must always have read permission for pages with execute
276 * permission. For the fun of it we'll go ahead and support write only
281 #define __P000 PAGE_NONE
282 #define __P001 PAGE_READONLY
283 #define __P010 __P000 /* copy on write */
284 #define __P011 __P001 /* copy on write */
285 #define __P100 PAGE_EXECREAD
286 #define __P101 PAGE_EXECREAD
287 #define __P110 __P100 /* copy on write */
288 #define __P111 __P101 /* copy on write */
290 #define __S000 PAGE_NONE
291 #define __S001 PAGE_READONLY
292 #define __S010 PAGE_WRITEONLY
293 #define __S011 PAGE_SHARED
294 #define __S100 PAGE_EXECREAD
295 #define __S101 PAGE_EXECREAD
296 #define __S110 PAGE_RWX
297 #define __S111 PAGE_RWX
300 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
302 /* initial page tables for 0-8MB for kernel */
306 /* zero page used for uninitialized stuff */
308 extern unsigned long *empty_zero_page;
311 * ZERO_PAGE is a global shared page that is always zero: used
312 * for zero-mapped memory areas etc..
315 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
317 #define pte_none(x) (pte_val(x) == 0)
318 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
319 #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
321 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
322 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
323 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
324 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
326 #if CONFIG_PGTABLE_LEVELS == 3
327 /* The first entry of the permanent pmd is not there if it contains
328 * the gateway marker */
329 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
331 #define pmd_none(x) (!pmd_val(x))
333 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
334 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
335 static inline void pmd_clear(pmd_t *pmd) {
336 #if CONFIG_PGTABLE_LEVELS == 3
337 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
338 /* This is the entry pointing to the permanent pmd
339 * attached to the pgd; cannot clear it */
340 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
343 __pmd_val_set(*pmd, 0);
348 #if CONFIG_PGTABLE_LEVELS == 3
349 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
350 #define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd))
352 /* For 64 bit we have three level tables */
354 #define pgd_none(x) (!pgd_val(x))
355 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
356 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
357 static inline void pgd_clear(pgd_t *pgd) {
358 #if CONFIG_PGTABLE_LEVELS == 3
359 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
360 /* This is the permanent pmd attached to the pgd; cannot
364 __pgd_val_set(*pgd, 0);
368 * The "pgd_xxx()" functions here are trivial for a folded two-level
369 * setup: the pgd is never bad, and a pmd always exists (as it's folded
370 * into the pgd entry)
372 static inline int pgd_none(pgd_t pgd) { return 0; }
373 static inline int pgd_bad(pgd_t pgd) { return 0; }
374 static inline int pgd_present(pgd_t pgd) { return 1; }
375 static inline void pgd_clear(pgd_t * pgdp) { }
379 * The following only work if pte_present() is true.
380 * Undefined behaviour if not..
382 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
383 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
384 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
385 static inline int pte_special(pte_t pte) { return 0; }
387 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
388 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
389 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
390 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
391 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
392 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
393 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
396 * Huge pte definitions.
398 #ifdef CONFIG_HUGETLB_PAGE
399 #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
400 #define pte_mkhuge(pte) (__pte(pte_val(pte) | \
401 (parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
403 #define pte_huge(pte) (0)
404 #define pte_mkhuge(pte) (pte)
409 * Conversion functions: convert a page and protection to a page entry,
410 * and a page entry and page directory to the page they refer to.
412 #define __mk_pte(addr,pgprot) \
416 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
421 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
423 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
426 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
430 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
431 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
433 /* Permanent address of a page. On parisc we don't have highmem. */
435 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
437 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
439 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd)))
441 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
442 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
444 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
446 /* to find an entry in a page-table-directory */
447 #define pgd_offset(mm, address) \
448 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
450 /* to find an entry in a kernel page-table-directory */
451 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
453 /* Find an entry in the second-level page table.. */
455 #if CONFIG_PGTABLE_LEVELS == 3
456 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
457 #define pmd_offset(dir,address) \
458 ((pmd_t *) pgd_page_vaddr(*(dir)) + pmd_index(address))
460 #define pmd_offset(dir,addr) ((pmd_t *) dir)
463 /* Find an entry in the third-level page table.. */
464 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
465 #define pte_offset_kernel(pmd, address) \
466 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
467 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
468 #define pte_unmap(pte) do { } while (0)
470 #define pte_unmap(pte) do { } while (0)
471 #define pte_unmap_nested(pte) do { } while (0)
473 extern void paging_init (void);
475 /* Used for deferring calls to flush_dcache_page() */
477 #define PG_dcache_dirty PG_arch_1
479 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
481 /* Encode and de-code a swap entry */
483 #define __swp_type(x) ((x).val & 0x1f)
484 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
485 (((x).val >> 8) & ~0x7) )
486 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
487 ((offset & 0x7) << 6) | \
488 ((offset & ~0x7) << 8) })
489 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
490 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
493 static inline spinlock_t *pgd_spinlock(pgd_t *pgd)
495 if (unlikely(pgd == swapper_pg_dir))
496 return &pa_swapper_pg_lock;
497 return (spinlock_t *)((char *)pgd + (PAGE_SIZE << (PGD_ALLOC_ORDER - 1)));
501 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
506 if (!pte_young(*ptep))
509 spin_lock_irqsave(pgd_spinlock(vma->vm_mm->pgd), flags);
511 if (!pte_young(pte)) {
512 spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags);
515 set_pte(ptep, pte_mkold(pte));
516 purge_tlb_entries(vma->vm_mm, addr);
517 spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags);
522 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
527 spin_lock_irqsave(pgd_spinlock(mm->pgd), flags);
529 set_pte(ptep, __pte(0));
530 purge_tlb_entries(mm, addr);
531 spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags);
536 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
539 spin_lock_irqsave(pgd_spinlock(mm->pgd), flags);
540 set_pte(ptep, pte_wrprotect(*ptep));
541 purge_tlb_entries(mm, addr);
542 spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags);
545 #define pte_same(A,B) (pte_val(A) == pte_val(B))
548 extern void arch_report_meminfo(struct seq_file *m);
550 #endif /* !__ASSEMBLY__ */
553 /* TLB page size encoding - see table 3-1 in parisc20.pdf */
554 #define _PAGE_SIZE_ENCODING_4K 0
555 #define _PAGE_SIZE_ENCODING_16K 1
556 #define _PAGE_SIZE_ENCODING_64K 2
557 #define _PAGE_SIZE_ENCODING_256K 3
558 #define _PAGE_SIZE_ENCODING_1M 4
559 #define _PAGE_SIZE_ENCODING_4M 5
560 #define _PAGE_SIZE_ENCODING_16M 6
561 #define _PAGE_SIZE_ENCODING_64M 7
563 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
564 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
565 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
566 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
567 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
568 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
572 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
574 /* We provide our own get_unmapped_area to provide cache coherency */
576 #define HAVE_ARCH_UNMAPPED_AREA
577 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
579 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
580 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
581 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
582 #define __HAVE_ARCH_PTE_SAME
583 #include <asm-generic/pgtable.h>
585 #endif /* _PARISC_PGTABLE_H */