1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.rst.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15 select OF_EARLY_FLATTREE
18 select HAVE_ARCH_TRACEHOOK
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
24 select GENERIC_CPU_DEVICES
26 select GENERIC_ATOMIC64
27 select GENERIC_CLOCKEVENTS_BROADCAST
28 select GENERIC_SMP_IDLE_THREAD
29 select MODULES_USE_ELF_RELA
30 select HAVE_DEBUG_STACKOVERFLOW
32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
33 select ARCH_USE_QUEUED_SPINLOCKS
34 select ARCH_USE_QUEUED_RWLOCKS
36 select ARCH_WANT_FRAME_POINTERS
37 select GENERIC_IRQ_MULTI_HANDLER
38 select MMU_GATHER_NO_RANGE if MMU
40 select TRACE_IRQFLAGS_SUPPORT
48 config GENERIC_HWEIGHT
54 # For now, use generic checksum functions
55 #These can be reimplemented in assembly later if so inclined
59 config STACKTRACE_SUPPORT
62 config LOCKDEP_SUPPORT
65 menu "Processor type and features"
68 prompt "Subarchitecture"
74 Generic OpenRISC 1200 architecture
78 config DCACHE_WRITETHROUGH
79 bool "Have write through data caches"
82 Select this if your implementation features write through data caches.
83 Selecting 'N' here will allow the kernel to force flushing of data
84 caches at relevant times. Most OpenRISC implementations support write-
89 config OPENRISC_BUILTIN_DTB
93 menu "Class II Instructions"
95 config OPENRISC_HAVE_INST_FF1
96 bool "Have instruction l.ff1"
99 Select this if your implementation has the Class II instruction l.ff1
101 config OPENRISC_HAVE_INST_FL1
102 bool "Have instruction l.fl1"
105 Select this if your implementation has the Class II instruction l.fl1
107 config OPENRISC_HAVE_INST_MUL
108 bool "Have instruction l.mul for hardware multiply"
111 Select this if your implementation has a hardware multiply instruction
113 config OPENRISC_HAVE_INST_DIV
114 bool "Have instruction l.div for hardware divide"
117 Select this if your implementation has a hardware divide instruction
121 int "Maximum number of CPUs (2-32)"
127 bool "Symmetric Multi-Processing support"
129 This enables support for systems with more than one CPU. If you have
130 a system with only one CPU, say N. If you have a system with more
133 If you don't know what to do here, say N.
135 source "kernel/Kconfig.hz"
137 config OPENRISC_NO_SPR_SR_DSX
138 bool "use SPR_SR_DSX software emulation" if OR1K_1200
141 SPR_SR_DSX bit is status register bit indicating whether
142 the last exception has happened in delay slot.
144 OpenRISC architecture makes it optional to have it implemented
145 in hardware and the OR1200 does not have it.
147 Say N here if you know that your OpenRISC processor has
148 SPR_SR_DSX bit implemented. Say Y if you are unsure.
150 config OPENRISC_HAVE_SHADOW_GPRS
151 bool "Support for shadow gpr files" if !SMP
154 Say Y here if your OpenRISC processor features shadowed
155 register files. They will in such case be used as a
156 scratch reg storage on exception entry.
158 On SMP systems, this feature is mandatory.
159 On a unicore system it's safe to say N here if you are unsure.
162 string "Default kernel command string"
165 On some architectures there is currently no way for the boot loader
166 to pass arguments to the kernel. For these architectures, you should
167 supply some command-line options at build time by entering them
170 menu "Debugging options"
172 config JUMP_UPON_UNHANDLED_EXCEPTION
173 bool "Try to die gracefully"
176 Now this puts kernel into infinite loop after first oops. Till
177 your kernel crashes this doesn't have any influence.
179 Say Y if you are unsure.
181 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
182 bool "Check for possible ESR exception bug"
185 This option enables some checks that might expose some problems
188 Say N if you are unsure.