1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.rst.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
14 select OF_EARLY_FLATTREE
17 select HAVE_ARCH_TRACEHOOK
19 select GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
23 select GENERIC_CPU_DEVICES
25 select GENERIC_ATOMIC64
26 select GENERIC_CLOCKEVENTS_BROADCAST
27 select GENERIC_SMP_IDLE_THREAD
28 select MODULES_USE_ELF_RELA
29 select HAVE_DEBUG_STACKOVERFLOW
31 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
32 select ARCH_USE_QUEUED_SPINLOCKS
33 select ARCH_USE_QUEUED_RWLOCKS
35 select ARCH_WANT_FRAME_POINTERS
36 select GENERIC_IRQ_MULTI_HANDLER
37 select MMU_GATHER_NO_RANGE if MMU
39 select TRACE_IRQFLAGS_SUPPORT
47 config GENERIC_HWEIGHT
53 # For now, use generic checksum functions
54 #These can be reimplemented in assembly later if so inclined
58 config STACKTRACE_SUPPORT
61 config LOCKDEP_SUPPORT
64 menu "Processor type and features"
67 prompt "Subarchitecture"
73 Generic OpenRISC 1200 architecture
77 config DCACHE_WRITETHROUGH
78 bool "Have write through data caches"
81 Select this if your implementation features write through data caches.
82 Selecting 'N' here will allow the kernel to force flushing of data
83 caches at relevant times. Most OpenRISC implementations support write-
88 config OPENRISC_BUILTIN_DTB
92 menu "Class II Instructions"
94 config OPENRISC_HAVE_INST_FF1
95 bool "Have instruction l.ff1"
98 Select this if your implementation has the Class II instruction l.ff1
100 config OPENRISC_HAVE_INST_FL1
101 bool "Have instruction l.fl1"
104 Select this if your implementation has the Class II instruction l.fl1
106 config OPENRISC_HAVE_INST_MUL
107 bool "Have instruction l.mul for hardware multiply"
110 Select this if your implementation has a hardware multiply instruction
112 config OPENRISC_HAVE_INST_DIV
113 bool "Have instruction l.div for hardware divide"
116 Select this if your implementation has a hardware divide instruction
120 int "Maximum number of CPUs (2-32)"
126 bool "Symmetric Multi-Processing support"
128 This enables support for systems with more than one CPU. If you have
129 a system with only one CPU, say N. If you have a system with more
132 If you don't know what to do here, say N.
134 source "kernel/Kconfig.hz"
136 config OPENRISC_NO_SPR_SR_DSX
137 bool "use SPR_SR_DSX software emulation" if OR1K_1200
140 SPR_SR_DSX bit is status register bit indicating whether
141 the last exception has happened in delay slot.
143 OpenRISC architecture makes it optional to have it implemented
144 in hardware and the OR1200 does not have it.
146 Say N here if you know that your OpenRISC processor has
147 SPR_SR_DSX bit implemented. Say Y if you are unsure.
149 config OPENRISC_HAVE_SHADOW_GPRS
150 bool "Support for shadow gpr files" if !SMP
153 Say Y here if your OpenRISC processor features shadowed
154 register files. They will in such case be used as a
155 scratch reg storage on exception entry.
157 On SMP systems, this feature is mandatory.
158 On a unicore system it's safe to say N here if you are unsure.
161 string "Default kernel command string"
164 On some architectures there is currently no way for the boot loader
165 to pass arguments to the kernel. For these architectures, you should
166 supply some command-line options at build time by entering them
169 menu "Debugging options"
171 config JUMP_UPON_UNHANDLED_EXCEPTION
172 bool "Try to die gracefully"
175 Now this puts kernel into infinite loop after first oops. Till
176 your kernel crashes this doesn't have any influence.
178 Say Y if you are unsure.
180 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
181 bool "Check for possible ESR exception bug"
184 This option enables some checks that might expose some problems
187 Say N if you are unsure.