1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.rst.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
15 select OF_EARLY_FLATTREE
18 select HAVE_ARCH_TRACEHOOK
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
24 select GENERIC_CPU_DEVICES
26 select GENERIC_ATOMIC64
27 select GENERIC_CLOCKEVENTS_BROADCAST
28 select GENERIC_SMP_IDLE_THREAD
29 select MODULES_USE_ELF_RELA
30 select HAVE_DEBUG_STACKOVERFLOW
32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
33 select ARCH_USE_QUEUED_RWLOCKS
35 select ARCH_WANT_FRAME_POINTERS
36 select GENERIC_IRQ_MULTI_HANDLER
37 select MMU_GATHER_NO_RANGE if MMU
38 select TRACE_IRQFLAGS_SUPPORT
46 config GENERIC_HWEIGHT
52 # For now, use generic checksum functions
53 #These can be reimplemented in assembly later if so inclined
57 config STACKTRACE_SUPPORT
60 config LOCKDEP_SUPPORT
63 menu "Processor type and features"
66 prompt "Subarchitecture"
72 Generic OpenRISC 1200 architecture
76 config DCACHE_WRITETHROUGH
77 bool "Have write through data caches"
80 Select this if your implementation features write through data caches.
81 Selecting 'N' here will allow the kernel to force flushing of data
82 caches at relevant times. Most OpenRISC implementations support write-
87 config OPENRISC_BUILTIN_DTB
91 menu "Class II Instructions"
93 config OPENRISC_HAVE_INST_FF1
94 bool "Have instruction l.ff1"
97 Select this if your implementation has the Class II instruction l.ff1
99 config OPENRISC_HAVE_INST_FL1
100 bool "Have instruction l.fl1"
103 Select this if your implementation has the Class II instruction l.fl1
105 config OPENRISC_HAVE_INST_MUL
106 bool "Have instruction l.mul for hardware multiply"
109 Select this if your implementation has a hardware multiply instruction
111 config OPENRISC_HAVE_INST_DIV
112 bool "Have instruction l.div for hardware divide"
115 Select this if your implementation has a hardware divide instruction
117 config OPENRISC_HAVE_INST_CMOV
118 bool "Have instruction l.cmov for conditional move"
121 This config enables gcc to generate l.cmov instructions when compiling
122 the kernel which in general will improve performance and reduce the
125 Select this if your implementation has support for the Class II
126 l.cmov conistional move instruction.
128 Say N if you are unsure.
130 config OPENRISC_HAVE_INST_ROR
131 bool "Have instruction l.ror for rotate right"
134 This config enables gcc to generate l.ror instructions when compiling
135 the kernel which in general will improve performance and reduce the
138 Select this if your implementation has support for the Class II
139 l.ror rotate right instruction.
141 Say N if you are unsure.
143 config OPENRISC_HAVE_INST_RORI
144 bool "Have instruction l.rori for rotate right with immediate"
147 This config enables gcc to generate l.rori instructions when compiling
148 the kernel which in general will improve performance and reduce the
151 Select this if your implementation has support for the Class II
152 l.rori rotate right with immediate instruction.
154 Say N if you are unsure.
156 config OPENRISC_HAVE_INST_SEXT
157 bool "Have instructions l.ext* for sign extension"
160 This config enables gcc to generate l.ext* instructions when compiling
161 the kernel which in general will improve performance and reduce the
164 Select this if your implementation has support for the Class II
165 l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
167 Say N if you are unsure.
172 int "Maximum number of CPUs (2-32)"
178 bool "Symmetric Multi-Processing support"
180 This enables support for systems with more than one CPU. If you have
181 a system with only one CPU, say N. If you have a system with more
184 If you don't know what to do here, say N.
186 source "kernel/Kconfig.hz"
188 config OPENRISC_NO_SPR_SR_DSX
189 bool "use SPR_SR_DSX software emulation" if OR1K_1200
192 SPR_SR_DSX bit is status register bit indicating whether
193 the last exception has happened in delay slot.
195 OpenRISC architecture makes it optional to have it implemented
196 in hardware and the OR1200 does not have it.
198 Say N here if you know that your OpenRISC processor has
199 SPR_SR_DSX bit implemented. Say Y if you are unsure.
201 config OPENRISC_HAVE_SHADOW_GPRS
202 bool "Support for shadow gpr files" if !SMP
205 Say Y here if your OpenRISC processor features shadowed
206 register files. They will in such case be used as a
207 scratch reg storage on exception entry.
209 On SMP systems, this feature is mandatory.
210 On a unicore system it's safe to say N here if you are unsure.
213 string "Default kernel command string"
216 On some architectures there is currently no way for the boot loader
217 to pass arguments to the kernel. For these architectures, you should
218 supply some command-line options at build time by entering them
221 menu "Debugging options"
223 config JUMP_UPON_UNHANDLED_EXCEPTION
224 bool "Try to die gracefully"
227 Now this puts kernel into infinite loop after first oops. Till
228 your kernel crashes this doesn't have any influence.
230 Say Y if you are unsure.
232 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
233 bool "Check for possible ESR exception bug"
236 This option enables some checks that might expose some problems
239 Say N if you are unsure.