1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2005-2017 Andes Technology Corporation
4 #ifndef _ASM_NDS32_NDS32_H_
5 #define _ASM_NDS32_NDS32_H_
7 #include <asm/bitfield.h>
8 #include <asm/cachectl.h>
11 #include <linux/init.h>
12 #include <asm/barrier.h>
13 #include <nds32_intrinsic.h>
15 #ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
16 #define FP_OFFSET (-3)
18 #define FP_OFFSET (-2)
21 extern void __init early_trap_init(void);
22 static inline void GIE_ENABLE(void)
28 static inline void GIE_DISABLE(void)
34 static inline unsigned long CACHE_SET(unsigned char cache)
38 return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
41 return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
45 static inline unsigned long CACHE_WAY(unsigned char cache)
50 ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
53 ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
56 static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
61 (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
64 (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
67 #endif /* __ASSEMBLY__ */
69 #define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
70 * We defined at the start of the physical memory */
72 /* dispatched sub-entry exception handler numbering */
73 #define RD_PROT 0 /* read protrection */
74 #define WRT_PROT 1 /* write protection */
75 #define NOEXEC 2 /* non executable */
76 #define PAGE_MODIFY 3 /* page modified */
77 #define ACC_BIT 4 /* access bit */
78 #define RESVED_PTE 5 /* reserved PTE attribute */
81 #endif /* _ASM_NDS32_NDS32_H_ */