1 comment "Processor Features"
6 config CPU_LITTLE_ENDIAN
7 def_bool !CPU_BIG_ENDIAN
10 bool "hardware zero overhead loop support"
11 depends on CPU_D10 || CPU_D15
14 A set of Zero-Overhead Loop mechanism is provided to reduce the
15 instruction fetch and execution overhead of loop-control instructions.
16 It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
17 You don't need to save these registers if you can make sure your user
18 program doesn't use these registers.
22 config CPU_CACHE_ALIASING
24 depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
27 If this CPU is using VIPT data cache and its cache way size is larger
28 than page size, say Y. If it is using PIPT data cache, say N.
33 prompt "minimum CPU type"
36 The data cache of N15/D15 is implemented as PIPT and it will not cause
37 the cache aliasing issue. The rest cpus(N13, N10 and D10) are
38 implemented as VIPT data cache. It may cause the cache aliasing issue
39 if its cache way size is larger than page size. You can specify the
40 CPU type direcly or choose CPU_V3 if unsure.
42 A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
43 A kernel built for N15 is able to run on N15 or D15.
44 A kernel built for D10 is able to run on D10 or D15.
45 A kernel built for D15 is able to run on D15.
46 A kernel built for N13 is able to run on N15, N13 or D15.
52 select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
55 select CPU_CACHE_ALIASING
60 select CPU_CACHE_ALIASING
62 bool "AndesCore v3 compatible"
63 select CPU_CACHE_ALIASING
66 prompt "Paging -- page size "
67 default ANDES_PAGE_SIZE_4KB
68 config ANDES_PAGE_SIZE_4KB
69 bool "use 4KB page size"
70 config ANDES_PAGE_SIZE_8KB
71 bool "use 8KB page size"
74 config CPU_ICACHE_DISABLE
75 bool "Disable I-Cache"
77 Say Y here to disable the processor instruction cache. Unless
78 you have a reason not to or are unsure, say N.
80 config CPU_DCACHE_DISABLE
81 bool "Disable D-Cache"
83 Say Y here to disable the processor data cache. Unless
84 you have a reason not to or are unsure, say N.
86 config CPU_DCACHE_WRITETHROUGH
87 bool "Force write through D-cache"
88 depends on !CPU_DCACHE_DISABLE
90 Say Y here to use the data cache in writethrough mode. Unless you
91 specifically require this or are unsure, say N.
97 Say Y here to enable write-back memory with no-write-allocation policy.
100 bool "Kernel support unaligned access handling by sw"
104 Andes processors cannot load/store information which is not
105 naturally aligned on the bus, i.e., a 4 byte load must start at an
106 address divisible by 4. On 32-bit Andes processors, these non-aligned
107 load/store instructions will be emulated in software if you say Y
108 here, which has a severe performance impact. With an IP-only
109 configuration it is safe to say N, otherwise say Y.
111 config HW_SUPPORT_UNALIGNMENT_ACCESS
112 bool "Kernel support unaligned access handling by hw"
113 depends on !ALIGNMENT_TRAP
116 Andes processors load/store world/half-word instructions can access
117 unaligned memory locations without generating the Data Alignment
118 Check exceptions. With an IP-only configuration it is safe to say N,
122 bool "High Memory Support"
123 depends on MMU && !CPU_CACHE_ALIASING
125 The address space of Andes processors is only 4 Gigabytes large
126 and it has to accommodate user address space, kernel address
127 space as well as some memory mapped IO. That means that, if you
128 have a large amount of physical memory and/or IO, not all of the
129 memory can be "permanently mapped" by the kernel. The physical
130 memory that is not permanently mapped is called "high memory".
132 Depending on the selected kernel/user memory split, minimum
133 vmalloc space and actual amount of RAM, you may not need this
134 option which should result in a slightly faster kernel.
139 bool "Support L2 cache"
142 Say Y here to enable L2 cache if your SoC are integrated with L2CC.
145 menu "Memory configuration"
148 prompt "Memory split"
150 default VMSPLIT_3G_OPT
152 Select the desired split between kernel and user memory.
154 If you are not absolutely sure what you are doing, leave this
158 bool "3G/1G user/kernel split"
159 config VMSPLIT_3G_OPT
160 bool "3G/1G user/kernel split (for full 1G low memory)"
162 bool "2G/2G user/kernel split"
164 bool "1G/3G user/kernel split"
169 default 0x40000000 if VMSPLIT_1G
170 default 0x80000000 if VMSPLIT_2G
171 default 0xB0000000 if VMSPLIT_3G_OPT