1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/sys_soc.h>
12 #include <linux/memblock.h>
14 #include <asm/bootinfo.h>
15 #include <asm/mipsregs.h>
16 #include <asm/smp-ops.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7621.h>
25 #define MT7621_GPIO_MODE_UART1 1
26 #define MT7621_GPIO_MODE_I2C 2
27 #define MT7621_GPIO_MODE_UART3_MASK 0x3
28 #define MT7621_GPIO_MODE_UART3_SHIFT 3
29 #define MT7621_GPIO_MODE_UART3_GPIO 1
30 #define MT7621_GPIO_MODE_UART2_MASK 0x3
31 #define MT7621_GPIO_MODE_UART2_SHIFT 5
32 #define MT7621_GPIO_MODE_UART2_GPIO 1
33 #define MT7621_GPIO_MODE_JTAG 7
34 #define MT7621_GPIO_MODE_WDT_MASK 0x3
35 #define MT7621_GPIO_MODE_WDT_SHIFT 8
36 #define MT7621_GPIO_MODE_WDT_GPIO 1
37 #define MT7621_GPIO_MODE_PCIE_RST 0
38 #define MT7621_GPIO_MODE_PCIE_REF 2
39 #define MT7621_GPIO_MODE_PCIE_MASK 0x3
40 #define MT7621_GPIO_MODE_PCIE_SHIFT 10
41 #define MT7621_GPIO_MODE_PCIE_GPIO 1
42 #define MT7621_GPIO_MODE_MDIO_MASK 0x3
43 #define MT7621_GPIO_MODE_MDIO_SHIFT 12
44 #define MT7621_GPIO_MODE_MDIO_GPIO 1
45 #define MT7621_GPIO_MODE_RGMII1 14
46 #define MT7621_GPIO_MODE_RGMII2 15
47 #define MT7621_GPIO_MODE_SPI_MASK 0x3
48 #define MT7621_GPIO_MODE_SPI_SHIFT 16
49 #define MT7621_GPIO_MODE_SPI_GPIO 1
50 #define MT7621_GPIO_MODE_SDHCI_MASK 0x3
51 #define MT7621_GPIO_MODE_SDHCI_SHIFT 18
52 #define MT7621_GPIO_MODE_SDHCI_GPIO 1
54 static void *detect_magic __initdata = detect_memory_region;
56 static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
57 static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
58 static struct rt2880_pmx_func uart3_grp[] = {
59 FUNC("uart3", 0, 5, 4),
61 FUNC("spdif3", 3, 5, 4),
63 static struct rt2880_pmx_func uart2_grp[] = {
64 FUNC("uart2", 0, 9, 4),
66 FUNC("spdif2", 3, 9, 4),
68 static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
69 static struct rt2880_pmx_func wdt_grp[] = {
70 FUNC("wdt rst", 0, 18, 1),
71 FUNC("wdt refclk", 2, 18, 1),
73 static struct rt2880_pmx_func pcie_rst_grp[] = {
74 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
75 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
77 static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
78 static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
79 static struct rt2880_pmx_func spi_grp[] = {
80 FUNC("spi", 0, 34, 7),
81 FUNC("nand1", 2, 34, 7),
83 static struct rt2880_pmx_func sdhci_grp[] = {
84 FUNC("sdhci", 0, 41, 8),
85 FUNC("nand2", 2, 41, 8),
87 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
89 static struct rt2880_pmx_group mt7621_pinmux_data[] = {
90 GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
91 GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
92 GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
93 MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
94 GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
95 MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
96 GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
97 GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
98 MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
99 GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
100 MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
101 GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
102 MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
103 GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
104 GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
105 MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
106 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
107 MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
108 GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
112 phys_addr_t mips_cpc_default_phys_base(void)
114 panic("Cannot detect cpc address");
117 static void __init mt7621_memory_detect(void)
119 void *dm = &detect_magic;
122 for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
123 if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))
127 if ((size == 256 * SZ_1M) &&
128 (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
129 __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {
130 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
131 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
133 memblock_add(MT7621_LOWMEM_BASE, size);
137 void __init ralink_of_remap(void)
139 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
140 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
142 if (!rt_sysc_membase || !rt_memc_membase)
143 panic("Failed to remap core resources");
146 static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
148 struct soc_device *soc_dev;
149 struct soc_device_attribute *soc_dev_attr;
151 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
155 soc_dev_attr->soc_id = "mt7621";
156 soc_dev_attr->family = "Ralink";
158 if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
159 (rev & CHIP_REV_ECO_MASK) == 1)
160 soc_dev_attr->revision = "E2";
162 soc_dev_attr->revision = "E1";
164 soc_dev_attr->data = soc_info;
166 soc_dev = soc_device_register(soc_dev_attr);
167 if (IS_ERR(soc_dev)) {
173 void __init prom_soc_init(struct ralink_soc_info *soc_info)
175 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
176 unsigned char *name = NULL;
181 /* Early detection of CMP support */
185 if (mips_cps_numiocu(0)) {
187 * mips_cm_probe() wipes out bootloader
188 * config for CM regions and we have to configure them
189 * again. This SoC cannot talk to pamlbus devices
190 * witout proper iocu region set up.
192 * FIXME: it would be better to do this with values
193 * from DT, but we need this very early because
194 * without this we cannot talk to pretty much anything
197 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
198 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
199 CM_GCR_REGn_MASK_CMTGT_IOCU0);
203 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
204 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
206 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
208 soc_info->compatible = "mediatek,mt7621-soc";
210 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
212 ralink_soc = MT762X_SOC_MT7621AT;
213 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
215 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
216 "MediaTek %s ver:%u eco:%u",
218 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
219 (rev & CHIP_REV_ECO_MASK));
221 soc_info->mem_detect = mt7621_memory_detect;
222 rt2880_pinmux_data = mt7621_pinmux_data;
224 soc_dev_init(soc_info, rev);
226 if (!register_cps_smp_ops())
228 if (!register_cmp_smp_ops())
230 if (!register_vsmp_smp_ops())