2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/kernel.h>
11 #include <linux/export.h>
12 #include <linux/pci.h>
13 #include <linux/smp.h>
14 #include <linux/dma-direct.h>
15 #include <asm/sn/arch.h>
16 #include <asm/pci/bridge.h>
17 #include <asm/paccess.h>
18 #include <asm/sn/intr.h>
19 #include <asm/sn/sn0/hub.h>
22 * Max #PCI busses we can handle; ie, max #PCI bridges.
24 #define MAX_PCI_BUSSES 40
27 * XXX: No kmalloc available when we do our crosstalk scan,
28 * we should try to move it later in the boot process.
30 static struct bridge_controller bridges[MAX_PCI_BUSSES];
32 extern struct pci_ops bridge_pci_ops;
34 int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
36 unsigned long offset = NODE_OFFSET(nasid);
37 struct bridge_controller *bc;
38 static int num_bridges = 0;
41 pci_set_flags(PCI_PROBE_ONLY);
45 /* XXX: kludge alert.. */
47 ioport_resource.end = ~0UL;
49 bc = &bridges[num_bridges];
51 bc->pc.pci_ops = &bridge_pci_ops;
52 bc->pc.mem_resource = &bc->mem;
53 bc->pc.io_resource = &bc->io;
55 bc->pc.index = num_bridges;
57 bc->mem.name = "Bridge PCI MEM";
58 bc->pc.mem_offset = offset;
61 bc->mem.flags = IORESOURCE_MEM;
63 bc->io.name = "Bridge IO MEM";
64 bc->pc.io_offset = offset;
67 bc->io.flags = IORESOURCE_IO;
69 bc->widget_id = widget_id;
72 bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
75 * point to this bridge
77 bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id);
80 * Clear all pending interrupts.
82 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
85 * Until otherwise set up, assume all interrupts are from slot 0
87 bridge_write(bc, b_int_device, 0x0);
90 * swap pio's to pci mem and io space (big windows)
92 bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP |
93 BRIDGE_CTRL_MEM_SWAP);
94 #ifdef CONFIG_PAGE_SIZE_4KB
95 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
96 #else /* 16kB or larger */
97 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
101 * Hmm... IRIX sets additional bits in the address which
102 * are documented as reserved in the bridge docs.
104 bridge_write(bc, b_wid_int_upper, 0x8000 | (masterwid << 16));
105 bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/
106 bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */
107 bridge_write(bc, b_int_enable, 0);
109 for (slot = 0; slot < 8; slot ++) {
110 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
111 bc->pci_int[slot] = -1;
113 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
115 register_pci_controller(&bc->pc);
123 * All observed requests have pin == 1. We could have a global here, that
124 * gets incremented and returned every time - unfortunately, pci_map_irq
125 * may be called on the same device over and over, and need to return the
126 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
128 * A given PCI device, in general, should be able to intr any of the cpus
129 * on any one of the hubs connected to its xbow.
131 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
136 static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
138 while (dev->bus->parent) {
139 /* Move up the chain of bridges. */
140 dev = dev->bus->self;
146 /* Do platform specific device initialization at pci_enable_device() time */
147 int pcibios_plat_dev_init(struct pci_dev *dev)
149 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
150 struct pci_dev *rdev = bridge_root_dev(dev);
151 int slot = PCI_SLOT(rdev->devfn);
154 irq = bc->pci_int[slot];
156 irq = request_bridge_irq(bc, slot);
160 bc->pci_int[slot] = irq;
167 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
169 struct pci_dev *pdev = to_pci_dev(dev);
170 struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
172 return bc->baddr + paddr;
175 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
177 return dma_addr & ~(0xffUL << 56);
181 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
182 * to find the slot number in sense of the bridge device register.
183 * XXX This also means multiple devices might rely on conflicting bridge
187 static inline void pci_disable_swapping(struct pci_dev *dev)
189 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
190 struct bridge_regs *bridge = bc->base;
191 int slot = PCI_SLOT(dev->devfn);
193 /* Turn off byte swapping */
194 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
195 bridge->b_widget.w_tflush; /* Flush */
198 static void pci_fixup_ioc3(struct pci_dev *d)
200 pci_disable_swapping(d);
204 int pcibus_to_node(struct pci_bus *bus)
206 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
210 EXPORT_SYMBOL(pcibus_to_node);
211 #endif /* CONFIG_NUMA */
213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,