2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/kernel.h>
22 #include <asm/gt64120.h>
24 #define PCI_ACCESS_READ 0
25 #define PCI_ACCESS_WRITE 1
28 * PCI configuration cycle AD bus definition
31 #define PCI_CFG_TYPE0_REG_SHF 0
32 #define PCI_CFG_TYPE0_FUNC_SHF 8
35 #define PCI_CFG_TYPE1_REG_SHF 0
36 #define PCI_CFG_TYPE1_FUNC_SHF 8
37 #define PCI_CFG_TYPE1_DEV_SHF 11
38 #define PCI_CFG_TYPE1_BUS_SHF 16
40 static int gt64120_pcibios_config_access(unsigned char access_type,
41 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
43 unsigned char busnum = bus->number;
46 if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
47 /* Galileo itself is devfn 0, don't move it around */
50 if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
51 return -1; /* Because of a bug in the galileo (for slot 31). */
53 /* Clear cause register bits */
54 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
55 GT_INTRCAUSE_TARABORT0_BIT));
58 GT_WRITE(GT_PCI0_CFGADDR_OFS,
59 (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
60 (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
61 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
62 GT_PCI0_CFGADDR_CONFIGEN_BIT);
64 if (access_type == PCI_ACCESS_WRITE) {
65 if (busnum == 0 && PCI_SLOT(devfn) == 0) {
67 * The Galileo system controller is acting
68 * differently than other devices.
70 GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
72 __GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
74 if (busnum == 0 && PCI_SLOT(devfn) == 0) {
76 * The Galileo system controller is acting
77 * differently than other devices.
79 *data = GT_READ(GT_PCI0_CFGDATA_OFS);
81 *data = __GT_READ(GT_PCI0_CFGDATA_OFS);
84 /* Check for master or target abort */
85 intr = GT_READ(GT_INTRCAUSE_OFS);
87 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
91 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
92 GT_INTRCAUSE_TARABORT0_BIT));
102 * We can't address 8 and 16 bit words directly. Instead we have to
103 * read/write a 32bit word and mask/modify the data we actually want.
105 static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
106 int where, int size, u32 * val)
110 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
112 return PCIBIOS_DEVICE_NOT_FOUND;
115 *val = (data >> ((where & 3) << 3)) & 0xff;
117 *val = (data >> ((where & 3) << 3)) & 0xffff;
121 return PCIBIOS_SUCCESSFUL;
124 static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
125 int where, int size, u32 val)
132 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
134 return PCIBIOS_DEVICE_NOT_FOUND;
137 data = (data & ~(0xff << ((where & 3) << 3))) |
138 (val << ((where & 3) << 3));
140 data = (data & ~(0xffff << ((where & 3) << 3))) |
141 (val << ((where & 3) << 3));
144 if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
146 return PCIBIOS_DEVICE_NOT_FOUND;
148 return PCIBIOS_SUCCESSFUL;
151 struct pci_ops gt64120_pci_ops = {
152 .read = gt64120_pcibios_read,
153 .write = gt64120_pcibios_write