2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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35 #include <linux/types.h>
36 #include <linux/kernel.h>
38 #include <linux/delay.h>
40 #include <asm/mipsregs.h>
43 #include <asm/netlogic/common.h>
44 #include <asm/netlogic/haldefs.h>
45 #include <asm/netlogic/xlp-hal/iomap.h>
46 #include <asm/netlogic/xlp-hal/xlp.h>
47 #include <asm/netlogic/xlp-hal/bridge.h>
48 #include <asm/netlogic/xlp-hal/pic.h>
49 #include <asm/netlogic/xlp-hal/sys.h>
51 /* Main initialization */
52 void nlm_node_init(int node)
54 struct nlm_soc_info *nodep;
56 nodep = nlm_get_node(node);
57 nodep->sysbase = nlm_get_sys_regbase(node);
58 nodep->picbase = nlm_get_pic_regbase(node);
59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
60 spin_lock_init(&nodep->piclock);
63 int nlm_irq_to_irt(int irq)
71 devoff = XLP_IO_UART0_OFFSET(0);
74 devoff = XLP_IO_UART1_OFFSET(0);
77 devoff = XLP_IO_SD_OFFSET(0);
79 case PIC_I2C_0_IRQ: /* I2C will be fixed up */
84 devoff = XLP2XX_IO_I2C_OFFSET(0);
86 devoff = XLP_IO_I2C0_OFFSET(0);
91 /* XLP2XX has three XHCI USB controller */
92 case PIC_2XX_XHCI_0_IRQ:
93 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
95 case PIC_2XX_XHCI_1_IRQ:
96 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
98 case PIC_2XX_XHCI_2_IRQ:
99 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
105 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
108 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
111 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
114 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
117 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
120 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
127 pcibase = nlm_pcicfg_base(devoff);
128 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
129 /* HW weirdness, I2C IRT entry has to be fixed up */
132 irt = irt + 1; break;
134 irt = irt + 2; break;
136 irt = irt + 3; break;
138 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
139 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
140 /* HW bug, PCI IRT entries are bad on early silicon, fix */
141 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
142 PIC_PCIE_LINK_LEGACY_IRQ_BASE);
143 } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
144 irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
146 } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
147 irq <= PIC_PCIE_MSIX_IRQ(3)) {
155 unsigned int nlm_get_core_frequency(int node, int core)
157 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
158 unsigned int rstval, dfsval, denom;
159 uint64_t num, sysbase;
161 sysbase = nlm_get_node(node)->sysbase;
162 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
163 if (cpu_is_xlpii()) {
164 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
167 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
168 pll_divf = ((rstval >> 10) & 0x7f) + 1;
169 pll_divr = ((rstval >> 8) & 0x3) + 1;
170 ext_div = ((rstval >> 30) & 0x3) + 1;
171 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
173 num = 800000000ULL * pll_divf;
174 denom = 3 * pll_divr * ext_div * dfs_div;
177 return (unsigned int)num;
180 /* Calculate Frequency to the PIC from PLL.
181 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
182 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
184 static unsigned int nlm_2xx_get_pic_frequency(int node)
186 u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
187 u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
188 u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
190 sysbase = nlm_get_node(node)->sysbase;
192 /* Find ref_clk_base */
194 (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
195 switch (ref_clk_select) {
197 ref_clk = 200000000ULL;
201 ref_clk = 100000000ULL;
205 ref_clk = 125000000ULL;
209 ref_clk = 400000000ULL;
214 /* Find the clock source PLL device for PIC */
215 reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
216 switch (reg_select) {
218 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
219 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
222 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
223 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
226 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
227 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
230 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
231 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
235 vco_post_div = (ctrl_val0 >> 5) & 0x7;
236 pll_post_div = (ctrl_val0 >> 24) & 0x7;
237 mdiv = ctrl_val2 & 0xff;
238 fdiv = (ctrl_val2 >> 8) & 0xfff;
240 /* Find PLL post divider value */
241 switch (pll_post_div) {
260 fdiv = fdiv/(1 << 13);
261 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
262 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
264 if (pll_out_freq_den > 0)
265 do_div(pll_out_freq_num, pll_out_freq_den);
267 /* PIC post divider, which happens after PLL */
268 pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
269 do_div(pll_out_freq_num, 1 << pic_div);
271 return pll_out_freq_num;
274 unsigned int nlm_get_pic_frequency(int node)
277 return nlm_2xx_get_pic_frequency(node);
282 unsigned int nlm_get_cpu_frequency(void)
284 return nlm_get_core_frequency(0, 0);
288 * Fills upto 8 pairs of entries containing the DRAM map of a node
289 * if n < 0, get dram map for all nodes
291 int xlp_get_dram_map(int n, uint64_t *dram_map)
293 uint64_t bridgebase, base, lim;
297 /* Look only at mapping on Node 0, we don't handle crazy configs */
298 bridgebase = nlm_get_bridge_regbase(0);
300 for (i = 0; i < 8; i++) {
301 val = nlm_read_bridge_reg(bridgebase,
302 BRIDGE_DRAM_NODE_TRANSLN(i));
303 node = (val >> 1) & 0x3;
304 if (n >= 0 && n != node)
306 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
307 val = (val >> 12) & 0xfffff;
308 base = (uint64_t) val << 20;
309 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
310 val = (val >> 12) & 0xfffff;
311 if (val == 0) /* BAR not used */
313 lim = ((uint64_t)val + 1) << 20;
315 dram_map[rv + 1] = lim;