2 * Just-In-Time compiler for eBPF filters on MIPS
4 * Copyright (c) 2017 Cavium, Inc.
8 * Copyright (c) 2014 Imagination Technologies Ltd.
9 * Author: Markos Chandras <markos.chandras@imgtec.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; version 2 of the License.
16 #include <linux/bitops.h>
17 #include <linux/errno.h>
18 #include <linux/filter.h>
19 #include <linux/bpf.h>
20 #include <linux/slab.h>
21 #include <asm/bitops.h>
22 #include <asm/byteorder.h>
23 #include <asm/cacheflush.h>
24 #include <asm/cpu-features.h>
25 #include <asm/isa-rev.h>
28 /* Registers used by JIT */
31 #define MIPS_R_V0 2 /* BPF_R0 */
33 #define MIPS_R_A0 4 /* BPF_R1 */
34 #define MIPS_R_A1 5 /* BPF_R2 */
35 #define MIPS_R_A2 6 /* BPF_R3 */
36 #define MIPS_R_A3 7 /* BPF_R4 */
37 #define MIPS_R_A4 8 /* BPF_R5 */
38 #define MIPS_R_T4 12 /* BPF_AX */
42 #define MIPS_R_S0 16 /* BPF_R6 */
43 #define MIPS_R_S1 17 /* BPF_R7 */
44 #define MIPS_R_S2 18 /* BPF_R8 */
45 #define MIPS_R_S3 19 /* BPF_R9 */
46 #define MIPS_R_S4 20 /* BPF_TCC */
56 #define EBPF_SAVE_S0 BIT(0)
57 #define EBPF_SAVE_S1 BIT(1)
58 #define EBPF_SAVE_S2 BIT(2)
59 #define EBPF_SAVE_S3 BIT(3)
60 #define EBPF_SAVE_S4 BIT(4)
61 #define EBPF_SAVE_RA BIT(5)
62 #define EBPF_SEEN_FP BIT(6)
63 #define EBPF_SEEN_TC BIT(7)
64 #define EBPF_TCC_IN_V1 BIT(8)
67 * For the mips64 ISA, we need to track the value range or type for
68 * each JIT register. The BPF machine requires zero extended 32-bit
69 * values, but the mips64 ISA requires sign extended 32-bit values.
70 * At each point in the BPF program we track the state of every
71 * register so that we can zero extend or sign extend as the BPF
77 /* not known to be 32-bit compatible. */
79 /* 32-bit compatible, no truncation needed for 64-bit ops. */
81 /* 32-bit compatible, need truncation for 64-bit ops. */
83 /* 32-bit no sign/zero extension needed. */
88 * high bit of offsets indicates if long branch conversion done at
91 #define OFFSETS_B_CONV BIT(31)
94 * struct jit_ctx - JIT context
96 * @stack_size: eBPF stack size
97 * @idx: Instruction index
99 * @offsets: Instruction offsets
100 * @target: Memory location for the compiled filter
101 * @reg_val_types Packed enum reg_val_type for each register.
104 const struct bpf_prog *skf;
111 unsigned int long_b_conversion:1;
112 unsigned int gen_b_offsets:1;
113 unsigned int use_bbit_insns:1;
116 static void set_reg_val_type(u64 *rvt, int reg, enum reg_val_type type)
118 *rvt &= ~(7ull << (reg * 3));
119 *rvt |= ((u64)type << (reg * 3));
122 static enum reg_val_type get_reg_val_type(const struct jit_ctx *ctx,
125 return (ctx->reg_val_types[index] >> (reg * 3)) & 7;
128 /* Simply emit the instruction if the JIT memory space has been allocated */
129 #define emit_instr_long(ctx, func64, func32, ...) \
131 if ((ctx)->target != NULL) { \
132 u32 *p = &(ctx)->target[ctx->idx]; \
133 if (IS_ENABLED(CONFIG_64BIT)) \
134 uasm_i_##func64(&p, ##__VA_ARGS__); \
136 uasm_i_##func32(&p, ##__VA_ARGS__); \
141 #define emit_instr(ctx, func, ...) \
142 emit_instr_long(ctx, func, func, ##__VA_ARGS__)
144 static unsigned int j_target(struct jit_ctx *ctx, int target_idx)
146 unsigned long target_va, base_va;
152 base_va = (unsigned long)ctx->target;
153 target_va = base_va + (ctx->offsets[target_idx] & ~OFFSETS_B_CONV);
155 if ((base_va & ~0x0ffffffful) != (target_va & ~0x0ffffffful))
156 return (unsigned int)-1;
157 r = target_va & 0x0ffffffful;
161 /* Compute the immediate value for PC-relative branches. */
162 static u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
164 if (!ctx->gen_b_offsets)
168 * We want a pc-relative branch. tgt is the instruction offset
169 * we want to jump to.
172 * I: target_offset <- sign_extend(offset)
173 * I+1: PC += target_offset (delay slot)
175 * ctx->idx currently points to the branch instruction
176 * but the offset is added to the delay slot so we need
179 return (ctx->offsets[tgt] & ~OFFSETS_B_CONV) -
183 enum which_ebpf_reg {
191 * For eBPF, the register mapping naturally falls out of the
192 * requirements of eBPF and the MIPS n64 ABI. We don't maintain a
193 * separate frame pointer, so BPF_REG_10 relative accesses are
194 * adjusted to be $sp relative.
196 static int ebpf_to_mips_reg(struct jit_ctx *ctx,
197 const struct bpf_insn *insn,
198 enum which_ebpf_reg w)
200 int ebpf_reg = (w == src_reg || w == src_reg_no_fp) ?
201 insn->src_reg : insn->dst_reg;
217 ctx->flags |= EBPF_SAVE_S0;
220 ctx->flags |= EBPF_SAVE_S1;
223 ctx->flags |= EBPF_SAVE_S2;
226 ctx->flags |= EBPF_SAVE_S3;
229 if (w == dst_reg || w == src_reg_no_fp)
231 ctx->flags |= EBPF_SEEN_FP;
233 * Needs special handling, return something that
234 * cannot be clobbered just in case.
241 WARN(1, "Illegal bpf reg: %d\n", ebpf_reg);
246 * eBPF stack frame will be something like:
248 * Entry $sp ------> +--------------------------------+
250 * +--------------------------------+
252 * +--------------------------------+
254 * +--------------------------------+
256 * +--------------------------------+
258 * +--------------------------------+
260 * +--------------------------------+
261 * | tmp-storage (if $ra saved) |
262 * $sp + tmp_offset --> +--------------------------------+ <--BPF_REG_10
263 * | BPF_REG_10 relative storage |
264 * | MAX_BPF_STACK (optional) |
268 * $sp --------> +--------------------------------+
270 * If BPF_REG_10 is never referenced, then the MAX_BPF_STACK sized
271 * area is not allocated.
273 static int gen_int_prologue(struct jit_ctx *ctx)
275 int stack_adjust = 0;
279 if (ctx->flags & EBPF_SAVE_RA)
281 * If RA we are doing a function call and may need
282 * extra 8-byte tmp area.
284 stack_adjust += 2 * sizeof(long);
285 if (ctx->flags & EBPF_SAVE_S0)
286 stack_adjust += sizeof(long);
287 if (ctx->flags & EBPF_SAVE_S1)
288 stack_adjust += sizeof(long);
289 if (ctx->flags & EBPF_SAVE_S2)
290 stack_adjust += sizeof(long);
291 if (ctx->flags & EBPF_SAVE_S3)
292 stack_adjust += sizeof(long);
293 if (ctx->flags & EBPF_SAVE_S4)
294 stack_adjust += sizeof(long);
296 BUILD_BUG_ON(MAX_BPF_STACK & 7);
297 locals_size = (ctx->flags & EBPF_SEEN_FP) ? MAX_BPF_STACK : 0;
299 stack_adjust += locals_size;
301 ctx->stack_size = stack_adjust;
304 * First instruction initializes the tail call count (TCC).
305 * On tail call we skip this instruction, and the TCC is
306 * passed in $v1 from the caller.
308 emit_instr(ctx, addiu, MIPS_R_V1, MIPS_R_ZERO, MAX_TAIL_CALL_CNT);
310 emit_instr_long(ctx, daddiu, addiu,
311 MIPS_R_SP, MIPS_R_SP, -stack_adjust);
315 store_offset = stack_adjust - sizeof(long);
317 if (ctx->flags & EBPF_SAVE_RA) {
318 emit_instr_long(ctx, sd, sw,
319 MIPS_R_RA, store_offset, MIPS_R_SP);
320 store_offset -= sizeof(long);
322 if (ctx->flags & EBPF_SAVE_S0) {
323 emit_instr_long(ctx, sd, sw,
324 MIPS_R_S0, store_offset, MIPS_R_SP);
325 store_offset -= sizeof(long);
327 if (ctx->flags & EBPF_SAVE_S1) {
328 emit_instr_long(ctx, sd, sw,
329 MIPS_R_S1, store_offset, MIPS_R_SP);
330 store_offset -= sizeof(long);
332 if (ctx->flags & EBPF_SAVE_S2) {
333 emit_instr_long(ctx, sd, sw,
334 MIPS_R_S2, store_offset, MIPS_R_SP);
335 store_offset -= sizeof(long);
337 if (ctx->flags & EBPF_SAVE_S3) {
338 emit_instr_long(ctx, sd, sw,
339 MIPS_R_S3, store_offset, MIPS_R_SP);
340 store_offset -= sizeof(long);
342 if (ctx->flags & EBPF_SAVE_S4) {
343 emit_instr_long(ctx, sd, sw,
344 MIPS_R_S4, store_offset, MIPS_R_SP);
345 store_offset -= sizeof(long);
348 if ((ctx->flags & EBPF_SEEN_TC) && !(ctx->flags & EBPF_TCC_IN_V1))
349 emit_instr_long(ctx, daddu, addu,
350 MIPS_R_S4, MIPS_R_V1, MIPS_R_ZERO);
355 static int build_int_epilogue(struct jit_ctx *ctx, int dest_reg)
357 const struct bpf_prog *prog = ctx->skf;
358 int stack_adjust = ctx->stack_size;
359 int store_offset = stack_adjust - sizeof(long);
360 enum reg_val_type td;
363 if (dest_reg == MIPS_R_RA) {
364 /* Don't let zero extended value escape. */
365 td = get_reg_val_type(ctx, prog->len, BPF_REG_0);
367 emit_instr(ctx, sll, r0, r0, 0);
370 if (ctx->flags & EBPF_SAVE_RA) {
371 emit_instr_long(ctx, ld, lw,
372 MIPS_R_RA, store_offset, MIPS_R_SP);
373 store_offset -= sizeof(long);
375 if (ctx->flags & EBPF_SAVE_S0) {
376 emit_instr_long(ctx, ld, lw,
377 MIPS_R_S0, store_offset, MIPS_R_SP);
378 store_offset -= sizeof(long);
380 if (ctx->flags & EBPF_SAVE_S1) {
381 emit_instr_long(ctx, ld, lw,
382 MIPS_R_S1, store_offset, MIPS_R_SP);
383 store_offset -= sizeof(long);
385 if (ctx->flags & EBPF_SAVE_S2) {
386 emit_instr_long(ctx, ld, lw,
387 MIPS_R_S2, store_offset, MIPS_R_SP);
388 store_offset -= sizeof(long);
390 if (ctx->flags & EBPF_SAVE_S3) {
391 emit_instr_long(ctx, ld, lw,
392 MIPS_R_S3, store_offset, MIPS_R_SP);
393 store_offset -= sizeof(long);
395 if (ctx->flags & EBPF_SAVE_S4) {
396 emit_instr_long(ctx, ld, lw,
397 MIPS_R_S4, store_offset, MIPS_R_SP);
398 store_offset -= sizeof(long);
400 emit_instr(ctx, jr, dest_reg);
403 emit_instr_long(ctx, daddiu, addiu,
404 MIPS_R_SP, MIPS_R_SP, stack_adjust);
406 emit_instr(ctx, nop);
411 static void gen_imm_to_reg(const struct bpf_insn *insn, int reg,
414 if (insn->imm >= S16_MIN && insn->imm <= S16_MAX) {
415 emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm);
417 int lower = (s16)(insn->imm & 0xffff);
418 int upper = insn->imm - lower;
420 emit_instr(ctx, lui, reg, upper >> 16);
421 emit_instr(ctx, addiu, reg, reg, lower);
425 static int gen_imm_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
428 int upper_bound, lower_bound;
429 int dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
434 switch (BPF_OP(insn->code)) {
437 upper_bound = S16_MAX;
438 lower_bound = S16_MIN;
441 upper_bound = -(int)S16_MIN;
442 lower_bound = -(int)S16_MAX;
447 upper_bound = 0xffff;
453 /* Shift amounts are truncated, no need for bounds */
454 upper_bound = S32_MAX;
455 lower_bound = S32_MIN;
462 * Immediate move clobbers the register, so no sign/zero
465 if (BPF_CLASS(insn->code) == BPF_ALU64 &&
466 BPF_OP(insn->code) != BPF_MOV &&
467 get_reg_val_type(ctx, idx, insn->dst_reg) == REG_32BIT)
468 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
469 /* BPF_ALU | BPF_LSH doesn't need separate sign extension */
470 if (BPF_CLASS(insn->code) == BPF_ALU &&
471 BPF_OP(insn->code) != BPF_LSH &&
472 BPF_OP(insn->code) != BPF_MOV &&
473 get_reg_val_type(ctx, idx, insn->dst_reg) != REG_32BIT)
474 emit_instr(ctx, sll, dst, dst, 0);
476 if (insn->imm >= lower_bound && insn->imm <= upper_bound) {
477 /* single insn immediate case */
478 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) {
479 case BPF_ALU64 | BPF_MOV:
480 emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, insn->imm);
482 case BPF_ALU64 | BPF_AND:
483 case BPF_ALU | BPF_AND:
484 emit_instr(ctx, andi, dst, dst, insn->imm);
486 case BPF_ALU64 | BPF_OR:
487 case BPF_ALU | BPF_OR:
488 emit_instr(ctx, ori, dst, dst, insn->imm);
490 case BPF_ALU64 | BPF_XOR:
491 case BPF_ALU | BPF_XOR:
492 emit_instr(ctx, xori, dst, dst, insn->imm);
494 case BPF_ALU64 | BPF_ADD:
495 emit_instr(ctx, daddiu, dst, dst, insn->imm);
497 case BPF_ALU64 | BPF_SUB:
498 emit_instr(ctx, daddiu, dst, dst, -insn->imm);
500 case BPF_ALU64 | BPF_RSH:
501 emit_instr(ctx, dsrl_safe, dst, dst, insn->imm & 0x3f);
503 case BPF_ALU | BPF_RSH:
504 emit_instr(ctx, srl, dst, dst, insn->imm & 0x1f);
506 case BPF_ALU64 | BPF_LSH:
507 emit_instr(ctx, dsll_safe, dst, dst, insn->imm & 0x3f);
509 case BPF_ALU | BPF_LSH:
510 emit_instr(ctx, sll, dst, dst, insn->imm & 0x1f);
512 case BPF_ALU64 | BPF_ARSH:
513 emit_instr(ctx, dsra_safe, dst, dst, insn->imm & 0x3f);
515 case BPF_ALU | BPF_ARSH:
516 emit_instr(ctx, sra, dst, dst, insn->imm & 0x1f);
518 case BPF_ALU | BPF_MOV:
519 emit_instr(ctx, addiu, dst, MIPS_R_ZERO, insn->imm);
521 case BPF_ALU | BPF_ADD:
522 emit_instr(ctx, addiu, dst, dst, insn->imm);
524 case BPF_ALU | BPF_SUB:
525 emit_instr(ctx, addiu, dst, dst, -insn->imm);
531 /* multi insn immediate case */
532 if (BPF_OP(insn->code) == BPF_MOV) {
533 gen_imm_to_reg(insn, dst, ctx);
535 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
536 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) {
537 case BPF_ALU64 | BPF_AND:
538 case BPF_ALU | BPF_AND:
539 emit_instr(ctx, and, dst, dst, MIPS_R_AT);
541 case BPF_ALU64 | BPF_OR:
542 case BPF_ALU | BPF_OR:
543 emit_instr(ctx, or, dst, dst, MIPS_R_AT);
545 case BPF_ALU64 | BPF_XOR:
546 case BPF_ALU | BPF_XOR:
547 emit_instr(ctx, xor, dst, dst, MIPS_R_AT);
549 case BPF_ALU64 | BPF_ADD:
550 emit_instr(ctx, daddu, dst, dst, MIPS_R_AT);
552 case BPF_ALU64 | BPF_SUB:
553 emit_instr(ctx, dsubu, dst, dst, MIPS_R_AT);
555 case BPF_ALU | BPF_ADD:
556 emit_instr(ctx, addu, dst, dst, MIPS_R_AT);
558 case BPF_ALU | BPF_SUB:
559 emit_instr(ctx, subu, dst, dst, MIPS_R_AT);
570 static void emit_const_to_reg(struct jit_ctx *ctx, int dst, u64 value)
572 if (value >= 0xffffffffffff8000ull || value < 0x8000ull) {
573 emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, (int)value);
574 } else if (value >= 0xffffffff80000000ull ||
575 (value < 0x80000000 && value > 0xffff)) {
576 emit_instr(ctx, lui, dst, (s32)(s16)(value >> 16));
577 emit_instr(ctx, ori, dst, dst, (unsigned int)(value & 0xffff));
580 bool seen_part = false;
581 int needed_shift = 0;
583 for (i = 0; i < 4; i++) {
584 u64 part = (value >> (16 * (3 - i))) & 0xffff;
586 if (seen_part && needed_shift > 0 && (part || i == 3)) {
587 emit_instr(ctx, dsll_safe, dst, dst, needed_shift);
591 if (i == 0 || (!seen_part && i < 3 && part < 0x8000)) {
592 emit_instr(ctx, lui, dst, (s32)(s16)part);
595 emit_instr(ctx, ori, dst,
596 seen_part ? dst : MIPS_R_ZERO,
607 static int emit_bpf_tail_call(struct jit_ctx *ctx, int this_idx)
611 ctx->flags |= EBPF_SEEN_TC;
613 * if (index >= array->map.max_entries)
616 off = offsetof(struct bpf_array, map.max_entries);
617 emit_instr(ctx, lwu, MIPS_R_T5, off, MIPS_R_A1);
618 emit_instr(ctx, sltu, MIPS_R_AT, MIPS_R_T5, MIPS_R_A2);
619 b_off = b_imm(this_idx + 1, ctx);
620 emit_instr(ctx, bne, MIPS_R_AT, MIPS_R_ZERO, b_off);
626 emit_instr(ctx, daddiu, MIPS_R_T5,
627 (ctx->flags & EBPF_TCC_IN_V1) ? MIPS_R_V1 : MIPS_R_S4, -1);
628 b_off = b_imm(this_idx + 1, ctx);
629 emit_instr(ctx, bltz, MIPS_R_T5, b_off);
631 * prog = array->ptrs[index];
636 emit_instr(ctx, dsll, MIPS_R_T8, MIPS_R_A2, 3);
637 emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, MIPS_R_A1);
638 off = offsetof(struct bpf_array, ptrs);
639 emit_instr(ctx, ld, MIPS_R_AT, off, MIPS_R_T8);
640 b_off = b_imm(this_idx + 1, ctx);
641 emit_instr(ctx, beq, MIPS_R_AT, MIPS_R_ZERO, b_off);
643 emit_instr(ctx, nop);
645 /* goto *(prog->bpf_func + 4); */
646 off = offsetof(struct bpf_prog, bpf_func);
647 emit_instr(ctx, ld, MIPS_R_T9, off, MIPS_R_AT);
648 /* All systems are go... propagate TCC */
649 emit_instr(ctx, daddu, MIPS_R_V1, MIPS_R_T5, MIPS_R_ZERO);
650 /* Skip first instruction (TCC initialization) */
651 emit_instr(ctx, daddiu, MIPS_R_T9, MIPS_R_T9, 4);
652 return build_int_epilogue(ctx, MIPS_R_T9);
655 static bool is_bad_offset(int b_off)
657 return b_off > 0x1ffff || b_off < -0x20000;
660 /* Returns the number of insn slots consumed. */
661 static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
662 int this_idx, int exit_idx)
664 int src, dst, r, td, ts, mem_off, b_off;
665 bool need_swap, did_move, cmp_eq;
666 unsigned int target = 0;
669 int bpf_op = BPF_OP(insn->code);
671 if (IS_ENABLED(CONFIG_32BIT) && ((BPF_CLASS(insn->code) == BPF_ALU64)
672 || (bpf_op == BPF_DW)))
675 switch (insn->code) {
676 case BPF_ALU64 | BPF_ADD | BPF_K: /* ALU64_IMM */
677 case BPF_ALU64 | BPF_SUB | BPF_K: /* ALU64_IMM */
678 case BPF_ALU64 | BPF_OR | BPF_K: /* ALU64_IMM */
679 case BPF_ALU64 | BPF_AND | BPF_K: /* ALU64_IMM */
680 case BPF_ALU64 | BPF_LSH | BPF_K: /* ALU64_IMM */
681 case BPF_ALU64 | BPF_RSH | BPF_K: /* ALU64_IMM */
682 case BPF_ALU64 | BPF_XOR | BPF_K: /* ALU64_IMM */
683 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ALU64_IMM */
684 case BPF_ALU64 | BPF_MOV | BPF_K: /* ALU64_IMM */
685 case BPF_ALU | BPF_MOV | BPF_K: /* ALU32_IMM */
686 case BPF_ALU | BPF_ADD | BPF_K: /* ALU32_IMM */
687 case BPF_ALU | BPF_SUB | BPF_K: /* ALU32_IMM */
688 case BPF_ALU | BPF_OR | BPF_K: /* ALU64_IMM */
689 case BPF_ALU | BPF_AND | BPF_K: /* ALU64_IMM */
690 case BPF_ALU | BPF_LSH | BPF_K: /* ALU64_IMM */
691 case BPF_ALU | BPF_RSH | BPF_K: /* ALU64_IMM */
692 case BPF_ALU | BPF_XOR | BPF_K: /* ALU64_IMM */
693 case BPF_ALU | BPF_ARSH | BPF_K: /* ALU64_IMM */
694 r = gen_imm_insn(insn, ctx, this_idx);
698 case BPF_ALU64 | BPF_MUL | BPF_K: /* ALU64_IMM */
699 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
702 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
703 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
704 if (insn->imm == 1) /* Mult by 1 is a nop */
706 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
707 if (MIPS_ISA_REV >= 6) {
708 emit_instr(ctx, dmulu, dst, dst, MIPS_R_AT);
710 emit_instr(ctx, dmultu, MIPS_R_AT, dst);
711 emit_instr(ctx, mflo, dst);
714 case BPF_ALU64 | BPF_NEG | BPF_K: /* ALU64_IMM */
715 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
718 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
719 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
720 emit_instr(ctx, dsubu, dst, MIPS_R_ZERO, dst);
722 case BPF_ALU | BPF_MUL | BPF_K: /* ALU_IMM */
723 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
726 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
727 if (td == REG_64BIT) {
729 emit_instr(ctx, sll, dst, dst, 0);
731 if (insn->imm == 1) /* Mult by 1 is a nop */
733 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
734 if (MIPS_ISA_REV >= 6) {
735 emit_instr(ctx, mulu, dst, dst, MIPS_R_AT);
737 emit_instr(ctx, multu, dst, MIPS_R_AT);
738 emit_instr(ctx, mflo, dst);
741 case BPF_ALU | BPF_NEG | BPF_K: /* ALU_IMM */
742 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
745 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
746 if (td == REG_64BIT) {
748 emit_instr(ctx, sll, dst, dst, 0);
750 emit_instr(ctx, subu, dst, MIPS_R_ZERO, dst);
752 case BPF_ALU | BPF_DIV | BPF_K: /* ALU_IMM */
753 case BPF_ALU | BPF_MOD | BPF_K: /* ALU_IMM */
756 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
759 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
762 emit_instr(ctx, sll, dst, dst, 0);
763 if (insn->imm == 1) {
764 /* div by 1 is a nop, mod by 1 is zero */
765 if (bpf_op == BPF_MOD)
766 emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO);
769 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
770 if (MIPS_ISA_REV >= 6) {
771 if (bpf_op == BPF_DIV)
772 emit_instr(ctx, divu_r6, dst, dst, MIPS_R_AT);
774 emit_instr(ctx, modu, dst, dst, MIPS_R_AT);
777 emit_instr(ctx, divu, dst, MIPS_R_AT);
778 if (bpf_op == BPF_DIV)
779 emit_instr(ctx, mflo, dst);
781 emit_instr(ctx, mfhi, dst);
783 case BPF_ALU64 | BPF_DIV | BPF_K: /* ALU_IMM */
784 case BPF_ALU64 | BPF_MOD | BPF_K: /* ALU_IMM */
787 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
790 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
791 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
792 if (insn->imm == 1) {
793 /* div by 1 is a nop, mod by 1 is zero */
794 if (bpf_op == BPF_MOD)
795 emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO);
798 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
799 if (MIPS_ISA_REV >= 6) {
800 if (bpf_op == BPF_DIV)
801 emit_instr(ctx, ddivu_r6, dst, dst, MIPS_R_AT);
803 emit_instr(ctx, modu, dst, dst, MIPS_R_AT);
806 emit_instr(ctx, ddivu, dst, MIPS_R_AT);
807 if (bpf_op == BPF_DIV)
808 emit_instr(ctx, mflo, dst);
810 emit_instr(ctx, mfhi, dst);
812 case BPF_ALU64 | BPF_MOV | BPF_X: /* ALU64_REG */
813 case BPF_ALU64 | BPF_ADD | BPF_X: /* ALU64_REG */
814 case BPF_ALU64 | BPF_SUB | BPF_X: /* ALU64_REG */
815 case BPF_ALU64 | BPF_XOR | BPF_X: /* ALU64_REG */
816 case BPF_ALU64 | BPF_OR | BPF_X: /* ALU64_REG */
817 case BPF_ALU64 | BPF_AND | BPF_X: /* ALU64_REG */
818 case BPF_ALU64 | BPF_MUL | BPF_X: /* ALU64_REG */
819 case BPF_ALU64 | BPF_DIV | BPF_X: /* ALU64_REG */
820 case BPF_ALU64 | BPF_MOD | BPF_X: /* ALU64_REG */
821 case BPF_ALU64 | BPF_LSH | BPF_X: /* ALU64_REG */
822 case BPF_ALU64 | BPF_RSH | BPF_X: /* ALU64_REG */
823 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ALU64_REG */
824 src = ebpf_to_mips_reg(ctx, insn, src_reg);
825 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
826 if (src < 0 || dst < 0)
828 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
829 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
831 if (insn->src_reg == BPF_REG_10) {
832 if (bpf_op == BPF_MOV) {
833 emit_instr(ctx, daddiu, dst, MIPS_R_SP, MAX_BPF_STACK);
836 emit_instr(ctx, daddiu, MIPS_R_AT, MIPS_R_SP, MAX_BPF_STACK);
839 } else if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
840 int tmp_reg = MIPS_R_AT;
842 if (bpf_op == BPF_MOV) {
846 emit_instr(ctx, daddu, tmp_reg, src, MIPS_R_ZERO);
847 emit_instr(ctx, dinsu, tmp_reg, MIPS_R_ZERO, 32, 32);
853 emit_instr(ctx, daddu, dst, src, MIPS_R_ZERO);
856 emit_instr(ctx, daddu, dst, dst, src);
859 emit_instr(ctx, dsubu, dst, dst, src);
862 emit_instr(ctx, xor, dst, dst, src);
865 emit_instr(ctx, or, dst, dst, src);
868 emit_instr(ctx, and, dst, dst, src);
871 if (MIPS_ISA_REV >= 6) {
872 emit_instr(ctx, dmulu, dst, dst, src);
874 emit_instr(ctx, dmultu, dst, src);
875 emit_instr(ctx, mflo, dst);
880 if (MIPS_ISA_REV >= 6) {
881 if (bpf_op == BPF_DIV)
882 emit_instr(ctx, ddivu_r6,
885 emit_instr(ctx, modu, dst, dst, src);
888 emit_instr(ctx, ddivu, dst, src);
889 if (bpf_op == BPF_DIV)
890 emit_instr(ctx, mflo, dst);
892 emit_instr(ctx, mfhi, dst);
895 emit_instr(ctx, dsllv, dst, dst, src);
898 emit_instr(ctx, dsrlv, dst, dst, src);
901 emit_instr(ctx, dsrav, dst, dst, src);
904 pr_err("ALU64_REG NOT HANDLED\n");
908 case BPF_ALU | BPF_MOV | BPF_X: /* ALU_REG */
909 case BPF_ALU | BPF_ADD | BPF_X: /* ALU_REG */
910 case BPF_ALU | BPF_SUB | BPF_X: /* ALU_REG */
911 case BPF_ALU | BPF_XOR | BPF_X: /* ALU_REG */
912 case BPF_ALU | BPF_OR | BPF_X: /* ALU_REG */
913 case BPF_ALU | BPF_AND | BPF_X: /* ALU_REG */
914 case BPF_ALU | BPF_MUL | BPF_X: /* ALU_REG */
915 case BPF_ALU | BPF_DIV | BPF_X: /* ALU_REG */
916 case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */
917 case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */
918 case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */
919 case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */
920 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
921 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
922 if (src < 0 || dst < 0)
924 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
925 if (td == REG_64BIT) {
927 emit_instr(ctx, sll, dst, dst, 0);
930 ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
931 if (ts == REG_64BIT) {
932 int tmp_reg = MIPS_R_AT;
934 if (bpf_op == BPF_MOV) {
939 emit_instr(ctx, sll, tmp_reg, src, 0);
945 emit_instr(ctx, addu, dst, src, MIPS_R_ZERO);
948 emit_instr(ctx, addu, dst, dst, src);
951 emit_instr(ctx, subu, dst, dst, src);
954 emit_instr(ctx, xor, dst, dst, src);
957 emit_instr(ctx, or, dst, dst, src);
960 emit_instr(ctx, and, dst, dst, src);
963 emit_instr(ctx, mul, dst, dst, src);
967 if (MIPS_ISA_REV >= 6) {
968 if (bpf_op == BPF_DIV)
969 emit_instr(ctx, divu_r6, dst, dst, src);
971 emit_instr(ctx, modu, dst, dst, src);
974 emit_instr(ctx, divu, dst, src);
975 if (bpf_op == BPF_DIV)
976 emit_instr(ctx, mflo, dst);
978 emit_instr(ctx, mfhi, dst);
981 emit_instr(ctx, sllv, dst, dst, src);
984 emit_instr(ctx, srlv, dst, dst, src);
987 emit_instr(ctx, srav, dst, dst, src);
990 pr_err("ALU_REG NOT HANDLED\n");
994 case BPF_JMP | BPF_EXIT:
995 if (this_idx + 1 < exit_idx) {
996 b_off = b_imm(exit_idx, ctx);
997 if (is_bad_offset(b_off))
999 emit_instr(ctx, beq, MIPS_R_ZERO, MIPS_R_ZERO, b_off);
1000 emit_instr(ctx, nop);
1003 case BPF_JMP | BPF_JEQ | BPF_K: /* JMP_IMM */
1004 case BPF_JMP | BPF_JNE | BPF_K: /* JMP_IMM */
1005 cmp_eq = (bpf_op == BPF_JEQ);
1006 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1009 if (insn->imm == 0) {
1012 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
1016 case BPF_JMP | BPF_JEQ | BPF_X: /* JMP_REG */
1017 case BPF_JMP | BPF_JNE | BPF_X:
1018 case BPF_JMP | BPF_JSLT | BPF_X:
1019 case BPF_JMP | BPF_JSLE | BPF_X:
1020 case BPF_JMP | BPF_JSGT | BPF_X:
1021 case BPF_JMP | BPF_JSGE | BPF_X:
1022 case BPF_JMP | BPF_JLT | BPF_X:
1023 case BPF_JMP | BPF_JLE | BPF_X:
1024 case BPF_JMP | BPF_JGT | BPF_X:
1025 case BPF_JMP | BPF_JGE | BPF_X:
1026 case BPF_JMP | BPF_JSET | BPF_X:
1027 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
1028 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1029 if (src < 0 || dst < 0)
1031 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
1032 ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
1033 if (td == REG_32BIT && ts != REG_32BIT) {
1034 emit_instr(ctx, sll, MIPS_R_AT, src, 0);
1036 } else if (ts == REG_32BIT && td != REG_32BIT) {
1037 emit_instr(ctx, sll, MIPS_R_AT, dst, 0);
1040 if (bpf_op == BPF_JSET) {
1041 emit_instr(ctx, and, MIPS_R_AT, dst, src);
1045 } else if (bpf_op == BPF_JSGT || bpf_op == BPF_JSLE) {
1046 emit_instr(ctx, dsubu, MIPS_R_AT, dst, src);
1047 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1048 b_off = b_imm(exit_idx, ctx);
1049 if (is_bad_offset(b_off))
1051 if (bpf_op == BPF_JSGT)
1052 emit_instr(ctx, blez, MIPS_R_AT, b_off);
1054 emit_instr(ctx, bgtz, MIPS_R_AT, b_off);
1055 emit_instr(ctx, nop);
1056 return 2; /* We consumed the exit. */
1058 b_off = b_imm(this_idx + insn->off + 1, ctx);
1059 if (is_bad_offset(b_off))
1061 if (bpf_op == BPF_JSGT)
1062 emit_instr(ctx, bgtz, MIPS_R_AT, b_off);
1064 emit_instr(ctx, blez, MIPS_R_AT, b_off);
1065 emit_instr(ctx, nop);
1067 } else if (bpf_op == BPF_JSGE || bpf_op == BPF_JSLT) {
1068 emit_instr(ctx, slt, MIPS_R_AT, dst, src);
1069 cmp_eq = bpf_op == BPF_JSGE;
1072 } else if (bpf_op == BPF_JGT || bpf_op == BPF_JLE) {
1073 /* dst or src could be AT */
1074 emit_instr(ctx, dsubu, MIPS_R_T8, dst, src);
1075 emit_instr(ctx, sltu, MIPS_R_AT, dst, src);
1076 /* SP known to be non-zero, movz becomes boolean not */
1077 if (MIPS_ISA_REV >= 6) {
1078 emit_instr(ctx, seleqz, MIPS_R_T9,
1079 MIPS_R_SP, MIPS_R_T8);
1081 emit_instr(ctx, movz, MIPS_R_T9,
1082 MIPS_R_SP, MIPS_R_T8);
1083 emit_instr(ctx, movn, MIPS_R_T9,
1084 MIPS_R_ZERO, MIPS_R_T8);
1086 emit_instr(ctx, or, MIPS_R_AT, MIPS_R_T9, MIPS_R_AT);
1087 cmp_eq = bpf_op == BPF_JGT;
1090 } else if (bpf_op == BPF_JGE || bpf_op == BPF_JLT) {
1091 emit_instr(ctx, sltu, MIPS_R_AT, dst, src);
1092 cmp_eq = bpf_op == BPF_JGE;
1095 } else { /* JNE/JEQ case */
1096 cmp_eq = (bpf_op == BPF_JEQ);
1100 * If the next insn is EXIT and we are jumping arround
1101 * only it, invert the sense of the compare and
1102 * conditionally jump to the exit. Poor man's branch
1105 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1106 b_off = b_imm(exit_idx, ctx);
1107 if (is_bad_offset(b_off)) {
1108 target = j_target(ctx, exit_idx);
1109 if (target == (unsigned int)-1)
1113 if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) {
1114 ctx->offsets[this_idx] |= OFFSETS_B_CONV;
1115 ctx->long_b_conversion = 1;
1120 emit_instr(ctx, bne, dst, src, b_off);
1122 emit_instr(ctx, beq, dst, src, b_off);
1123 emit_instr(ctx, nop);
1124 if (ctx->offsets[this_idx] & OFFSETS_B_CONV) {
1125 emit_instr(ctx, j, target);
1126 emit_instr(ctx, nop);
1128 return 2; /* We consumed the exit. */
1130 b_off = b_imm(this_idx + insn->off + 1, ctx);
1131 if (is_bad_offset(b_off)) {
1132 target = j_target(ctx, this_idx + insn->off + 1);
1133 if (target == (unsigned int)-1)
1137 if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) {
1138 ctx->offsets[this_idx] |= OFFSETS_B_CONV;
1139 ctx->long_b_conversion = 1;
1144 emit_instr(ctx, beq, dst, src, b_off);
1146 emit_instr(ctx, bne, dst, src, b_off);
1147 emit_instr(ctx, nop);
1148 if (ctx->offsets[this_idx] & OFFSETS_B_CONV) {
1149 emit_instr(ctx, j, target);
1150 emit_instr(ctx, nop);
1153 case BPF_JMP | BPF_JSGT | BPF_K: /* JMP_IMM */
1154 case BPF_JMP | BPF_JSGE | BPF_K: /* JMP_IMM */
1155 case BPF_JMP | BPF_JSLT | BPF_K: /* JMP_IMM */
1156 case BPF_JMP | BPF_JSLE | BPF_K: /* JMP_IMM */
1157 cmp_eq = (bpf_op == BPF_JSGE);
1158 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1162 if (insn->imm == 0) {
1163 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1164 b_off = b_imm(exit_idx, ctx);
1165 if (is_bad_offset(b_off))
1169 emit_instr(ctx, blez, dst, b_off);
1172 emit_instr(ctx, bltz, dst, b_off);
1175 emit_instr(ctx, bgez, dst, b_off);
1178 emit_instr(ctx, bgtz, dst, b_off);
1181 emit_instr(ctx, nop);
1182 return 2; /* We consumed the exit. */
1184 b_off = b_imm(this_idx + insn->off + 1, ctx);
1185 if (is_bad_offset(b_off))
1189 emit_instr(ctx, bgtz, dst, b_off);
1192 emit_instr(ctx, bgez, dst, b_off);
1195 emit_instr(ctx, bltz, dst, b_off);
1198 emit_instr(ctx, blez, dst, b_off);
1201 emit_instr(ctx, nop);
1205 * only "LT" compare available, so we must use imm + 1
1206 * to generate "GT" and imm -1 to generate LE
1208 if (bpf_op == BPF_JSGT)
1209 t64s = insn->imm + 1;
1210 else if (bpf_op == BPF_JSLE)
1211 t64s = insn->imm + 1;
1215 cmp_eq = bpf_op == BPF_JSGT || bpf_op == BPF_JSGE;
1216 if (t64s >= S16_MIN && t64s <= S16_MAX) {
1217 emit_instr(ctx, slti, MIPS_R_AT, dst, (int)t64s);
1222 emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s);
1223 emit_instr(ctx, slt, MIPS_R_AT, dst, MIPS_R_AT);
1228 case BPF_JMP | BPF_JGT | BPF_K:
1229 case BPF_JMP | BPF_JGE | BPF_K:
1230 case BPF_JMP | BPF_JLT | BPF_K:
1231 case BPF_JMP | BPF_JLE | BPF_K:
1232 cmp_eq = (bpf_op == BPF_JGE);
1233 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1237 * only "LT" compare available, so we must use imm + 1
1238 * to generate "GT" and imm -1 to generate LE
1240 if (bpf_op == BPF_JGT)
1241 t64s = (u64)(u32)(insn->imm) + 1;
1242 else if (bpf_op == BPF_JLE)
1243 t64s = (u64)(u32)(insn->imm) + 1;
1245 t64s = (u64)(u32)(insn->imm);
1247 cmp_eq = bpf_op == BPF_JGT || bpf_op == BPF_JGE;
1249 emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s);
1250 emit_instr(ctx, sltu, MIPS_R_AT, dst, MIPS_R_AT);
1255 case BPF_JMP | BPF_JSET | BPF_K: /* JMP_IMM */
1256 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1260 if (ctx->use_bbit_insns && hweight32((u32)insn->imm) == 1) {
1261 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1262 b_off = b_imm(exit_idx, ctx);
1263 if (is_bad_offset(b_off))
1265 emit_instr(ctx, bbit0, dst, ffs((u32)insn->imm) - 1, b_off);
1266 emit_instr(ctx, nop);
1267 return 2; /* We consumed the exit. */
1269 b_off = b_imm(this_idx + insn->off + 1, ctx);
1270 if (is_bad_offset(b_off))
1272 emit_instr(ctx, bbit1, dst, ffs((u32)insn->imm) - 1, b_off);
1273 emit_instr(ctx, nop);
1276 t64 = (u32)insn->imm;
1277 emit_const_to_reg(ctx, MIPS_R_AT, t64);
1278 emit_instr(ctx, and, MIPS_R_AT, dst, MIPS_R_AT);
1284 case BPF_JMP | BPF_JA:
1286 * Prefer relative branch for easier debugging, but
1287 * fall back if needed.
1289 b_off = b_imm(this_idx + insn->off + 1, ctx);
1290 if (is_bad_offset(b_off)) {
1291 target = j_target(ctx, this_idx + insn->off + 1);
1292 if (target == (unsigned int)-1)
1294 emit_instr(ctx, j, target);
1296 emit_instr(ctx, b, b_off);
1298 emit_instr(ctx, nop);
1300 case BPF_LD | BPF_DW | BPF_IMM:
1301 if (insn->src_reg != 0)
1303 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1306 t64 = ((u64)(u32)insn->imm) | ((u64)(insn + 1)->imm << 32);
1307 emit_const_to_reg(ctx, dst, t64);
1308 return 2; /* Double slot insn */
1310 case BPF_JMP | BPF_CALL:
1311 ctx->flags |= EBPF_SAVE_RA;
1312 t64s = (s64)insn->imm + (long)__bpf_call_base;
1313 emit_const_to_reg(ctx, MIPS_R_T9, (u64)t64s);
1314 emit_instr(ctx, jalr, MIPS_R_RA, MIPS_R_T9);
1316 emit_instr(ctx, nop);
1319 case BPF_JMP | BPF_TAIL_CALL:
1320 if (emit_bpf_tail_call(ctx, this_idx))
1324 case BPF_ALU | BPF_END | BPF_FROM_BE:
1325 case BPF_ALU | BPF_END | BPF_FROM_LE:
1326 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1329 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
1330 if (insn->imm == 64 && td == REG_32BIT)
1331 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
1333 if (insn->imm != 64 && td == REG_64BIT) {
1335 emit_instr(ctx, sll, dst, dst, 0);
1339 need_swap = (BPF_SRC(insn->code) == BPF_FROM_LE);
1341 need_swap = (BPF_SRC(insn->code) == BPF_FROM_BE);
1343 if (insn->imm == 16) {
1345 emit_instr(ctx, wsbh, dst, dst);
1346 emit_instr(ctx, andi, dst, dst, 0xffff);
1347 } else if (insn->imm == 32) {
1349 emit_instr(ctx, wsbh, dst, dst);
1350 emit_instr(ctx, rotr, dst, dst, 16);
1352 } else { /* 64-bit*/
1354 emit_instr(ctx, dsbh, dst, dst);
1355 emit_instr(ctx, dshd, dst, dst);
1360 case BPF_ST | BPF_B | BPF_MEM:
1361 case BPF_ST | BPF_H | BPF_MEM:
1362 case BPF_ST | BPF_W | BPF_MEM:
1363 case BPF_ST | BPF_DW | BPF_MEM:
1364 if (insn->dst_reg == BPF_REG_10) {
1365 ctx->flags |= EBPF_SEEN_FP;
1367 mem_off = insn->off + MAX_BPF_STACK;
1369 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1372 mem_off = insn->off;
1374 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
1375 switch (BPF_SIZE(insn->code)) {
1377 emit_instr(ctx, sb, MIPS_R_AT, mem_off, dst);
1380 emit_instr(ctx, sh, MIPS_R_AT, mem_off, dst);
1383 emit_instr(ctx, sw, MIPS_R_AT, mem_off, dst);
1386 emit_instr(ctx, sd, MIPS_R_AT, mem_off, dst);
1391 case BPF_LDX | BPF_B | BPF_MEM:
1392 case BPF_LDX | BPF_H | BPF_MEM:
1393 case BPF_LDX | BPF_W | BPF_MEM:
1394 case BPF_LDX | BPF_DW | BPF_MEM:
1395 if (insn->src_reg == BPF_REG_10) {
1396 ctx->flags |= EBPF_SEEN_FP;
1398 mem_off = insn->off + MAX_BPF_STACK;
1400 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
1403 mem_off = insn->off;
1405 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1408 switch (BPF_SIZE(insn->code)) {
1410 emit_instr(ctx, lbu, dst, mem_off, src);
1413 emit_instr(ctx, lhu, dst, mem_off, src);
1416 emit_instr(ctx, lw, dst, mem_off, src);
1419 emit_instr(ctx, ld, dst, mem_off, src);
1424 case BPF_STX | BPF_B | BPF_MEM:
1425 case BPF_STX | BPF_H | BPF_MEM:
1426 case BPF_STX | BPF_W | BPF_MEM:
1427 case BPF_STX | BPF_DW | BPF_MEM:
1428 case BPF_STX | BPF_W | BPF_XADD:
1429 case BPF_STX | BPF_DW | BPF_XADD:
1430 if (insn->dst_reg == BPF_REG_10) {
1431 ctx->flags |= EBPF_SEEN_FP;
1433 mem_off = insn->off + MAX_BPF_STACK;
1435 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1438 mem_off = insn->off;
1440 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
1443 if (BPF_MODE(insn->code) == BPF_XADD) {
1445 * If mem_off does not fit within the 9 bit ll/sc
1446 * instruction immediate field, use a temp reg.
1448 if (MIPS_ISA_REV >= 6 &&
1449 (mem_off >= BIT(8) || mem_off < -BIT(8))) {
1450 emit_instr(ctx, daddiu, MIPS_R_T6,
1455 switch (BPF_SIZE(insn->code)) {
1457 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1458 emit_instr(ctx, sll, MIPS_R_AT, src, 0);
1461 emit_instr(ctx, ll, MIPS_R_T8, mem_off, dst);
1462 emit_instr(ctx, addu, MIPS_R_T8, MIPS_R_T8, src);
1463 emit_instr(ctx, sc, MIPS_R_T8, mem_off, dst);
1465 * On failure back up to LL (-4
1466 * instructions of 4 bytes each
1468 emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4);
1469 emit_instr(ctx, nop);
1472 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1473 emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO);
1474 emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32);
1477 emit_instr(ctx, lld, MIPS_R_T8, mem_off, dst);
1478 emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, src);
1479 emit_instr(ctx, scd, MIPS_R_T8, mem_off, dst);
1480 emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4);
1481 emit_instr(ctx, nop);
1484 } else { /* BPF_MEM */
1485 switch (BPF_SIZE(insn->code)) {
1487 emit_instr(ctx, sb, src, mem_off, dst);
1490 emit_instr(ctx, sh, src, mem_off, dst);
1493 emit_instr(ctx, sw, src, mem_off, dst);
1496 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1497 emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO);
1498 emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32);
1501 emit_instr(ctx, sd, src, mem_off, dst);
1508 pr_err("NOT HANDLED %d - (%02x)\n",
1509 this_idx, (unsigned int)insn->code);
1515 #define RVT_VISITED_MASK 0xc000000000000000ull
1516 #define RVT_FALL_THROUGH 0x4000000000000000ull
1517 #define RVT_BRANCH_TAKEN 0x8000000000000000ull
1518 #define RVT_DONE (RVT_FALL_THROUGH | RVT_BRANCH_TAKEN)
1520 static int build_int_body(struct jit_ctx *ctx)
1522 const struct bpf_prog *prog = ctx->skf;
1523 const struct bpf_insn *insn;
1526 for (i = 0; i < prog->len; ) {
1527 insn = prog->insnsi + i;
1528 if ((ctx->reg_val_types[i] & RVT_VISITED_MASK) == 0) {
1529 /* dead instruction, don't emit it. */
1534 if (ctx->target == NULL)
1535 ctx->offsets[i] = (ctx->offsets[i] & OFFSETS_B_CONV) | (ctx->idx * 4);
1537 r = build_one_insn(insn, ctx, i, prog->len);
1542 /* epilogue offset */
1543 if (ctx->target == NULL)
1544 ctx->offsets[i] = ctx->idx * 4;
1547 * All exits have an offset of the epilogue, some offsets may
1548 * not have been set due to banch-around threading, so set
1551 if (ctx->target == NULL)
1552 for (i = 0; i < prog->len; i++) {
1553 insn = prog->insnsi + i;
1554 if (insn->code == (BPF_JMP | BPF_EXIT))
1555 ctx->offsets[i] = ctx->idx * 4;
1560 /* return the last idx processed, or negative for error */
1561 static int reg_val_propagate_range(struct jit_ctx *ctx, u64 initial_rvt,
1562 int start_idx, bool follow_taken)
1564 const struct bpf_prog *prog = ctx->skf;
1565 const struct bpf_insn *insn;
1566 u64 exit_rvt = initial_rvt;
1567 u64 *rvt = ctx->reg_val_types;
1571 for (idx = start_idx; idx < prog->len; idx++) {
1572 rvt[idx] = (rvt[idx] & RVT_VISITED_MASK) | exit_rvt;
1573 insn = prog->insnsi + idx;
1574 switch (BPF_CLASS(insn->code)) {
1576 switch (BPF_OP(insn->code)) {
1588 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1591 if (BPF_SRC(insn->code)) {
1592 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1594 /* IMM to REG move*/
1596 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1598 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1602 if (insn->imm == 64)
1603 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1604 else if (insn->imm == 32)
1605 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1606 else /* insn->imm == 16 */
1607 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1610 rvt[idx] |= RVT_DONE;
1613 switch (BPF_OP(insn->code)) {
1615 if (BPF_SRC(insn->code)) {
1616 /* REG to REG move*/
1617 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1619 /* IMM to REG move*/
1621 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1623 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT);
1627 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1629 rvt[idx] |= RVT_DONE;
1632 switch (BPF_SIZE(insn->code)) {
1634 if (BPF_MODE(insn->code) == BPF_IMM) {
1637 val = (s64)((u32)insn->imm | ((u64)(insn + 1)->imm << 32));
1638 if (val > 0 && val <= S32_MAX)
1639 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1640 else if (val >= S32_MIN && val <= S32_MAX)
1641 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT);
1643 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1644 rvt[idx] |= RVT_DONE;
1647 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1652 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1655 if (BPF_MODE(insn->code) == BPF_IMM)
1656 set_reg_val_type(&exit_rvt, insn->dst_reg,
1657 insn->imm >= 0 ? REG_32BIT_POS : REG_32BIT);
1659 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1662 rvt[idx] |= RVT_DONE;
1665 switch (BPF_SIZE(insn->code)) {
1667 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1671 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1674 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1677 rvt[idx] |= RVT_DONE;
1680 switch (BPF_OP(insn->code)) {
1682 rvt[idx] = RVT_DONE | exit_rvt;
1683 rvt[prog->len] = exit_rvt;
1686 rvt[idx] |= RVT_DONE;
1701 rvt[idx] |= RVT_BRANCH_TAKEN;
1703 follow_taken = false;
1705 rvt[idx] |= RVT_FALL_THROUGH;
1709 set_reg_val_type(&exit_rvt, BPF_REG_0, REG_64BIT);
1710 /* Upon call return, argument registers are clobbered. */
1711 for (reg = BPF_REG_0; reg <= BPF_REG_5; reg++)
1712 set_reg_val_type(&exit_rvt, reg, REG_64BIT);
1714 rvt[idx] |= RVT_DONE;
1717 WARN(1, "Unhandled BPF_JMP case.\n");
1718 rvt[idx] |= RVT_DONE;
1723 rvt[idx] |= RVT_DONE;
1731 * Track the value range (i.e. 32-bit vs. 64-bit) of each register at
1732 * each eBPF insn. This allows unneeded sign and zero extension
1733 * operations to be omitted.
1735 * Doesn't handle yet confluence of control paths with conflicting
1736 * ranges, but it is good enough for most sane code.
1738 static int reg_val_propagate(struct jit_ctx *ctx)
1740 const struct bpf_prog *prog = ctx->skf;
1746 * 11 registers * 3 bits/reg leaves top bits free for other
1747 * uses. Bit-62..63 used to see if we have visited an insn.
1751 /* Upon entry, argument registers are 64-bit. */
1752 for (reg = BPF_REG_1; reg <= BPF_REG_5; reg++)
1753 set_reg_val_type(&exit_rvt, reg, REG_64BIT);
1756 * First follow all conditional branches on the fall-through
1757 * edge of control flow..
1759 reg_val_propagate_range(ctx, exit_rvt, 0, false);
1762 * Then repeatedly find the first conditional branch where
1763 * both edges of control flow have not been taken, and follow
1764 * the branch taken edge. We will end up restarting the
1765 * search once per conditional branch insn.
1767 for (i = 0; i < prog->len; i++) {
1768 u64 rvt = ctx->reg_val_types[i];
1770 if ((rvt & RVT_VISITED_MASK) == RVT_DONE ||
1771 (rvt & RVT_VISITED_MASK) == 0)
1773 if ((rvt & RVT_VISITED_MASK) == RVT_FALL_THROUGH) {
1774 reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, true);
1775 } else { /* RVT_BRANCH_TAKEN */
1776 WARN(1, "Unexpected RVT_BRANCH_TAKEN case.\n");
1777 reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, false);
1779 goto restart_search;
1782 * Eventually all conditional branches have been followed on
1783 * both branches and we are done. Any insn that has not been
1784 * visited at this point is dead.
1790 static void jit_fill_hole(void *area, unsigned int size)
1794 /* We are guaranteed to have aligned memory. */
1795 for (p = area; size >= sizeof(u32); size -= sizeof(u32))
1796 uasm_i_break(&p, BRK_BUG); /* Increments p */
1799 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1801 struct bpf_prog *orig_prog = prog;
1802 bool tmp_blinded = false;
1803 struct bpf_prog *tmp;
1804 struct bpf_binary_header *header = NULL;
1806 unsigned int image_size;
1809 if (!prog->jit_requested || MIPS_ISA_REV < 2)
1812 tmp = bpf_jit_blind_constants(prog);
1813 /* If blinding was requested and we failed during blinding,
1814 * we must fall back to the interpreter.
1823 memset(&ctx, 0, sizeof(ctx));
1826 switch (current_cpu_type()) {
1827 case CPU_CAVIUM_OCTEON:
1828 case CPU_CAVIUM_OCTEON_PLUS:
1829 case CPU_CAVIUM_OCTEON2:
1830 case CPU_CAVIUM_OCTEON3:
1831 ctx.use_bbit_insns = 1;
1834 ctx.use_bbit_insns = 0;
1838 ctx.offsets = kcalloc(prog->len + 1, sizeof(*ctx.offsets), GFP_KERNEL);
1839 if (ctx.offsets == NULL)
1842 ctx.reg_val_types = kcalloc(prog->len + 1, sizeof(*ctx.reg_val_types), GFP_KERNEL);
1843 if (ctx.reg_val_types == NULL)
1848 if (reg_val_propagate(&ctx))
1852 * First pass discovers used resources and instruction offsets
1853 * assuming short branches are used.
1855 if (build_int_body(&ctx))
1859 * If no calls are made (EBPF_SAVE_RA), then tail call count
1860 * in $v1, else we must save in n$s4.
1862 if (ctx.flags & EBPF_SEEN_TC) {
1863 if (ctx.flags & EBPF_SAVE_RA)
1864 ctx.flags |= EBPF_SAVE_S4;
1866 ctx.flags |= EBPF_TCC_IN_V1;
1870 * Second pass generates offsets, if any branches are out of
1871 * range a jump-around long sequence is generated, and we have
1872 * to try again from the beginning to generate the new
1873 * offsets. This is done until no additional conversions are
1878 ctx.gen_b_offsets = 1;
1879 ctx.long_b_conversion = 0;
1880 if (gen_int_prologue(&ctx))
1882 if (build_int_body(&ctx))
1884 if (build_int_epilogue(&ctx, MIPS_R_RA))
1886 } while (ctx.long_b_conversion);
1888 image_size = 4 * ctx.idx;
1890 header = bpf_jit_binary_alloc(image_size, &image_ptr,
1891 sizeof(u32), jit_fill_hole);
1895 ctx.target = (u32 *)image_ptr;
1897 /* Third pass generates the code */
1899 if (gen_int_prologue(&ctx))
1901 if (build_int_body(&ctx))
1903 if (build_int_epilogue(&ctx, MIPS_R_RA))
1906 /* Update the icache */
1907 flush_icache_range((unsigned long)ctx.target,
1908 (unsigned long)&ctx.target[ctx.idx]);
1910 if (bpf_jit_enable > 1)
1912 bpf_jit_dump(prog->len, image_size, 2, ctx.target);
1914 bpf_jit_binary_lock_ro(header);
1915 prog->bpf_func = (void *)ctx.target;
1917 prog->jited_len = image_size;
1920 bpf_jit_prog_release_other(prog, prog == orig_prog ?
1923 kfree(ctx.reg_val_types);
1930 bpf_jit_binary_free(header);