2 * Just-In-Time compiler for eBPF filters on MIPS
4 * Copyright (c) 2017 Cavium, Inc.
8 * Copyright (c) 2014 Imagination Technologies Ltd.
9 * Author: Markos Chandras <markos.chandras@imgtec.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; version 2 of the License.
16 #include <linux/bitops.h>
17 #include <linux/errno.h>
18 #include <linux/filter.h>
19 #include <linux/bpf.h>
20 #include <linux/slab.h>
21 #include <asm/bitops.h>
22 #include <asm/byteorder.h>
23 #include <asm/cacheflush.h>
24 #include <asm/cpu-features.h>
27 /* Registers used by JIT */
30 #define MIPS_R_V0 2 /* BPF_R0 */
32 #define MIPS_R_A0 4 /* BPF_R1 */
33 #define MIPS_R_A1 5 /* BPF_R2 */
34 #define MIPS_R_A2 6 /* BPF_R3 */
35 #define MIPS_R_A3 7 /* BPF_R4 */
36 #define MIPS_R_A4 8 /* BPF_R5 */
37 #define MIPS_R_T4 12 /* BPF_AX */
41 #define MIPS_R_S0 16 /* BPF_R6 */
42 #define MIPS_R_S1 17 /* BPF_R7 */
43 #define MIPS_R_S2 18 /* BPF_R8 */
44 #define MIPS_R_S3 19 /* BPF_R9 */
45 #define MIPS_R_S4 20 /* BPF_TCC */
55 #define EBPF_SAVE_S0 BIT(0)
56 #define EBPF_SAVE_S1 BIT(1)
57 #define EBPF_SAVE_S2 BIT(2)
58 #define EBPF_SAVE_S3 BIT(3)
59 #define EBPF_SAVE_S4 BIT(4)
60 #define EBPF_SAVE_RA BIT(5)
61 #define EBPF_SEEN_FP BIT(6)
62 #define EBPF_SEEN_TC BIT(7)
63 #define EBPF_TCC_IN_V1 BIT(8)
66 * For the mips64 ISA, we need to track the value range or type for
67 * each JIT register. The BPF machine requires zero extended 32-bit
68 * values, but the mips64 ISA requires sign extended 32-bit values.
69 * At each point in the BPF program we track the state of every
70 * register so that we can zero extend or sign extend as the BPF
76 /* not known to be 32-bit compatible. */
78 /* 32-bit compatible, no truncation needed for 64-bit ops. */
80 /* 32-bit compatible, need truncation for 64-bit ops. */
82 /* 32-bit no sign/zero extension needed. */
87 * high bit of offsets indicates if long branch conversion done at
90 #define OFFSETS_B_CONV BIT(31)
93 * struct jit_ctx - JIT context
95 * @stack_size: eBPF stack size
96 * @idx: Instruction index
98 * @offsets: Instruction offsets
99 * @target: Memory location for the compiled filter
100 * @reg_val_types Packed enum reg_val_type for each register.
103 const struct bpf_prog *skf;
110 unsigned int long_b_conversion:1;
111 unsigned int gen_b_offsets:1;
112 unsigned int use_bbit_insns:1;
115 static void set_reg_val_type(u64 *rvt, int reg, enum reg_val_type type)
117 *rvt &= ~(7ull << (reg * 3));
118 *rvt |= ((u64)type << (reg * 3));
121 static enum reg_val_type get_reg_val_type(const struct jit_ctx *ctx,
124 return (ctx->reg_val_types[index] >> (reg * 3)) & 7;
127 /* Simply emit the instruction if the JIT memory space has been allocated */
128 #define emit_instr(ctx, func, ...) \
130 if ((ctx)->target != NULL) { \
131 u32 *p = &(ctx)->target[ctx->idx]; \
132 uasm_i_##func(&p, ##__VA_ARGS__); \
137 static unsigned int j_target(struct jit_ctx *ctx, int target_idx)
139 unsigned long target_va, base_va;
145 base_va = (unsigned long)ctx->target;
146 target_va = base_va + (ctx->offsets[target_idx] & ~OFFSETS_B_CONV);
148 if ((base_va & ~0x0ffffffful) != (target_va & ~0x0ffffffful))
149 return (unsigned int)-1;
150 r = target_va & 0x0ffffffful;
154 /* Compute the immediate value for PC-relative branches. */
155 static u32 b_imm(unsigned int tgt, struct jit_ctx *ctx)
157 if (!ctx->gen_b_offsets)
161 * We want a pc-relative branch. tgt is the instruction offset
162 * we want to jump to.
165 * I: target_offset <- sign_extend(offset)
166 * I+1: PC += target_offset (delay slot)
168 * ctx->idx currently points to the branch instruction
169 * but the offset is added to the delay slot so we need
172 return (ctx->offsets[tgt] & ~OFFSETS_B_CONV) -
176 enum which_ebpf_reg {
184 * For eBPF, the register mapping naturally falls out of the
185 * requirements of eBPF and the MIPS n64 ABI. We don't maintain a
186 * separate frame pointer, so BPF_REG_10 relative accesses are
187 * adjusted to be $sp relative.
189 int ebpf_to_mips_reg(struct jit_ctx *ctx, const struct bpf_insn *insn,
190 enum which_ebpf_reg w)
192 int ebpf_reg = (w == src_reg || w == src_reg_no_fp) ?
193 insn->src_reg : insn->dst_reg;
209 ctx->flags |= EBPF_SAVE_S0;
212 ctx->flags |= EBPF_SAVE_S1;
215 ctx->flags |= EBPF_SAVE_S2;
218 ctx->flags |= EBPF_SAVE_S3;
221 if (w == dst_reg || w == src_reg_no_fp)
223 ctx->flags |= EBPF_SEEN_FP;
225 * Needs special handling, return something that
226 * cannot be clobbered just in case.
233 WARN(1, "Illegal bpf reg: %d\n", ebpf_reg);
238 * eBPF stack frame will be something like:
240 * Entry $sp ------> +--------------------------------+
242 * +--------------------------------+
244 * +--------------------------------+
246 * +--------------------------------+
248 * +--------------------------------+
250 * +--------------------------------+
252 * +--------------------------------+
253 * | tmp-storage (if $ra saved) |
254 * $sp + tmp_offset --> +--------------------------------+ <--BPF_REG_10
255 * | BPF_REG_10 relative storage |
256 * | MAX_BPF_STACK (optional) |
260 * $sp --------> +--------------------------------+
262 * If BPF_REG_10 is never referenced, then the MAX_BPF_STACK sized
263 * area is not allocated.
265 static int gen_int_prologue(struct jit_ctx *ctx)
267 int stack_adjust = 0;
271 if (ctx->flags & EBPF_SAVE_RA)
273 * If RA we are doing a function call and may need
274 * extra 8-byte tmp area.
277 if (ctx->flags & EBPF_SAVE_S0)
279 if (ctx->flags & EBPF_SAVE_S1)
281 if (ctx->flags & EBPF_SAVE_S2)
283 if (ctx->flags & EBPF_SAVE_S3)
285 if (ctx->flags & EBPF_SAVE_S4)
288 BUILD_BUG_ON(MAX_BPF_STACK & 7);
289 locals_size = (ctx->flags & EBPF_SEEN_FP) ? MAX_BPF_STACK : 0;
291 stack_adjust += locals_size;
293 ctx->stack_size = stack_adjust;
296 * First instruction initializes the tail call count (TCC).
297 * On tail call we skip this instruction, and the TCC is
298 * passed in $v1 from the caller.
300 emit_instr(ctx, daddiu, MIPS_R_V1, MIPS_R_ZERO, MAX_TAIL_CALL_CNT);
302 emit_instr(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack_adjust);
306 store_offset = stack_adjust - 8;
308 if (ctx->flags & EBPF_SAVE_RA) {
309 emit_instr(ctx, sd, MIPS_R_RA, store_offset, MIPS_R_SP);
312 if (ctx->flags & EBPF_SAVE_S0) {
313 emit_instr(ctx, sd, MIPS_R_S0, store_offset, MIPS_R_SP);
316 if (ctx->flags & EBPF_SAVE_S1) {
317 emit_instr(ctx, sd, MIPS_R_S1, store_offset, MIPS_R_SP);
320 if (ctx->flags & EBPF_SAVE_S2) {
321 emit_instr(ctx, sd, MIPS_R_S2, store_offset, MIPS_R_SP);
324 if (ctx->flags & EBPF_SAVE_S3) {
325 emit_instr(ctx, sd, MIPS_R_S3, store_offset, MIPS_R_SP);
328 if (ctx->flags & EBPF_SAVE_S4) {
329 emit_instr(ctx, sd, MIPS_R_S4, store_offset, MIPS_R_SP);
333 if ((ctx->flags & EBPF_SEEN_TC) && !(ctx->flags & EBPF_TCC_IN_V1))
334 emit_instr(ctx, daddu, MIPS_R_S4, MIPS_R_V1, MIPS_R_ZERO);
339 static int build_int_epilogue(struct jit_ctx *ctx, int dest_reg)
341 const struct bpf_prog *prog = ctx->skf;
342 int stack_adjust = ctx->stack_size;
343 int store_offset = stack_adjust - 8;
344 enum reg_val_type td;
347 if (dest_reg == MIPS_R_RA) {
348 /* Don't let zero extended value escape. */
349 td = get_reg_val_type(ctx, prog->len, BPF_REG_0);
351 emit_instr(ctx, sll, r0, r0, 0);
354 if (ctx->flags & EBPF_SAVE_RA) {
355 emit_instr(ctx, ld, MIPS_R_RA, store_offset, MIPS_R_SP);
358 if (ctx->flags & EBPF_SAVE_S0) {
359 emit_instr(ctx, ld, MIPS_R_S0, store_offset, MIPS_R_SP);
362 if (ctx->flags & EBPF_SAVE_S1) {
363 emit_instr(ctx, ld, MIPS_R_S1, store_offset, MIPS_R_SP);
366 if (ctx->flags & EBPF_SAVE_S2) {
367 emit_instr(ctx, ld, MIPS_R_S2, store_offset, MIPS_R_SP);
370 if (ctx->flags & EBPF_SAVE_S3) {
371 emit_instr(ctx, ld, MIPS_R_S3, store_offset, MIPS_R_SP);
374 if (ctx->flags & EBPF_SAVE_S4) {
375 emit_instr(ctx, ld, MIPS_R_S4, store_offset, MIPS_R_SP);
378 emit_instr(ctx, jr, dest_reg);
381 emit_instr(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, stack_adjust);
383 emit_instr(ctx, nop);
388 static void gen_imm_to_reg(const struct bpf_insn *insn, int reg,
391 if (insn->imm >= S16_MIN && insn->imm <= S16_MAX) {
392 emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm);
394 int lower = (s16)(insn->imm & 0xffff);
395 int upper = insn->imm - lower;
397 emit_instr(ctx, lui, reg, upper >> 16);
398 emit_instr(ctx, addiu, reg, reg, lower);
402 static int gen_imm_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
405 int upper_bound, lower_bound;
406 int dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
411 switch (BPF_OP(insn->code)) {
414 upper_bound = S16_MAX;
415 lower_bound = S16_MIN;
418 upper_bound = -(int)S16_MIN;
419 lower_bound = -(int)S16_MAX;
424 upper_bound = 0xffff;
430 /* Shift amounts are truncated, no need for bounds */
431 upper_bound = S32_MAX;
432 lower_bound = S32_MIN;
439 * Immediate move clobbers the register, so no sign/zero
442 if (BPF_CLASS(insn->code) == BPF_ALU64 &&
443 BPF_OP(insn->code) != BPF_MOV &&
444 get_reg_val_type(ctx, idx, insn->dst_reg) == REG_32BIT)
445 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
446 /* BPF_ALU | BPF_LSH doesn't need separate sign extension */
447 if (BPF_CLASS(insn->code) == BPF_ALU &&
448 BPF_OP(insn->code) != BPF_LSH &&
449 BPF_OP(insn->code) != BPF_MOV &&
450 get_reg_val_type(ctx, idx, insn->dst_reg) != REG_32BIT)
451 emit_instr(ctx, sll, dst, dst, 0);
453 if (insn->imm >= lower_bound && insn->imm <= upper_bound) {
454 /* single insn immediate case */
455 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) {
456 case BPF_ALU64 | BPF_MOV:
457 emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, insn->imm);
459 case BPF_ALU64 | BPF_AND:
460 case BPF_ALU | BPF_AND:
461 emit_instr(ctx, andi, dst, dst, insn->imm);
463 case BPF_ALU64 | BPF_OR:
464 case BPF_ALU | BPF_OR:
465 emit_instr(ctx, ori, dst, dst, insn->imm);
467 case BPF_ALU64 | BPF_XOR:
468 case BPF_ALU | BPF_XOR:
469 emit_instr(ctx, xori, dst, dst, insn->imm);
471 case BPF_ALU64 | BPF_ADD:
472 emit_instr(ctx, daddiu, dst, dst, insn->imm);
474 case BPF_ALU64 | BPF_SUB:
475 emit_instr(ctx, daddiu, dst, dst, -insn->imm);
477 case BPF_ALU64 | BPF_RSH:
478 emit_instr(ctx, dsrl_safe, dst, dst, insn->imm & 0x3f);
480 case BPF_ALU | BPF_RSH:
481 emit_instr(ctx, srl, dst, dst, insn->imm & 0x1f);
483 case BPF_ALU64 | BPF_LSH:
484 emit_instr(ctx, dsll_safe, dst, dst, insn->imm & 0x3f);
486 case BPF_ALU | BPF_LSH:
487 emit_instr(ctx, sll, dst, dst, insn->imm & 0x1f);
489 case BPF_ALU64 | BPF_ARSH:
490 emit_instr(ctx, dsra_safe, dst, dst, insn->imm & 0x3f);
492 case BPF_ALU | BPF_ARSH:
493 emit_instr(ctx, sra, dst, dst, insn->imm & 0x1f);
495 case BPF_ALU | BPF_MOV:
496 emit_instr(ctx, addiu, dst, MIPS_R_ZERO, insn->imm);
498 case BPF_ALU | BPF_ADD:
499 emit_instr(ctx, addiu, dst, dst, insn->imm);
501 case BPF_ALU | BPF_SUB:
502 emit_instr(ctx, addiu, dst, dst, -insn->imm);
508 /* multi insn immediate case */
509 if (BPF_OP(insn->code) == BPF_MOV) {
510 gen_imm_to_reg(insn, dst, ctx);
512 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
513 switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) {
514 case BPF_ALU64 | BPF_AND:
515 case BPF_ALU | BPF_AND:
516 emit_instr(ctx, and, dst, dst, MIPS_R_AT);
518 case BPF_ALU64 | BPF_OR:
519 case BPF_ALU | BPF_OR:
520 emit_instr(ctx, or, dst, dst, MIPS_R_AT);
522 case BPF_ALU64 | BPF_XOR:
523 case BPF_ALU | BPF_XOR:
524 emit_instr(ctx, xor, dst, dst, MIPS_R_AT);
526 case BPF_ALU64 | BPF_ADD:
527 emit_instr(ctx, daddu, dst, dst, MIPS_R_AT);
529 case BPF_ALU64 | BPF_SUB:
530 emit_instr(ctx, dsubu, dst, dst, MIPS_R_AT);
532 case BPF_ALU | BPF_ADD:
533 emit_instr(ctx, addu, dst, dst, MIPS_R_AT);
535 case BPF_ALU | BPF_SUB:
536 emit_instr(ctx, subu, dst, dst, MIPS_R_AT);
547 static void emit_const_to_reg(struct jit_ctx *ctx, int dst, u64 value)
549 if (value >= 0xffffffffffff8000ull || value < 0x8000ull) {
550 emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, (int)value);
551 } else if (value >= 0xffffffff80000000ull ||
552 (value < 0x80000000 && value > 0xffff)) {
553 emit_instr(ctx, lui, dst, (s32)(s16)(value >> 16));
554 emit_instr(ctx, ori, dst, dst, (unsigned int)(value & 0xffff));
557 bool seen_part = false;
558 int needed_shift = 0;
560 for (i = 0; i < 4; i++) {
561 u64 part = (value >> (16 * (3 - i))) & 0xffff;
563 if (seen_part && needed_shift > 0 && (part || i == 3)) {
564 emit_instr(ctx, dsll_safe, dst, dst, needed_shift);
568 if (i == 0 || (!seen_part && i < 3 && part < 0x8000)) {
569 emit_instr(ctx, lui, dst, (s32)(s16)part);
572 emit_instr(ctx, ori, dst,
573 seen_part ? dst : MIPS_R_ZERO,
584 static int emit_bpf_tail_call(struct jit_ctx *ctx, int this_idx)
588 ctx->flags |= EBPF_SEEN_TC;
590 * if (index >= array->map.max_entries)
593 off = offsetof(struct bpf_array, map.max_entries);
594 emit_instr(ctx, lwu, MIPS_R_T5, off, MIPS_R_A1);
595 emit_instr(ctx, sltu, MIPS_R_AT, MIPS_R_T5, MIPS_R_A2);
596 b_off = b_imm(this_idx + 1, ctx);
597 emit_instr(ctx, bne, MIPS_R_AT, MIPS_R_ZERO, b_off);
603 emit_instr(ctx, daddiu, MIPS_R_T5,
604 (ctx->flags & EBPF_TCC_IN_V1) ? MIPS_R_V1 : MIPS_R_S4, -1);
605 b_off = b_imm(this_idx + 1, ctx);
606 emit_instr(ctx, bltz, MIPS_R_T5, b_off);
608 * prog = array->ptrs[index];
613 emit_instr(ctx, dsll, MIPS_R_T8, MIPS_R_A2, 3);
614 emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, MIPS_R_A1);
615 off = offsetof(struct bpf_array, ptrs);
616 emit_instr(ctx, ld, MIPS_R_AT, off, MIPS_R_T8);
617 b_off = b_imm(this_idx + 1, ctx);
618 emit_instr(ctx, beq, MIPS_R_AT, MIPS_R_ZERO, b_off);
620 emit_instr(ctx, nop);
622 /* goto *(prog->bpf_func + 4); */
623 off = offsetof(struct bpf_prog, bpf_func);
624 emit_instr(ctx, ld, MIPS_R_T9, off, MIPS_R_AT);
625 /* All systems are go... propagate TCC */
626 emit_instr(ctx, daddu, MIPS_R_V1, MIPS_R_T5, MIPS_R_ZERO);
627 /* Skip first instruction (TCC initialization) */
628 emit_instr(ctx, daddiu, MIPS_R_T9, MIPS_R_T9, 4);
629 return build_int_epilogue(ctx, MIPS_R_T9);
632 static bool is_bad_offset(int b_off)
634 return b_off > 0x1ffff || b_off < -0x20000;
637 /* Returns the number of insn slots consumed. */
638 static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
639 int this_idx, int exit_idx)
641 int src, dst, r, td, ts, mem_off, b_off;
642 bool need_swap, did_move, cmp_eq;
643 unsigned int target = 0;
646 int bpf_op = BPF_OP(insn->code);
648 switch (insn->code) {
649 case BPF_ALU64 | BPF_ADD | BPF_K: /* ALU64_IMM */
650 case BPF_ALU64 | BPF_SUB | BPF_K: /* ALU64_IMM */
651 case BPF_ALU64 | BPF_OR | BPF_K: /* ALU64_IMM */
652 case BPF_ALU64 | BPF_AND | BPF_K: /* ALU64_IMM */
653 case BPF_ALU64 | BPF_LSH | BPF_K: /* ALU64_IMM */
654 case BPF_ALU64 | BPF_RSH | BPF_K: /* ALU64_IMM */
655 case BPF_ALU64 | BPF_XOR | BPF_K: /* ALU64_IMM */
656 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ALU64_IMM */
657 case BPF_ALU64 | BPF_MOV | BPF_K: /* ALU64_IMM */
658 case BPF_ALU | BPF_MOV | BPF_K: /* ALU32_IMM */
659 case BPF_ALU | BPF_ADD | BPF_K: /* ALU32_IMM */
660 case BPF_ALU | BPF_SUB | BPF_K: /* ALU32_IMM */
661 case BPF_ALU | BPF_OR | BPF_K: /* ALU64_IMM */
662 case BPF_ALU | BPF_AND | BPF_K: /* ALU64_IMM */
663 case BPF_ALU | BPF_LSH | BPF_K: /* ALU64_IMM */
664 case BPF_ALU | BPF_RSH | BPF_K: /* ALU64_IMM */
665 case BPF_ALU | BPF_XOR | BPF_K: /* ALU64_IMM */
666 case BPF_ALU | BPF_ARSH | BPF_K: /* ALU64_IMM */
667 r = gen_imm_insn(insn, ctx, this_idx);
671 case BPF_ALU64 | BPF_MUL | BPF_K: /* ALU64_IMM */
672 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
675 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
676 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
677 if (insn->imm == 1) /* Mult by 1 is a nop */
679 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
680 emit_instr(ctx, dmultu, MIPS_R_AT, dst);
681 emit_instr(ctx, mflo, dst);
683 case BPF_ALU64 | BPF_NEG | BPF_K: /* ALU64_IMM */
684 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
687 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
688 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
689 emit_instr(ctx, dsubu, dst, MIPS_R_ZERO, dst);
691 case BPF_ALU | BPF_MUL | BPF_K: /* ALU_IMM */
692 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
695 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
696 if (td == REG_64BIT) {
698 emit_instr(ctx, sll, dst, dst, 0);
700 if (insn->imm == 1) /* Mult by 1 is a nop */
702 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
703 emit_instr(ctx, multu, dst, MIPS_R_AT);
704 emit_instr(ctx, mflo, dst);
706 case BPF_ALU | BPF_NEG | BPF_K: /* ALU_IMM */
707 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
710 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
711 if (td == REG_64BIT) {
713 emit_instr(ctx, sll, dst, dst, 0);
715 emit_instr(ctx, subu, dst, MIPS_R_ZERO, dst);
717 case BPF_ALU | BPF_DIV | BPF_K: /* ALU_IMM */
718 case BPF_ALU | BPF_MOD | BPF_K: /* ALU_IMM */
721 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
724 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
727 emit_instr(ctx, sll, dst, dst, 0);
728 if (insn->imm == 1) {
729 /* div by 1 is a nop, mod by 1 is zero */
730 if (bpf_op == BPF_MOD)
731 emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO);
734 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
735 emit_instr(ctx, divu, dst, MIPS_R_AT);
736 if (bpf_op == BPF_DIV)
737 emit_instr(ctx, mflo, dst);
739 emit_instr(ctx, mfhi, dst);
741 case BPF_ALU64 | BPF_DIV | BPF_K: /* ALU_IMM */
742 case BPF_ALU64 | BPF_MOD | BPF_K: /* ALU_IMM */
745 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
748 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
749 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
750 if (insn->imm == 1) {
751 /* div by 1 is a nop, mod by 1 is zero */
752 if (bpf_op == BPF_MOD)
753 emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO);
756 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
757 emit_instr(ctx, ddivu, dst, MIPS_R_AT);
758 if (bpf_op == BPF_DIV)
759 emit_instr(ctx, mflo, dst);
761 emit_instr(ctx, mfhi, dst);
763 case BPF_ALU64 | BPF_MOV | BPF_X: /* ALU64_REG */
764 case BPF_ALU64 | BPF_ADD | BPF_X: /* ALU64_REG */
765 case BPF_ALU64 | BPF_SUB | BPF_X: /* ALU64_REG */
766 case BPF_ALU64 | BPF_XOR | BPF_X: /* ALU64_REG */
767 case BPF_ALU64 | BPF_OR | BPF_X: /* ALU64_REG */
768 case BPF_ALU64 | BPF_AND | BPF_X: /* ALU64_REG */
769 case BPF_ALU64 | BPF_MUL | BPF_X: /* ALU64_REG */
770 case BPF_ALU64 | BPF_DIV | BPF_X: /* ALU64_REG */
771 case BPF_ALU64 | BPF_MOD | BPF_X: /* ALU64_REG */
772 case BPF_ALU64 | BPF_LSH | BPF_X: /* ALU64_REG */
773 case BPF_ALU64 | BPF_RSH | BPF_X: /* ALU64_REG */
774 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ALU64_REG */
775 src = ebpf_to_mips_reg(ctx, insn, src_reg);
776 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
777 if (src < 0 || dst < 0)
779 if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT)
780 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
782 if (insn->src_reg == BPF_REG_10) {
783 if (bpf_op == BPF_MOV) {
784 emit_instr(ctx, daddiu, dst, MIPS_R_SP, MAX_BPF_STACK);
787 emit_instr(ctx, daddiu, MIPS_R_AT, MIPS_R_SP, MAX_BPF_STACK);
790 } else if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
791 int tmp_reg = MIPS_R_AT;
793 if (bpf_op == BPF_MOV) {
797 emit_instr(ctx, daddu, tmp_reg, src, MIPS_R_ZERO);
798 emit_instr(ctx, dinsu, tmp_reg, MIPS_R_ZERO, 32, 32);
804 emit_instr(ctx, daddu, dst, src, MIPS_R_ZERO);
807 emit_instr(ctx, daddu, dst, dst, src);
810 emit_instr(ctx, dsubu, dst, dst, src);
813 emit_instr(ctx, xor, dst, dst, src);
816 emit_instr(ctx, or, dst, dst, src);
819 emit_instr(ctx, and, dst, dst, src);
822 emit_instr(ctx, dmultu, dst, src);
823 emit_instr(ctx, mflo, dst);
827 emit_instr(ctx, ddivu, dst, src);
828 if (bpf_op == BPF_DIV)
829 emit_instr(ctx, mflo, dst);
831 emit_instr(ctx, mfhi, dst);
834 emit_instr(ctx, dsllv, dst, dst, src);
837 emit_instr(ctx, dsrlv, dst, dst, src);
840 emit_instr(ctx, dsrav, dst, dst, src);
843 pr_err("ALU64_REG NOT HANDLED\n");
847 case BPF_ALU | BPF_MOV | BPF_X: /* ALU_REG */
848 case BPF_ALU | BPF_ADD | BPF_X: /* ALU_REG */
849 case BPF_ALU | BPF_SUB | BPF_X: /* ALU_REG */
850 case BPF_ALU | BPF_XOR | BPF_X: /* ALU_REG */
851 case BPF_ALU | BPF_OR | BPF_X: /* ALU_REG */
852 case BPF_ALU | BPF_AND | BPF_X: /* ALU_REG */
853 case BPF_ALU | BPF_MUL | BPF_X: /* ALU_REG */
854 case BPF_ALU | BPF_DIV | BPF_X: /* ALU_REG */
855 case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */
856 case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */
857 case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */
858 case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */
859 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
860 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
861 if (src < 0 || dst < 0)
863 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
864 if (td == REG_64BIT) {
866 emit_instr(ctx, sll, dst, dst, 0);
869 ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
870 if (ts == REG_64BIT) {
871 int tmp_reg = MIPS_R_AT;
873 if (bpf_op == BPF_MOV) {
878 emit_instr(ctx, sll, tmp_reg, src, 0);
884 emit_instr(ctx, addu, dst, src, MIPS_R_ZERO);
887 emit_instr(ctx, addu, dst, dst, src);
890 emit_instr(ctx, subu, dst, dst, src);
893 emit_instr(ctx, xor, dst, dst, src);
896 emit_instr(ctx, or, dst, dst, src);
899 emit_instr(ctx, and, dst, dst, src);
902 emit_instr(ctx, mul, dst, dst, src);
906 emit_instr(ctx, divu, dst, src);
907 if (bpf_op == BPF_DIV)
908 emit_instr(ctx, mflo, dst);
910 emit_instr(ctx, mfhi, dst);
913 emit_instr(ctx, sllv, dst, dst, src);
916 emit_instr(ctx, srlv, dst, dst, src);
919 emit_instr(ctx, srav, dst, dst, src);
922 pr_err("ALU_REG NOT HANDLED\n");
926 case BPF_JMP | BPF_EXIT:
927 if (this_idx + 1 < exit_idx) {
928 b_off = b_imm(exit_idx, ctx);
929 if (is_bad_offset(b_off))
931 emit_instr(ctx, beq, MIPS_R_ZERO, MIPS_R_ZERO, b_off);
932 emit_instr(ctx, nop);
935 case BPF_JMP | BPF_JEQ | BPF_K: /* JMP_IMM */
936 case BPF_JMP | BPF_JNE | BPF_K: /* JMP_IMM */
937 cmp_eq = (bpf_op == BPF_JEQ);
938 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
941 if (insn->imm == 0) {
944 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
948 case BPF_JMP | BPF_JEQ | BPF_X: /* JMP_REG */
949 case BPF_JMP | BPF_JNE | BPF_X:
950 case BPF_JMP | BPF_JSLT | BPF_X:
951 case BPF_JMP | BPF_JSLE | BPF_X:
952 case BPF_JMP | BPF_JSGT | BPF_X:
953 case BPF_JMP | BPF_JSGE | BPF_X:
954 case BPF_JMP | BPF_JLT | BPF_X:
955 case BPF_JMP | BPF_JLE | BPF_X:
956 case BPF_JMP | BPF_JGT | BPF_X:
957 case BPF_JMP | BPF_JGE | BPF_X:
958 case BPF_JMP | BPF_JSET | BPF_X:
959 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
960 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
961 if (src < 0 || dst < 0)
963 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
964 ts = get_reg_val_type(ctx, this_idx, insn->src_reg);
965 if (td == REG_32BIT && ts != REG_32BIT) {
966 emit_instr(ctx, sll, MIPS_R_AT, src, 0);
968 } else if (ts == REG_32BIT && td != REG_32BIT) {
969 emit_instr(ctx, sll, MIPS_R_AT, dst, 0);
972 if (bpf_op == BPF_JSET) {
973 emit_instr(ctx, and, MIPS_R_AT, dst, src);
977 } else if (bpf_op == BPF_JSGT || bpf_op == BPF_JSLE) {
978 emit_instr(ctx, dsubu, MIPS_R_AT, dst, src);
979 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
980 b_off = b_imm(exit_idx, ctx);
981 if (is_bad_offset(b_off))
983 if (bpf_op == BPF_JSGT)
984 emit_instr(ctx, blez, MIPS_R_AT, b_off);
986 emit_instr(ctx, bgtz, MIPS_R_AT, b_off);
987 emit_instr(ctx, nop);
988 return 2; /* We consumed the exit. */
990 b_off = b_imm(this_idx + insn->off + 1, ctx);
991 if (is_bad_offset(b_off))
993 if (bpf_op == BPF_JSGT)
994 emit_instr(ctx, bgtz, MIPS_R_AT, b_off);
996 emit_instr(ctx, blez, MIPS_R_AT, b_off);
997 emit_instr(ctx, nop);
999 } else if (bpf_op == BPF_JSGE || bpf_op == BPF_JSLT) {
1000 emit_instr(ctx, slt, MIPS_R_AT, dst, src);
1001 cmp_eq = bpf_op == BPF_JSGE;
1004 } else if (bpf_op == BPF_JGT || bpf_op == BPF_JLE) {
1005 /* dst or src could be AT */
1006 emit_instr(ctx, dsubu, MIPS_R_T8, dst, src);
1007 emit_instr(ctx, sltu, MIPS_R_AT, dst, src);
1008 /* SP known to be non-zero, movz becomes boolean not */
1009 emit_instr(ctx, movz, MIPS_R_T9, MIPS_R_SP, MIPS_R_T8);
1010 emit_instr(ctx, movn, MIPS_R_T9, MIPS_R_ZERO, MIPS_R_T8);
1011 emit_instr(ctx, or, MIPS_R_AT, MIPS_R_T9, MIPS_R_AT);
1012 cmp_eq = bpf_op == BPF_JGT;
1015 } else if (bpf_op == BPF_JGE || bpf_op == BPF_JLT) {
1016 emit_instr(ctx, sltu, MIPS_R_AT, dst, src);
1017 cmp_eq = bpf_op == BPF_JGE;
1020 } else { /* JNE/JEQ case */
1021 cmp_eq = (bpf_op == BPF_JEQ);
1025 * If the next insn is EXIT and we are jumping arround
1026 * only it, invert the sense of the compare and
1027 * conditionally jump to the exit. Poor man's branch
1030 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1031 b_off = b_imm(exit_idx, ctx);
1032 if (is_bad_offset(b_off)) {
1033 target = j_target(ctx, exit_idx);
1034 if (target == (unsigned int)-1)
1038 if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) {
1039 ctx->offsets[this_idx] |= OFFSETS_B_CONV;
1040 ctx->long_b_conversion = 1;
1045 emit_instr(ctx, bne, dst, src, b_off);
1047 emit_instr(ctx, beq, dst, src, b_off);
1048 emit_instr(ctx, nop);
1049 if (ctx->offsets[this_idx] & OFFSETS_B_CONV) {
1050 emit_instr(ctx, j, target);
1051 emit_instr(ctx, nop);
1053 return 2; /* We consumed the exit. */
1055 b_off = b_imm(this_idx + insn->off + 1, ctx);
1056 if (is_bad_offset(b_off)) {
1057 target = j_target(ctx, this_idx + insn->off + 1);
1058 if (target == (unsigned int)-1)
1062 if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) {
1063 ctx->offsets[this_idx] |= OFFSETS_B_CONV;
1064 ctx->long_b_conversion = 1;
1069 emit_instr(ctx, beq, dst, src, b_off);
1071 emit_instr(ctx, bne, dst, src, b_off);
1072 emit_instr(ctx, nop);
1073 if (ctx->offsets[this_idx] & OFFSETS_B_CONV) {
1074 emit_instr(ctx, j, target);
1075 emit_instr(ctx, nop);
1078 case BPF_JMP | BPF_JSGT | BPF_K: /* JMP_IMM */
1079 case BPF_JMP | BPF_JSGE | BPF_K: /* JMP_IMM */
1080 case BPF_JMP | BPF_JSLT | BPF_K: /* JMP_IMM */
1081 case BPF_JMP | BPF_JSLE | BPF_K: /* JMP_IMM */
1082 cmp_eq = (bpf_op == BPF_JSGE);
1083 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1087 if (insn->imm == 0) {
1088 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1089 b_off = b_imm(exit_idx, ctx);
1090 if (is_bad_offset(b_off))
1094 emit_instr(ctx, blez, dst, b_off);
1097 emit_instr(ctx, bltz, dst, b_off);
1100 emit_instr(ctx, bgez, dst, b_off);
1103 emit_instr(ctx, bgtz, dst, b_off);
1106 emit_instr(ctx, nop);
1107 return 2; /* We consumed the exit. */
1109 b_off = b_imm(this_idx + insn->off + 1, ctx);
1110 if (is_bad_offset(b_off))
1114 emit_instr(ctx, bgtz, dst, b_off);
1117 emit_instr(ctx, bgez, dst, b_off);
1120 emit_instr(ctx, bltz, dst, b_off);
1123 emit_instr(ctx, blez, dst, b_off);
1126 emit_instr(ctx, nop);
1130 * only "LT" compare available, so we must use imm + 1
1131 * to generate "GT" and imm -1 to generate LE
1133 if (bpf_op == BPF_JSGT)
1134 t64s = insn->imm + 1;
1135 else if (bpf_op == BPF_JSLE)
1136 t64s = insn->imm + 1;
1140 cmp_eq = bpf_op == BPF_JSGT || bpf_op == BPF_JSGE;
1141 if (t64s >= S16_MIN && t64s <= S16_MAX) {
1142 emit_instr(ctx, slti, MIPS_R_AT, dst, (int)t64s);
1147 emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s);
1148 emit_instr(ctx, slt, MIPS_R_AT, dst, MIPS_R_AT);
1153 case BPF_JMP | BPF_JGT | BPF_K:
1154 case BPF_JMP | BPF_JGE | BPF_K:
1155 case BPF_JMP | BPF_JLT | BPF_K:
1156 case BPF_JMP | BPF_JLE | BPF_K:
1157 cmp_eq = (bpf_op == BPF_JGE);
1158 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1162 * only "LT" compare available, so we must use imm + 1
1163 * to generate "GT" and imm -1 to generate LE
1165 if (bpf_op == BPF_JGT)
1166 t64s = (u64)(u32)(insn->imm) + 1;
1167 else if (bpf_op == BPF_JLE)
1168 t64s = (u64)(u32)(insn->imm) + 1;
1170 t64s = (u64)(u32)(insn->imm);
1172 cmp_eq = bpf_op == BPF_JGT || bpf_op == BPF_JGE;
1174 emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s);
1175 emit_instr(ctx, sltu, MIPS_R_AT, dst, MIPS_R_AT);
1180 case BPF_JMP | BPF_JSET | BPF_K: /* JMP_IMM */
1181 dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok);
1185 if (ctx->use_bbit_insns && hweight32((u32)insn->imm) == 1) {
1186 if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) {
1187 b_off = b_imm(exit_idx, ctx);
1188 if (is_bad_offset(b_off))
1190 emit_instr(ctx, bbit0, dst, ffs((u32)insn->imm) - 1, b_off);
1191 emit_instr(ctx, nop);
1192 return 2; /* We consumed the exit. */
1194 b_off = b_imm(this_idx + insn->off + 1, ctx);
1195 if (is_bad_offset(b_off))
1197 emit_instr(ctx, bbit1, dst, ffs((u32)insn->imm) - 1, b_off);
1198 emit_instr(ctx, nop);
1201 t64 = (u32)insn->imm;
1202 emit_const_to_reg(ctx, MIPS_R_AT, t64);
1203 emit_instr(ctx, and, MIPS_R_AT, dst, MIPS_R_AT);
1209 case BPF_JMP | BPF_JA:
1211 * Prefer relative branch for easier debugging, but
1212 * fall back if needed.
1214 b_off = b_imm(this_idx + insn->off + 1, ctx);
1215 if (is_bad_offset(b_off)) {
1216 target = j_target(ctx, this_idx + insn->off + 1);
1217 if (target == (unsigned int)-1)
1219 emit_instr(ctx, j, target);
1221 emit_instr(ctx, b, b_off);
1223 emit_instr(ctx, nop);
1225 case BPF_LD | BPF_DW | BPF_IMM:
1226 if (insn->src_reg != 0)
1228 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1231 t64 = ((u64)(u32)insn->imm) | ((u64)(insn + 1)->imm << 32);
1232 emit_const_to_reg(ctx, dst, t64);
1233 return 2; /* Double slot insn */
1235 case BPF_JMP | BPF_CALL:
1236 ctx->flags |= EBPF_SAVE_RA;
1237 t64s = (s64)insn->imm + (s64)__bpf_call_base;
1238 emit_const_to_reg(ctx, MIPS_R_T9, (u64)t64s);
1239 emit_instr(ctx, jalr, MIPS_R_RA, MIPS_R_T9);
1241 emit_instr(ctx, nop);
1244 case BPF_JMP | BPF_TAIL_CALL:
1245 if (emit_bpf_tail_call(ctx, this_idx))
1249 case BPF_ALU | BPF_END | BPF_FROM_BE:
1250 case BPF_ALU | BPF_END | BPF_FROM_LE:
1251 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1254 td = get_reg_val_type(ctx, this_idx, insn->dst_reg);
1255 if (insn->imm == 64 && td == REG_32BIT)
1256 emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);
1258 if (insn->imm != 64 && td == REG_64BIT) {
1260 emit_instr(ctx, sll, dst, dst, 0);
1264 need_swap = (BPF_SRC(insn->code) == BPF_FROM_LE);
1266 need_swap = (BPF_SRC(insn->code) == BPF_FROM_BE);
1268 if (insn->imm == 16) {
1270 emit_instr(ctx, wsbh, dst, dst);
1271 emit_instr(ctx, andi, dst, dst, 0xffff);
1272 } else if (insn->imm == 32) {
1274 emit_instr(ctx, wsbh, dst, dst);
1275 emit_instr(ctx, rotr, dst, dst, 16);
1277 } else { /* 64-bit*/
1279 emit_instr(ctx, dsbh, dst, dst);
1280 emit_instr(ctx, dshd, dst, dst);
1285 case BPF_ST | BPF_B | BPF_MEM:
1286 case BPF_ST | BPF_H | BPF_MEM:
1287 case BPF_ST | BPF_W | BPF_MEM:
1288 case BPF_ST | BPF_DW | BPF_MEM:
1289 if (insn->dst_reg == BPF_REG_10) {
1290 ctx->flags |= EBPF_SEEN_FP;
1292 mem_off = insn->off + MAX_BPF_STACK;
1294 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1297 mem_off = insn->off;
1299 gen_imm_to_reg(insn, MIPS_R_AT, ctx);
1300 switch (BPF_SIZE(insn->code)) {
1302 emit_instr(ctx, sb, MIPS_R_AT, mem_off, dst);
1305 emit_instr(ctx, sh, MIPS_R_AT, mem_off, dst);
1308 emit_instr(ctx, sw, MIPS_R_AT, mem_off, dst);
1311 emit_instr(ctx, sd, MIPS_R_AT, mem_off, dst);
1316 case BPF_LDX | BPF_B | BPF_MEM:
1317 case BPF_LDX | BPF_H | BPF_MEM:
1318 case BPF_LDX | BPF_W | BPF_MEM:
1319 case BPF_LDX | BPF_DW | BPF_MEM:
1320 if (insn->src_reg == BPF_REG_10) {
1321 ctx->flags |= EBPF_SEEN_FP;
1323 mem_off = insn->off + MAX_BPF_STACK;
1325 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
1328 mem_off = insn->off;
1330 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1333 switch (BPF_SIZE(insn->code)) {
1335 emit_instr(ctx, lbu, dst, mem_off, src);
1338 emit_instr(ctx, lhu, dst, mem_off, src);
1341 emit_instr(ctx, lw, dst, mem_off, src);
1344 emit_instr(ctx, ld, dst, mem_off, src);
1349 case BPF_STX | BPF_B | BPF_MEM:
1350 case BPF_STX | BPF_H | BPF_MEM:
1351 case BPF_STX | BPF_W | BPF_MEM:
1352 case BPF_STX | BPF_DW | BPF_MEM:
1353 case BPF_STX | BPF_W | BPF_XADD:
1354 case BPF_STX | BPF_DW | BPF_XADD:
1355 if (insn->dst_reg == BPF_REG_10) {
1356 ctx->flags |= EBPF_SEEN_FP;
1358 mem_off = insn->off + MAX_BPF_STACK;
1360 dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
1363 mem_off = insn->off;
1365 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
1368 if (BPF_MODE(insn->code) == BPF_XADD) {
1369 switch (BPF_SIZE(insn->code)) {
1371 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1372 emit_instr(ctx, sll, MIPS_R_AT, src, 0);
1375 emit_instr(ctx, ll, MIPS_R_T8, mem_off, dst);
1376 emit_instr(ctx, addu, MIPS_R_T8, MIPS_R_T8, src);
1377 emit_instr(ctx, sc, MIPS_R_T8, mem_off, dst);
1379 * On failure back up to LL (-4
1380 * instructions of 4 bytes each
1382 emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4);
1383 emit_instr(ctx, nop);
1386 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1387 emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO);
1388 emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32);
1391 emit_instr(ctx, lld, MIPS_R_T8, mem_off, dst);
1392 emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, src);
1393 emit_instr(ctx, scd, MIPS_R_T8, mem_off, dst);
1394 emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4);
1395 emit_instr(ctx, nop);
1398 } else { /* BPF_MEM */
1399 switch (BPF_SIZE(insn->code)) {
1401 emit_instr(ctx, sb, src, mem_off, dst);
1404 emit_instr(ctx, sh, src, mem_off, dst);
1407 emit_instr(ctx, sw, src, mem_off, dst);
1410 if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) {
1411 emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO);
1412 emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32);
1415 emit_instr(ctx, sd, src, mem_off, dst);
1422 pr_err("NOT HANDLED %d - (%02x)\n",
1423 this_idx, (unsigned int)insn->code);
1429 #define RVT_VISITED_MASK 0xc000000000000000ull
1430 #define RVT_FALL_THROUGH 0x4000000000000000ull
1431 #define RVT_BRANCH_TAKEN 0x8000000000000000ull
1432 #define RVT_DONE (RVT_FALL_THROUGH | RVT_BRANCH_TAKEN)
1434 static int build_int_body(struct jit_ctx *ctx)
1436 const struct bpf_prog *prog = ctx->skf;
1437 const struct bpf_insn *insn;
1440 for (i = 0; i < prog->len; ) {
1441 insn = prog->insnsi + i;
1442 if ((ctx->reg_val_types[i] & RVT_VISITED_MASK) == 0) {
1443 /* dead instruction, don't emit it. */
1448 if (ctx->target == NULL)
1449 ctx->offsets[i] = (ctx->offsets[i] & OFFSETS_B_CONV) | (ctx->idx * 4);
1451 r = build_one_insn(insn, ctx, i, prog->len);
1456 /* epilogue offset */
1457 if (ctx->target == NULL)
1458 ctx->offsets[i] = ctx->idx * 4;
1461 * All exits have an offset of the epilogue, some offsets may
1462 * not have been set due to banch-around threading, so set
1465 if (ctx->target == NULL)
1466 for (i = 0; i < prog->len; i++) {
1467 insn = prog->insnsi + i;
1468 if (insn->code == (BPF_JMP | BPF_EXIT))
1469 ctx->offsets[i] = ctx->idx * 4;
1474 /* return the last idx processed, or negative for error */
1475 static int reg_val_propagate_range(struct jit_ctx *ctx, u64 initial_rvt,
1476 int start_idx, bool follow_taken)
1478 const struct bpf_prog *prog = ctx->skf;
1479 const struct bpf_insn *insn;
1480 u64 exit_rvt = initial_rvt;
1481 u64 *rvt = ctx->reg_val_types;
1485 for (idx = start_idx; idx < prog->len; idx++) {
1486 rvt[idx] = (rvt[idx] & RVT_VISITED_MASK) | exit_rvt;
1487 insn = prog->insnsi + idx;
1488 switch (BPF_CLASS(insn->code)) {
1490 switch (BPF_OP(insn->code)) {
1502 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1505 if (BPF_SRC(insn->code)) {
1506 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1508 /* IMM to REG move*/
1510 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1512 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1516 if (insn->imm == 64)
1517 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1518 else if (insn->imm == 32)
1519 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1520 else /* insn->imm == 16 */
1521 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1524 rvt[idx] |= RVT_DONE;
1527 switch (BPF_OP(insn->code)) {
1529 if (BPF_SRC(insn->code)) {
1530 /* REG to REG move*/
1531 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1533 /* IMM to REG move*/
1535 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1537 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT);
1541 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1543 rvt[idx] |= RVT_DONE;
1546 switch (BPF_SIZE(insn->code)) {
1548 if (BPF_MODE(insn->code) == BPF_IMM) {
1551 val = (s64)((u32)insn->imm | ((u64)(insn + 1)->imm << 32));
1552 if (val > 0 && val <= S32_MAX)
1553 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1554 else if (val >= S32_MIN && val <= S32_MAX)
1555 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT);
1557 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1558 rvt[idx] |= RVT_DONE;
1561 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1566 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1569 if (BPF_MODE(insn->code) == BPF_IMM)
1570 set_reg_val_type(&exit_rvt, insn->dst_reg,
1571 insn->imm >= 0 ? REG_32BIT_POS : REG_32BIT);
1573 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1576 rvt[idx] |= RVT_DONE;
1579 switch (BPF_SIZE(insn->code)) {
1581 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT);
1585 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS);
1588 set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT);
1591 rvt[idx] |= RVT_DONE;
1594 switch (BPF_OP(insn->code)) {
1596 rvt[idx] = RVT_DONE | exit_rvt;
1597 rvt[prog->len] = exit_rvt;
1600 rvt[idx] |= RVT_DONE;
1615 rvt[idx] |= RVT_BRANCH_TAKEN;
1617 follow_taken = false;
1619 rvt[idx] |= RVT_FALL_THROUGH;
1623 set_reg_val_type(&exit_rvt, BPF_REG_0, REG_64BIT);
1624 /* Upon call return, argument registers are clobbered. */
1625 for (reg = BPF_REG_0; reg <= BPF_REG_5; reg++)
1626 set_reg_val_type(&exit_rvt, reg, REG_64BIT);
1628 rvt[idx] |= RVT_DONE;
1631 WARN(1, "Unhandled BPF_JMP case.\n");
1632 rvt[idx] |= RVT_DONE;
1637 rvt[idx] |= RVT_DONE;
1645 * Track the value range (i.e. 32-bit vs. 64-bit) of each register at
1646 * each eBPF insn. This allows unneeded sign and zero extension
1647 * operations to be omitted.
1649 * Doesn't handle yet confluence of control paths with conflicting
1650 * ranges, but it is good enough for most sane code.
1652 static int reg_val_propagate(struct jit_ctx *ctx)
1654 const struct bpf_prog *prog = ctx->skf;
1660 * 11 registers * 3 bits/reg leaves top bits free for other
1661 * uses. Bit-62..63 used to see if we have visited an insn.
1665 /* Upon entry, argument registers are 64-bit. */
1666 for (reg = BPF_REG_1; reg <= BPF_REG_5; reg++)
1667 set_reg_val_type(&exit_rvt, reg, REG_64BIT);
1670 * First follow all conditional branches on the fall-through
1671 * edge of control flow..
1673 reg_val_propagate_range(ctx, exit_rvt, 0, false);
1676 * Then repeatedly find the first conditional branch where
1677 * both edges of control flow have not been taken, and follow
1678 * the branch taken edge. We will end up restarting the
1679 * search once per conditional branch insn.
1681 for (i = 0; i < prog->len; i++) {
1682 u64 rvt = ctx->reg_val_types[i];
1684 if ((rvt & RVT_VISITED_MASK) == RVT_DONE ||
1685 (rvt & RVT_VISITED_MASK) == 0)
1687 if ((rvt & RVT_VISITED_MASK) == RVT_FALL_THROUGH) {
1688 reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, true);
1689 } else { /* RVT_BRANCH_TAKEN */
1690 WARN(1, "Unexpected RVT_BRANCH_TAKEN case.\n");
1691 reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, false);
1693 goto restart_search;
1696 * Eventually all conditional branches have been followed on
1697 * both branches and we are done. Any insn that has not been
1698 * visited at this point is dead.
1704 static void jit_fill_hole(void *area, unsigned int size)
1708 /* We are guaranteed to have aligned memory. */
1709 for (p = area; size >= sizeof(u32); size -= sizeof(u32))
1710 uasm_i_break(&p, BRK_BUG); /* Increments p */
1713 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1715 struct bpf_prog *orig_prog = prog;
1716 bool tmp_blinded = false;
1717 struct bpf_prog *tmp;
1718 struct bpf_binary_header *header = NULL;
1720 unsigned int image_size;
1723 if (!prog->jit_requested || !cpu_has_mips64r2)
1726 tmp = bpf_jit_blind_constants(prog);
1727 /* If blinding was requested and we failed during blinding,
1728 * we must fall back to the interpreter.
1737 memset(&ctx, 0, sizeof(ctx));
1740 switch (current_cpu_type()) {
1741 case CPU_CAVIUM_OCTEON:
1742 case CPU_CAVIUM_OCTEON_PLUS:
1743 case CPU_CAVIUM_OCTEON2:
1744 case CPU_CAVIUM_OCTEON3:
1745 ctx.use_bbit_insns = 1;
1748 ctx.use_bbit_insns = 0;
1752 ctx.offsets = kcalloc(prog->len + 1, sizeof(*ctx.offsets), GFP_KERNEL);
1753 if (ctx.offsets == NULL)
1756 ctx.reg_val_types = kcalloc(prog->len + 1, sizeof(*ctx.reg_val_types), GFP_KERNEL);
1757 if (ctx.reg_val_types == NULL)
1762 if (reg_val_propagate(&ctx))
1766 * First pass discovers used resources and instruction offsets
1767 * assuming short branches are used.
1769 if (build_int_body(&ctx))
1773 * If no calls are made (EBPF_SAVE_RA), then tail call count
1774 * in $v1, else we must save in n$s4.
1776 if (ctx.flags & EBPF_SEEN_TC) {
1777 if (ctx.flags & EBPF_SAVE_RA)
1778 ctx.flags |= EBPF_SAVE_S4;
1780 ctx.flags |= EBPF_TCC_IN_V1;
1784 * Second pass generates offsets, if any branches are out of
1785 * range a jump-around long sequence is generated, and we have
1786 * to try again from the beginning to generate the new
1787 * offsets. This is done until no additional conversions are
1792 ctx.gen_b_offsets = 1;
1793 ctx.long_b_conversion = 0;
1794 if (gen_int_prologue(&ctx))
1796 if (build_int_body(&ctx))
1798 if (build_int_epilogue(&ctx, MIPS_R_RA))
1800 } while (ctx.long_b_conversion);
1802 image_size = 4 * ctx.idx;
1804 header = bpf_jit_binary_alloc(image_size, &image_ptr,
1805 sizeof(u32), jit_fill_hole);
1809 ctx.target = (u32 *)image_ptr;
1811 /* Third pass generates the code */
1813 if (gen_int_prologue(&ctx))
1815 if (build_int_body(&ctx))
1817 if (build_int_epilogue(&ctx, MIPS_R_RA))
1820 /* Update the icache */
1821 flush_icache_range((unsigned long)ctx.target,
1822 (unsigned long)(ctx.target + ctx.idx * sizeof(u32)));
1824 if (bpf_jit_enable > 1)
1826 bpf_jit_dump(prog->len, image_size, 2, ctx.target);
1828 bpf_jit_binary_lock_ro(header);
1829 prog->bpf_func = (void *)ctx.target;
1831 prog->jited_len = image_size;
1834 bpf_jit_prog_release_other(prog, prog == orig_prog ?
1837 kfree(ctx.reg_val_types);
1844 bpf_jit_binary_free(header);