arch/mips/mti-malta/malta-setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Carsten Langgaard, carstenl@mips.com
   4  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
   5  * Copyright (C) 2008 Dmitri Vorobiev
   6  */
   7 #include <linux/cpu.h>
   8 #include <linux/init.h>
   9 #include <linux/sched.h>
  10 #include <linux/ioport.h>
  11 #include <linux/irq.h>
  12 #include <linux/of_fdt.h>
  13 #include <linux/pci.h>
  14 #include <linux/screen_info.h>
  15 #include <linux/time.h>
  16 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
  17
  18 #include <asm/fw/fw.h>
  19 #include <asm/mips-cps.h>
  20 #include <asm/mips-boards/generic.h>
  21 #include <asm/mips-boards/malta.h>
  22 #include <asm/mips-boards/maltaint.h>
  23 #include <asm/dma.h>
  24 #include <asm/prom.h>
  25 #include <asm/traps.h>
  26 #ifdef CONFIG_VT
  27 #include <linux/console.h>
  28 #endif
  29
  30 #define ROCIT_CONFIG_GEN0               0x1f403000
  31 #define  ROCIT_CONFIG_GEN0_PCI_IOCU     BIT(7)
  32
  33 static struct resource standard_io_resources[] = {
  34         {
  35                 .name = "dma1",
  36                 .start = 0x00,
  37                 .end = 0x1f,
  38                 .flags = IORESOURCE_IO | IORESOURCE_BUSY
  39         },
  40         {
  41                 .name = "timer",
  42                 .start = 0x40,
  43                 .end = 0x5f,
  44                 .flags = IORESOURCE_IO | IORESOURCE_BUSY
  45         },
  46         {
  47                 .name = "keyboard",
  48                 .start = 0x60,
  49                 .end = 0x6f,
  50                 .flags = IORESOURCE_IO | IORESOURCE_BUSY
  51         },
  52         {
  53                 .name = "dma page reg",
  54                 .start = 0x80,
  55                 .end = 0x8f,
  56                 .flags = IORESOURCE_IO | IORESOURCE_BUSY
  57         },
  58         {
  59                 .name = "dma2",
  60                 .start = 0xc0,
  61                 .end = 0xdf,
  62                 .flags = IORESOURCE_IO | IORESOURCE_BUSY
  63         },
  64 };
  65
  66 const char *get_system_type(void)
  67 {
  68         return "MIPS Malta";
  69 }
  70
  71 #ifdef CONFIG_BLK_DEV_FD
  72 static void __init fd_activate(void)
  73 {
  74         /*
  75          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  76          * Controller.
  77          * Done by YAMON 2.00 onwards
  78          */
  79         /* Entering config state. */
  80         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  81
  82         /* Activate floppy controller. */
  83         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
  84         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
  85         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
  86         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
  87
  88         /* Exit config state. */
  89         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
  90 }
  91 #endif
  92
  93 static void __init plat_setup_iocoherency(void)
  94 {
  95         u32 cfg;
  96
  97         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
  98                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
  99                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 100                         pr_info("Enabled Bonito CPU coherency\n");
 101                         dma_default_coherent = true;
 102                 }
 103                 if (strstr(fw_getcmdline(), "iobcuncached")) {
 104                         BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
 105                         BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 106                                 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 107                                   BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 108                         pr_info("Disabled Bonito IOBC coherency\n");
 109                 } else {
 110                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
 111                         BONITO_PCIMEMBASECFG |=
 112                                 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 113                                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 114                         pr_info("Enabled Bonito IOBC coherency\n");
 115                 }
 116         } else if (mips_cps_numiocu(0) != 0) {
 117                 /* Nothing special needs to be done to enable coherency */
 118                 pr_info("CMP IOCU detected\n");
 119                 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
 120                 if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
 121                         dma_default_coherent = true;
 122                 else
 123                         pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
 124         }
 125
 126         if (dma_default_coherent)
 127                 pr_info("Hardware DMA cache coherency enabled\n");
 128         else
 129                 pr_info("Software DMA cache coherency enabled\n");
 130 }
 131
 132 static void __init pci_clock_check(void)
 133 {
 134         unsigned int __iomem *jmpr_p =
 135                 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
 136         int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
 137         static const int pciclocks[] __initconst = {
 138                 33, 20, 25, 30, 12, 16, 37, 10
 139         };
 140         int pciclock = pciclocks[jmpr];
 141         char *optptr, *argptr = fw_getcmdline();
 142
 143         /*
 144          * If user passed a pci_clock= option, don't tack on another one
 145          */
 146         optptr = strstr(argptr, "pci_clock=");
 147         if (optptr && (optptr == argptr || optptr[-1] == ' '))
 148                 return;
 149
 150         if (pciclock != 33) {
 151                 pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
 152                         pciclock);
 153                 argptr += strlen(argptr);
 154                 sprintf(argptr, " pci_clock=%d", pciclock);
 155                 if (pciclock < 20 || pciclock > 66)
 156                         pr_warn("WARNING: IDE timing calculations will be "
 157                                 "incorrect\n");
 158         }
 159 }
 160
 161 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 162 static void __init screen_info_setup(void)
 163 {
 164         screen_info = (struct screen_info) {
 165                 .orig_x = 0,
 166                 .orig_y = 25,
 167                 .ext_mem_k = 0,
 168                 .orig_video_page = 0,
 169                 .orig_video_mode = 0,
 170                 .orig_video_cols = 80,
 171                 .unused2 = 0,
 172                 .orig_video_ega_bx = 0,
 173                 .unused3 = 0,
 174                 .orig_video_lines = 25,
 175                 .orig_video_isVGA = VIDEO_TYPE_VGAC,
 176                 .orig_video_points = 16
 177         };
 178 }
 179 #endif
 180
 181 static void __init bonito_quirks_setup(void)
 182 {
 183         char *argptr;
 184
 185         argptr = fw_getcmdline();
 186         if (strstr(argptr, "debug")) {
 187                 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
 188                 pr_info("Enabled Bonito debug mode\n");
 189         } else
 190                 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
 191 }
 192
 193 void __init *plat_get_fdt(void)
 194 {
 195         return (void *)__dtb_start;
 196 }
 197
 198 void __init plat_mem_setup(void)
 199 {
 200         unsigned int i;
 201         void *fdt = plat_get_fdt();
 202
 203         fdt = malta_dt_shim(fdt);
 204         __dt_setup_arch(fdt);
 205
 206         if (IS_ENABLED(CONFIG_EVA))
 207                 /* EVA has already been configured in mach-malta/kernel-init.h */
 208                 pr_info("Enhanced Virtual Addressing (EVA) activated\n");
 209
 210         mips_pcibios_init();
 211
 212         /* Request I/O space for devices used on the Malta board. */
 213         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 214                 request_resource(&ioport_resource, standard_io_resources+i);
 215
 216         /*
 217          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
 218          */
 219         enable_dma(4);
 220
 221         if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
 222                 bonito_quirks_setup();
 223
 224         plat_setup_iocoherency();
 225
 226         pci_clock_check();
 227
 228 #ifdef CONFIG_BLK_DEV_FD
 229         fd_activate();
 230 #endif
 231
 232 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
 233         screen_info_setup();
 234 #endif
 235 }