arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
  14  */
  15
  16 enum fields {
  17         RS = 0x001,
  18         RT = 0x002,
  19         RD = 0x004,
  20         RE = 0x008,
  21         SIMM = 0x010,
  22         UIMM = 0x020,
  23         BIMM = 0x040,
  24         JIMM = 0x080,
  25         FUNC = 0x100,
  26         SET = 0x200,
  27         SCIMM = 0x400
  28 };
  29
  30 #define OP_MASK         0x3f
  31 #define OP_SH           26
  32 #define RD_MASK         0x1f
  33 #define RD_SH           11
  34 #define RE_MASK         0x1f
  35 #define RE_SH           6
  36 #define IMM_MASK        0xffff
  37 #define IMM_SH          0
  38 #define JIMM_MASK       0x3ffffff
  39 #define JIMM_SH         0
  40 #define FUNC_MASK       0x3f
  41 #define FUNC_SH         0
  42 #define SET_MASK        0x7
  43 #define SET_SH          0
  44
  45 enum opcode {
  46         insn_invalid,
  47         insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
  48         insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  49         insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
  50         insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
  51         insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
  52         insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
  53         insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
  54         insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
  55         insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
  56         insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,
  57         insn_wait, insn_xor, insn_xori, insn_yield,
  58 };
  59
  60 struct insn {
  61         enum opcode opcode;
  62         u32 match;
  63         enum fields fields;
  64 };
  65
  66 static inline u32 build_rs(u32 arg)
  67 {
  68         WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  69
  70         return (arg & RS_MASK) << RS_SH;
  71 }
  72
  73 static inline u32 build_rt(u32 arg)
  74 {
  75         WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  76
  77         return (arg & RT_MASK) << RT_SH;
  78 }
  79
  80 static inline u32 build_rd(u32 arg)
  81 {
  82         WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  83
  84         return (arg & RD_MASK) << RD_SH;
  85 }
  86
  87 static inline u32 build_re(u32 arg)
  88 {
  89         WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  90
  91         return (arg & RE_MASK) << RE_SH;
  92 }
  93
  94 static inline u32 build_simm(s32 arg)
  95 {
  96         WARN(arg > 0x7fff || arg < -0x8000,
  97              KERN_WARNING "Micro-assembler field overflow\n");
  98
  99         return arg & 0xffff;
 100 }
 101
 102 static inline u32 build_uimm(u32 arg)
 103 {
 104         WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 105
 106         return arg & IMM_MASK;
 107 }
 108
 109 static inline u32 build_scimm(u32 arg)
 110 {
 111         WARN(arg & ~SCIMM_MASK,
 112              KERN_WARNING "Micro-assembler field overflow\n");
 113
 114         return (arg & SCIMM_MASK) << SCIMM_SH;
 115 }
 116
 117 static inline u32 build_func(u32 arg)
 118 {
 119         WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 120
 121         return arg & FUNC_MASK;
 122 }
 123
 124 static inline u32 build_set(u32 arg)
 125 {
 126         WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 127
 128         return arg & SET_MASK;
 129 }
 130
 131 static void build_insn(u32 **buf, enum opcode opc, ...);
 132
 133 #define I_u1u2u3(op)                                    \
 134 Ip_u1u2u3(op)                                           \
 135 {                                                       \
 136         build_insn(buf, insn##op, a, b, c);             \
 137 }                                                       \
 138 UASM_EXPORT_SYMBOL(uasm_i##op);
 139
 140 #define I_u2u1u3(op)                                    \
 141 Ip_u2u1u3(op)                                           \
 142 {                                                       \
 143         build_insn(buf, insn##op, b, a, c);             \
 144 }                                                       \
 145 UASM_EXPORT_SYMBOL(uasm_i##op);
 146
 147 #define I_u3u2u1(op)                                    \
 148 Ip_u3u2u1(op)                                           \
 149 {                                                       \
 150         build_insn(buf, insn##op, c, b, a);             \
 151 }                                                       \
 152 UASM_EXPORT_SYMBOL(uasm_i##op);
 153
 154 #define I_u3u1u2(op)                                    \
 155 Ip_u3u1u2(op)                                           \
 156 {                                                       \
 157         build_insn(buf, insn##op, b, c, a);             \
 158 }                                                       \
 159 UASM_EXPORT_SYMBOL(uasm_i##op);
 160
 161 #define I_u1u2s3(op)                                    \
 162 Ip_u1u2s3(op)                                           \
 163 {                                                       \
 164         build_insn(buf, insn##op, a, b, c);             \
 165 }                                                       \
 166 UASM_EXPORT_SYMBOL(uasm_i##op);
 167
 168 #define I_u2s3u1(op)                                    \
 169 Ip_u2s3u1(op)                                           \
 170 {                                                       \
 171         build_insn(buf, insn##op, c, a, b);             \
 172 }                                                       \
 173 UASM_EXPORT_SYMBOL(uasm_i##op);
 174
 175 #define I_u2u1s3(op)                                    \
 176 Ip_u2u1s3(op)                                           \
 177 {                                                       \
 178         build_insn(buf, insn##op, b, a, c);             \
 179 }                                                       \
 180 UASM_EXPORT_SYMBOL(uasm_i##op);
 181
 182 #define I_u2u1msbu3(op)                                 \
 183 Ip_u2u1msbu3(op)                                        \
 184 {                                                       \
 185         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 186 }                                                       \
 187 UASM_EXPORT_SYMBOL(uasm_i##op);
 188
 189 #define I_u2u1msb32u3(op)                               \
 190 Ip_u2u1msbu3(op)                                        \
 191 {                                                       \
 192         build_insn(buf, insn##op, b, a, c+d-33, c);     \
 193 }                                                       \
 194 UASM_EXPORT_SYMBOL(uasm_i##op);
 195
 196 #define I_u2u1msbdu3(op)                                \
 197 Ip_u2u1msbu3(op)                                        \
 198 {                                                       \
 199         build_insn(buf, insn##op, b, a, d-1, c);        \
 200 }                                                       \
 201 UASM_EXPORT_SYMBOL(uasm_i##op);
 202
 203 #define I_u1u2(op)                                      \
 204 Ip_u1u2(op)                                             \
 205 {                                                       \
 206         build_insn(buf, insn##op, a, b);                \
 207 }                                                       \
 208 UASM_EXPORT_SYMBOL(uasm_i##op);
 209
 210 #define I_u2u1(op)                                      \
 211 Ip_u1u2(op)                                             \
 212 {                                                       \
 213         build_insn(buf, insn##op, b, a);                \
 214 }                                                       \
 215 UASM_EXPORT_SYMBOL(uasm_i##op);
 216
 217 #define I_u1s2(op)                                      \
 218 Ip_u1s2(op)                                             \
 219 {                                                       \
 220         build_insn(buf, insn##op, a, b);                \
 221 }                                                       \
 222 UASM_EXPORT_SYMBOL(uasm_i##op);
 223
 224 #define I_u1(op)                                        \
 225 Ip_u1(op)                                               \
 226 {                                                       \
 227         build_insn(buf, insn##op, a);                   \
 228 }                                                       \
 229 UASM_EXPORT_SYMBOL(uasm_i##op);
 230
 231 #define I_0(op)                                         \
 232 Ip_0(op)                                                \
 233 {                                                       \
 234         build_insn(buf, insn##op);                      \
 235 }                                                       \
 236 UASM_EXPORT_SYMBOL(uasm_i##op);
 237
 238 I_u2u1s3(_addiu)
 239 I_u3u1u2(_addu)
 240 I_u2u1u3(_andi)
 241 I_u3u1u2(_and)
 242 I_u1u2s3(_beq)
 243 I_u1u2s3(_beql)
 244 I_u1s2(_bgez)
 245 I_u1s2(_bgezl)
 246 I_u1s2(_bltz)
 247 I_u1s2(_bltzl)
 248 I_u1u2s3(_bne)
 249 I_u2s3u1(_cache)
 250 I_u1u2u3(_dmfc0)
 251 I_u1u2u3(_dmtc0)
 252 I_u2u1s3(_daddiu)
 253 I_u3u1u2(_daddu)
 254 I_u2u1u3(_dsll)
 255 I_u2u1u3(_dsll32)
 256 I_u2u1u3(_dsra)
 257 I_u2u1u3(_dsrl)
 258 I_u2u1u3(_dsrl32)
 259 I_u2u1u3(_drotr)
 260 I_u2u1u3(_drotr32)
 261 I_u3u1u2(_dsubu)
 262 I_0(_eret)
 263 I_u2u1msbdu3(_ext)
 264 I_u2u1msbu3(_ins)
 265 I_u1(_j)
 266 I_u1(_jal)
 267 I_u2u1(_jalr)
 268 I_u1(_jr)
 269 I_u2s3u1(_ld)
 270 I_u2s3u1(_ll)
 271 I_u2s3u1(_lld)
 272 I_u1s2(_lui)
 273 I_u2s3u1(_lw)
 274 I_u1u2u3(_mfc0)
 275 I_u1u2u3(_mtc0)
 276 I_u2u1u3(_ori)
 277 I_u3u1u2(_or)
 278 I_0(_rfe)
 279 I_u2s3u1(_sc)
 280 I_u2s3u1(_scd)
 281 I_u2s3u1(_sd)
 282 I_u2u1u3(_sll)
 283 I_u2u1u3(_sra)
 284 I_u2u1u3(_srl)
 285 I_u2u1u3(_rotr)
 286 I_u3u1u2(_subu)
 287 I_u2s3u1(_sw)
 288 I_u1(_sync)
 289 I_0(_tlbp)
 290 I_0(_tlbr)
 291 I_0(_tlbwi)
 292 I_0(_tlbwr)
 293 I_u1(_wait);
 294 I_u3u1u2(_xor)
 295 I_u2u1u3(_xori)
 296 I_u2u1(_yield)
 297 I_u2u1msbu3(_dins);
 298 I_u2u1msb32u3(_dinsm);
 299 I_u1(_syscall);
 300 I_u1u2s3(_bbit0);
 301 I_u1u2s3(_bbit1);
 302 I_u3u1u2(_lwx)
 303 I_u3u1u2(_ldx)
 304
 305 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 306 #include <asm/octeon/octeon.h>
 307 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
 308                             unsigned int c)
 309 {
 310         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
 311                 /*
 312                  * As per erratum Core-14449, replace prefetches 0-4,
 313                  * 6-24 with 'pref 28'.
 314                  */
 315                 build_insn(buf, insn_pref, c, 28, b);
 316         else
 317                 build_insn(buf, insn_pref, c, a, b);
 318 }
 319 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
 320 #else
 321 I_u2s3u1(_pref)
 322 #endif
 323
 324 /* Handle labels. */
 325 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
 326 {
 327         (*lab)->addr = addr;
 328         (*lab)->lab = lid;
 329         (*lab)++;
 330 }
 331 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
 332
 333 int ISAFUNC(uasm_in_compat_space_p)(long addr)
 334 {
 335         /* Is this address in 32bit compat space? */
 336 #ifdef CONFIG_64BIT
 337         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 338 #else
 339         return 1;
 340 #endif
 341 }
 342 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
 343
 344 static int uasm_rel_highest(long val)
 345 {
 346 #ifdef CONFIG_64BIT
 347         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 348 #else
 349         return 0;
 350 #endif
 351 }
 352
 353 static int uasm_rel_higher(long val)
 354 {
 355 #ifdef CONFIG_64BIT
 356         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 357 #else
 358         return 0;
 359 #endif
 360 }
 361
 362 int ISAFUNC(uasm_rel_hi)(long val)
 363 {
 364         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 365 }
 366 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
 367
 368 int ISAFUNC(uasm_rel_lo)(long val)
 369 {
 370         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 371 }
 372 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
 373
 374 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
 375 {
 376         if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
 377                 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
 378                 if (uasm_rel_higher(addr))
 379                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
 380                 if (ISAFUNC(uasm_rel_hi(addr))) {
 381                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 382                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 383                                         ISAFUNC(uasm_rel_hi)(addr));
 384                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 385                 } else
 386                         ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
 387         } else
 388                 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
 389 }
 390 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
 391
 392 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
 393 {
 394         ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
 395         if (ISAFUNC(uasm_rel_lo(addr))) {
 396                 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
 397                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 398                                         ISAFUNC(uasm_rel_lo(addr)));
 399                 else
 400                         ISAFUNC(uasm_i_addiu)(buf, rs, rs,
 401                                         ISAFUNC(uasm_rel_lo(addr)));
 402         }
 403 }
 404 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
 405
 406 /* Handle relocations. */
 407 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
 408 {
 409         (*rel)->addr = addr;
 410         (*rel)->type = R_MIPS_PC16;
 411         (*rel)->lab = lid;
 412         (*rel)++;
 413 }
 414 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
 415
 416 static inline void __resolve_relocs(struct uasm_reloc *rel,
 417                                     struct uasm_label *lab);
 418
 419 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
 420                                   struct uasm_label *lab)
 421 {
 422         struct uasm_label *l;
 423
 424         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 425                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 426                         if (rel->lab == l->lab)
 427                                 __resolve_relocs(rel, l);
 428 }
 429 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
 430
 431 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
 432                                long off)
 433 {
 434         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 435                 if (rel->addr >= first && rel->addr < end)
 436                         rel->addr += off;
 437 }
 438 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
 439
 440 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
 441                                long off)
 442 {
 443         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 444                 if (lab->addr >= first && lab->addr < end)
 445                         lab->addr += off;
 446 }
 447 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
 448
 449 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
 450                                 u32 *first, u32 *end, u32 *target)
 451 {
 452         long off = (long)(target - first);
 453
 454         memcpy(target, first, (end - first) * sizeof(u32));
 455
 456         ISAFUNC(uasm_move_relocs(rel, first, end, off));
 457         ISAFUNC(uasm_move_labels(lab, first, end, off));
 458 }
 459 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
 460
 461 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
 462 {
 463         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 464                 if (rel->addr == addr
 465                     && (rel->type == R_MIPS_PC16
 466                         || rel->type == R_MIPS_26))
 467                         return 1;
 468         }
 469
 470         return 0;
 471 }
 472 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
 473
 474 /* Convenience functions for labeled branches. */
 475 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 476                            int lid)
 477 {
 478         uasm_r_mips_pc16(r, *p, lid);
 479         ISAFUNC(uasm_i_bltz)(p, reg, 0);
 480 }
 481 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
 482
 483 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
 484 {
 485         uasm_r_mips_pc16(r, *p, lid);
 486         ISAFUNC(uasm_i_b)(p, 0);
 487 }
 488 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
 489
 490 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
 491                           unsigned int r2, int lid)
 492 {
 493         uasm_r_mips_pc16(r, *p, lid);
 494         ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
 495 }
 496 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
 497
 498 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 499                            int lid)
 500 {
 501         uasm_r_mips_pc16(r, *p, lid);
 502         ISAFUNC(uasm_i_beqz)(p, reg, 0);
 503 }
 504 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
 505
 506 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 507                             int lid)
 508 {
 509         uasm_r_mips_pc16(r, *p, lid);
 510         ISAFUNC(uasm_i_beqzl)(p, reg, 0);
 511 }
 512 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
 513
 514 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 515                           unsigned int reg2, int lid)
 516 {
 517         uasm_r_mips_pc16(r, *p, lid);
 518         ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
 519 }
 520 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
 521
 522 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 523                            int lid)
 524 {
 525         uasm_r_mips_pc16(r, *p, lid);
 526         ISAFUNC(uasm_i_bnez)(p, reg, 0);
 527 }
 528 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
 529
 530 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 531                             int lid)
 532 {
 533         uasm_r_mips_pc16(r, *p, lid);
 534         ISAFUNC(uasm_i_bgezl)(p, reg, 0);
 535 }
 536 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
 537
 538 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 539                            int lid)
 540 {
 541         uasm_r_mips_pc16(r, *p, lid);
 542         ISAFUNC(uasm_i_bgez)(p, reg, 0);
 543 }
 544 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
 545
 546 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 547                             unsigned int bit, int lid)
 548 {
 549         uasm_r_mips_pc16(r, *p, lid);
 550         ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
 551 }
 552 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
 553
 554 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 555                             unsigned int bit, int lid)
 556 {
 557         uasm_r_mips_pc16(r, *p, lid);
 558         ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
 559 }
 560 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));