2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/cpu_pm.h>
12 #include <linux/init.h>
13 #include <linux/sched.h>
14 #include <linux/smp.h>
16 #include <linux/hugetlb.h>
17 #include <linux/export.h>
20 #include <asm/cpu-type.h>
21 #include <asm/bootinfo.h>
22 #include <asm/hazards.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
26 #include <asm/tlbmisc.h>
28 extern void build_tlb_refill_handler(void);
31 * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has
32 * a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. Unfortunately,
33 * itlb/dtlb are not totally transparent to software.
35 static inline void flush_micro_tlb(void)
37 switch (current_cpu_type()) {
39 write_c0_diag(LOONGSON_DIAG_ITLB);
42 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
49 static inline void flush_micro_tlb_vm(struct vm_area_struct *vma)
51 if (vma->vm_flags & VM_EXEC)
55 void local_flush_tlb_all(void)
58 unsigned long old_ctx;
59 int entry, ftlbhighset;
61 local_irq_save(flags);
62 /* Save old context and create impossible VPN2 value */
63 old_ctx = read_c0_entryhi();
68 entry = num_wired_entries();
72 * If there are any wired entries, fall back to iterating
74 if (cpu_has_tlbinv && !entry) {
75 if (current_cpu_data.tlbsizevtlb) {
78 tlbinvf(); /* invalidate VTLB */
80 ftlbhighset = current_cpu_data.tlbsizevtlb +
81 current_cpu_data.tlbsizeftlbsets;
82 for (entry = current_cpu_data.tlbsizevtlb;
85 write_c0_index(entry);
87 tlbinvf(); /* invalidate one FTLB set */
90 while (entry < current_cpu_data.tlbsize) {
91 /* Make sure all entries differ. */
92 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
93 write_c0_index(entry);
100 write_c0_entryhi(old_ctx);
103 local_irq_restore(flags);
105 EXPORT_SYMBOL(local_flush_tlb_all);
107 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
110 struct mm_struct *mm = vma->vm_mm;
111 int cpu = smp_processor_id();
113 if (cpu_context(cpu, mm) != 0) {
114 unsigned long size, flags;
116 local_irq_save(flags);
117 start = round_down(start, PAGE_SIZE << 1);
118 end = round_up(end, PAGE_SIZE << 1);
119 size = (end - start) >> (PAGE_SHIFT + 1);
120 if (size <= (current_cpu_data.tlbsizeftlbsets ?
121 current_cpu_data.tlbsize / 8 :
122 current_cpu_data.tlbsize / 2)) {
123 unsigned long old_entryhi, uninitialized_var(old_mmid);
124 int newpid = cpu_asid(cpu, mm);
126 old_entryhi = read_c0_entryhi();
128 old_mmid = read_c0_memorymapid();
129 write_c0_memorymapid(newpid);
133 while (start < end) {
137 write_c0_entryhi(start);
139 write_c0_entryhi(start | newpid);
140 start += (PAGE_SIZE << 1);
144 idx = read_c0_index();
145 write_c0_entrylo0(0);
146 write_c0_entrylo1(0);
149 /* Make sure all entries differ. */
150 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
155 write_c0_entryhi(old_entryhi);
157 write_c0_memorymapid(old_mmid);
160 drop_mmu_context(mm);
163 local_irq_restore(flags);
167 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
169 unsigned long size, flags;
171 local_irq_save(flags);
172 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
173 size = (size + 1) >> 1;
174 if (size <= (current_cpu_data.tlbsizeftlbsets ?
175 current_cpu_data.tlbsize / 8 :
176 current_cpu_data.tlbsize / 2)) {
177 int pid = read_c0_entryhi();
179 start &= (PAGE_MASK << 1);
180 end += ((PAGE_SIZE << 1) - 1);
181 end &= (PAGE_MASK << 1);
184 while (start < end) {
187 write_c0_entryhi(start);
188 start += (PAGE_SIZE << 1);
192 idx = read_c0_index();
193 write_c0_entrylo0(0);
194 write_c0_entrylo1(0);
197 /* Make sure all entries differ. */
198 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
203 write_c0_entryhi(pid);
206 local_flush_tlb_all();
209 local_irq_restore(flags);
212 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
214 int cpu = smp_processor_id();
216 if (cpu_context(cpu, vma->vm_mm) != 0) {
217 unsigned long uninitialized_var(old_mmid);
218 unsigned long flags, old_entryhi;
221 page &= (PAGE_MASK << 1);
222 local_irq_save(flags);
223 old_entryhi = read_c0_entryhi();
226 old_mmid = read_c0_memorymapid();
227 write_c0_entryhi(page);
228 write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm));
230 write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm));
235 idx = read_c0_index();
236 write_c0_entrylo0(0);
237 write_c0_entrylo1(0);
240 /* Make sure all entries differ. */
241 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
247 write_c0_entryhi(old_entryhi);
249 write_c0_memorymapid(old_mmid);
251 flush_micro_tlb_vm(vma);
252 local_irq_restore(flags);
257 * This one is only used for pages with the global bit set so we don't care
258 * much about the ASID.
260 void local_flush_tlb_one(unsigned long page)
265 local_irq_save(flags);
266 oldpid = read_c0_entryhi();
268 page &= (PAGE_MASK << 1);
269 write_c0_entryhi(page);
273 idx = read_c0_index();
274 write_c0_entrylo0(0);
275 write_c0_entrylo1(0);
277 /* Make sure all entries differ. */
278 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
283 write_c0_entryhi(oldpid);
286 local_irq_restore(flags);
290 * We will need multiple versions of update_mmu_cache(), one that just
291 * updates the TLB with the new pte(s), and another which also checks
292 * for the R4k "end of page" hardware bug and does the needy.
294 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
304 * Handle debugger faulting in for debugee.
306 if (current->active_mm != vma->vm_mm)
309 local_irq_save(flags);
312 address &= (PAGE_MASK << 1);
314 write_c0_entryhi(address);
316 pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data);
317 write_c0_entryhi(address | pid);
319 pgdp = pgd_offset(vma->vm_mm, address);
323 pudp = pud_offset(pgdp, address);
324 pmdp = pmd_offset(pudp, address);
325 idx = read_c0_index();
326 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
327 /* this could be a huge page */
328 if (pmd_huge(*pmdp)) {
330 write_c0_pagemask(PM_HUGE_MASK);
331 ptep = (pte_t *)pmdp;
332 lo = pte_to_entrylo(pte_val(*ptep));
333 write_c0_entrylo0(lo);
334 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
342 write_c0_pagemask(PM_DEFAULT_MASK);
346 ptep = pte_offset_map(pmdp, address);
348 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
350 write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));
352 writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);
354 write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));
356 writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);
358 write_c0_entrylo0(ptep->pte_high);
360 write_c0_entrylo1(ptep->pte_high);
363 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
364 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
374 flush_micro_tlb_vm(vma);
375 local_irq_restore(flags);
378 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
379 unsigned long entryhi, unsigned long pagemask)
382 panic("Broken for XPA kernels");
384 unsigned int uninitialized_var(old_mmid);
387 unsigned long old_pagemask;
388 unsigned long old_ctx;
390 local_irq_save(flags);
392 old_mmid = read_c0_memorymapid();
393 write_c0_memorymapid(MMID_KERNEL_WIRED);
395 /* Save old context and create impossible VPN2 value */
396 old_ctx = read_c0_entryhi();
398 old_pagemask = read_c0_pagemask();
399 wired = num_wired_entries();
400 write_c0_wired(wired + 1);
401 write_c0_index(wired);
402 tlbw_use_hazard(); /* What is the hazard here? */
403 write_c0_pagemask(pagemask);
404 write_c0_entryhi(entryhi);
405 write_c0_entrylo0(entrylo0);
406 write_c0_entrylo1(entrylo1);
411 write_c0_entryhi(old_ctx);
413 write_c0_memorymapid(old_mmid);
414 tlbw_use_hazard(); /* What is the hazard here? */
416 write_c0_pagemask(old_pagemask);
417 local_flush_tlb_all();
418 local_irq_restore(flags);
422 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
424 int has_transparent_hugepage(void)
426 static unsigned int mask = -1;
428 if (mask == -1) { /* first call comes during __init */
431 local_irq_save(flags);
432 write_c0_pagemask(PM_HUGE_MASK);
433 back_to_back_c0_hazard();
434 mask = read_c0_pagemask();
435 write_c0_pagemask(PM_DEFAULT_MASK);
436 local_irq_restore(flags);
438 return mask == PM_HUGE_MASK;
441 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
444 * Used for loading TLB entries before trap_init() has started, when we
445 * don't actually want to add a wired entry which remains throughout the
446 * lifetime of the system
451 __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
452 unsigned long entryhi, unsigned long pagemask)
457 unsigned long old_pagemask;
458 unsigned long old_ctx;
460 local_irq_save(flags);
461 /* Save old context and create impossible VPN2 value */
463 old_ctx = read_c0_entryhi();
464 old_pagemask = read_c0_pagemask();
465 wired = num_wired_entries();
466 if (--temp_tlb_entry < wired) {
468 "No TLB space left for add_temporary_entry\n");
473 write_c0_index(temp_tlb_entry);
474 write_c0_pagemask(pagemask);
475 write_c0_entryhi(entryhi);
476 write_c0_entrylo0(entrylo0);
477 write_c0_entrylo1(entrylo1);
482 write_c0_entryhi(old_ctx);
483 write_c0_pagemask(old_pagemask);
486 local_irq_restore(flags);
491 static int __init set_ntlb(char *str)
493 get_option(&str, &ntlb);
497 __setup("ntlb=", set_ntlb);
500 * Configure TLB (for init or after a CPU has been powered off).
502 static void r4k_tlb_configure(void)
505 * You should never change this register:
506 * - On R4600 1.7 the tlbp never hits for pages smaller than
507 * the value in the c0_pagemask register.
508 * - The entire mm handling assumes the c0_pagemask register to
509 * be set to fixed-size pages.
511 write_c0_pagemask(PM_DEFAULT_MASK);
512 back_to_back_c0_hazard();
513 if (read_c0_pagemask() != PM_DEFAULT_MASK)
514 panic("MMU doesn't support PAGE_SIZE=0x%lx", PAGE_SIZE);
517 if (current_cpu_type() == CPU_R10000 ||
518 current_cpu_type() == CPU_R12000 ||
519 current_cpu_type() == CPU_R14000 ||
520 current_cpu_type() == CPU_R16000)
521 write_c0_framemask(0);
525 * Enable the no read, no exec bits, and enable large physical
529 set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
531 set_c0_pagegrain(PG_RIE | PG_XIE);
535 temp_tlb_entry = current_cpu_data.tlbsize - 1;
537 /* From this point on the ARC firmware is dead. */
538 local_flush_tlb_all();
540 /* Did I tell you that ARC SUCKS? */
548 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
549 int wired = current_cpu_data.tlbsize - ntlb;
550 write_c0_wired(wired);
551 write_c0_index(wired-1);
552 printk("Restricting TLB to %d entries\n", ntlb);
554 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
557 build_tlb_refill_handler();
560 static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd,
564 case CPU_PM_ENTER_FAILED:
573 static struct notifier_block r4k_tlb_pm_notifier_block = {
574 .notifier_call = r4k_tlb_pm_notifier,
577 static int __init r4k_tlb_init_pm(void)
579 return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block);
581 arch_initcall(r4k_tlb_init_pm);