2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/cpu_pm.h>
11 #include <linux/hardirq.h>
12 #include <linux/init.h>
13 #include <linux/highmem.h>
14 #include <linux/kernel.h>
15 #include <linux/linkage.h>
16 #include <linux/preempt.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
20 #include <linux/export.h>
21 #include <linux/bitops.h>
23 #include <asm/bcache.h>
24 #include <asm/bootinfo.h>
25 #include <asm/cache.h>
26 #include <asm/cacheops.h>
28 #include <asm/cpu-features.h>
29 #include <asm/cpu-type.h>
32 #include <asm/pgtable.h>
33 #include <asm/r4kcache.h>
34 #include <asm/sections.h>
35 #include <asm/mmu_context.h>
37 #include <asm/cacheflush.h> /* for run_uncached() */
38 #include <asm/traps.h>
39 #include <asm/dma-coherence.h>
40 #include <asm/mips-cps.h>
43 * Bits describing what cache ops an SMP callback function may perform.
45 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * active_mm must be checked before using user addresses, falling
48 * R4K_INDEX - Index based cache operations.
51 #define R4K_HIT BIT(0)
52 #define R4K_INDEX BIT(1)
55 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
56 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
58 * Decides whether a cache op needs to be performed on every core in the system.
59 * This may change depending on the @type of cache operation, as well as the set
60 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
61 * hotplug from changing the result.
63 * Returns: 1 if the cache operation @type should be done on every core in
65 * 0 if the cache operation @type is globalized and only needs to
66 * be performed on a simple CPU.
68 static inline bool r4k_op_needs_ipi(unsigned int type)
70 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
71 if (type == R4K_HIT && mips_cm_present())
75 * Hardware doesn't globalize the required cache ops, so SMP calls may
76 * be needed, but only if there are foreign CPUs (non-siblings with
79 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
81 return !cpumask_empty(&cpu_foreign_map[0]);
88 * Special Variant of smp_call_function for use by cache functions:
91 * o collapses to normal function call on UP kernels
92 * o collapses to normal function call on systems with a single shared
94 * o doesn't disable interrupts on the local CPU
96 static inline void r4k_on_each_cpu(unsigned int type,
97 void (*func)(void *info), void *info)
100 if (r4k_op_needs_ipi(type))
101 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
110 static unsigned long icache_size __read_mostly;
111 static unsigned long dcache_size __read_mostly;
112 static unsigned long vcache_size __read_mostly;
113 static unsigned long scache_size __read_mostly;
116 * Dummy cache handling routines for machines without boardcaches
118 static void cache_noop(void) {}
120 static struct bcache_ops no_sc_ops = {
121 .bc_enable = (void *)cache_noop,
122 .bc_disable = (void *)cache_noop,
123 .bc_wback_inv = (void *)cache_noop,
124 .bc_inv = (void *)cache_noop
127 struct bcache_ops *bcops = &no_sc_ops;
129 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
130 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
132 #define R4600_HIT_CACHEOP_WAR_IMPL \
134 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
135 *(volatile unsigned long *)CKSEG1; \
136 if (R4600_V1_HIT_CACHEOP_WAR) \
137 __asm__ __volatile__("nop;nop;nop;nop"); \
140 static void (*r4k_blast_dcache_page)(unsigned long addr);
142 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
144 R4600_HIT_CACHEOP_WAR_IMPL;
145 blast_dcache32_page(addr);
148 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
150 blast_dcache64_page(addr);
153 static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
155 blast_dcache128_page(addr);
158 static void r4k_blast_dcache_page_setup(void)
160 unsigned long dc_lsize = cpu_dcache_line_size();
164 r4k_blast_dcache_page = (void *)cache_noop;
167 r4k_blast_dcache_page = blast_dcache16_page;
170 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
173 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
176 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
184 #define r4k_blast_dcache_user_page r4k_blast_dcache_page
187 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
189 static void r4k_blast_dcache_user_page_setup(void)
191 unsigned long dc_lsize = cpu_dcache_line_size();
194 r4k_blast_dcache_user_page = (void *)cache_noop;
195 else if (dc_lsize == 16)
196 r4k_blast_dcache_user_page = blast_dcache16_user_page;
197 else if (dc_lsize == 32)
198 r4k_blast_dcache_user_page = blast_dcache32_user_page;
199 else if (dc_lsize == 64)
200 r4k_blast_dcache_user_page = blast_dcache64_user_page;
205 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
207 static void r4k_blast_dcache_page_indexed_setup(void)
209 unsigned long dc_lsize = cpu_dcache_line_size();
212 r4k_blast_dcache_page_indexed = (void *)cache_noop;
213 else if (dc_lsize == 16)
214 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
215 else if (dc_lsize == 32)
216 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
217 else if (dc_lsize == 64)
218 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
219 else if (dc_lsize == 128)
220 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
223 void (* r4k_blast_dcache)(void);
224 EXPORT_SYMBOL(r4k_blast_dcache);
226 static void r4k_blast_dcache_setup(void)
228 unsigned long dc_lsize = cpu_dcache_line_size();
231 r4k_blast_dcache = (void *)cache_noop;
232 else if (dc_lsize == 16)
233 r4k_blast_dcache = blast_dcache16;
234 else if (dc_lsize == 32)
235 r4k_blast_dcache = blast_dcache32;
236 else if (dc_lsize == 64)
237 r4k_blast_dcache = blast_dcache64;
238 else if (dc_lsize == 128)
239 r4k_blast_dcache = blast_dcache128;
242 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
243 #define JUMP_TO_ALIGN(order) \
244 __asm__ __volatile__( \
246 ".align\t" #order "\n\t" \
249 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
250 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
252 static inline void blast_r4600_v1_icache32(void)
256 local_irq_save(flags);
258 local_irq_restore(flags);
261 static inline void tx49_blast_icache32(void)
263 unsigned long start = INDEX_BASE;
264 unsigned long end = start + current_cpu_data.icache.waysize;
265 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
266 unsigned long ws_end = current_cpu_data.icache.ways <<
267 current_cpu_data.icache.waybit;
268 unsigned long ws, addr;
270 CACHE32_UNROLL32_ALIGN2;
271 /* I'm in even chunk. blast odd chunks */
272 for (ws = 0; ws < ws_end; ws += ws_inc)
273 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
274 cache32_unroll32(addr|ws, Index_Invalidate_I);
275 CACHE32_UNROLL32_ALIGN;
276 /* I'm in odd chunk. blast even chunks */
277 for (ws = 0; ws < ws_end; ws += ws_inc)
278 for (addr = start; addr < end; addr += 0x400 * 2)
279 cache32_unroll32(addr|ws, Index_Invalidate_I);
282 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
286 local_irq_save(flags);
287 blast_icache32_page_indexed(page);
288 local_irq_restore(flags);
291 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
293 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
294 unsigned long start = INDEX_BASE + (page & indexmask);
295 unsigned long end = start + PAGE_SIZE;
296 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
297 unsigned long ws_end = current_cpu_data.icache.ways <<
298 current_cpu_data.icache.waybit;
299 unsigned long ws, addr;
301 CACHE32_UNROLL32_ALIGN2;
302 /* I'm in even chunk. blast odd chunks */
303 for (ws = 0; ws < ws_end; ws += ws_inc)
304 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
305 cache32_unroll32(addr|ws, Index_Invalidate_I);
306 CACHE32_UNROLL32_ALIGN;
307 /* I'm in odd chunk. blast even chunks */
308 for (ws = 0; ws < ws_end; ws += ws_inc)
309 for (addr = start; addr < end; addr += 0x400 * 2)
310 cache32_unroll32(addr|ws, Index_Invalidate_I);
313 static void (* r4k_blast_icache_page)(unsigned long addr);
315 static void r4k_blast_icache_page_setup(void)
317 unsigned long ic_lsize = cpu_icache_line_size();
320 r4k_blast_icache_page = (void *)cache_noop;
321 else if (ic_lsize == 16)
322 r4k_blast_icache_page = blast_icache16_page;
323 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
324 r4k_blast_icache_page = loongson2_blast_icache32_page;
325 else if (ic_lsize == 32)
326 r4k_blast_icache_page = blast_icache32_page;
327 else if (ic_lsize == 64)
328 r4k_blast_icache_page = blast_icache64_page;
329 else if (ic_lsize == 128)
330 r4k_blast_icache_page = blast_icache128_page;
334 #define r4k_blast_icache_user_page r4k_blast_icache_page
337 static void (*r4k_blast_icache_user_page)(unsigned long addr);
339 static void r4k_blast_icache_user_page_setup(void)
341 unsigned long ic_lsize = cpu_icache_line_size();
344 r4k_blast_icache_user_page = (void *)cache_noop;
345 else if (ic_lsize == 16)
346 r4k_blast_icache_user_page = blast_icache16_user_page;
347 else if (ic_lsize == 32)
348 r4k_blast_icache_user_page = blast_icache32_user_page;
349 else if (ic_lsize == 64)
350 r4k_blast_icache_user_page = blast_icache64_user_page;
355 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
357 static void r4k_blast_icache_page_indexed_setup(void)
359 unsigned long ic_lsize = cpu_icache_line_size();
362 r4k_blast_icache_page_indexed = (void *)cache_noop;
363 else if (ic_lsize == 16)
364 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
365 else if (ic_lsize == 32) {
366 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
367 r4k_blast_icache_page_indexed =
368 blast_icache32_r4600_v1_page_indexed;
369 else if (TX49XX_ICACHE_INDEX_INV_WAR)
370 r4k_blast_icache_page_indexed =
371 tx49_blast_icache32_page_indexed;
372 else if (current_cpu_type() == CPU_LOONGSON2)
373 r4k_blast_icache_page_indexed =
374 loongson2_blast_icache32_page_indexed;
376 r4k_blast_icache_page_indexed =
377 blast_icache32_page_indexed;
378 } else if (ic_lsize == 64)
379 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
382 void (* r4k_blast_icache)(void);
383 EXPORT_SYMBOL(r4k_blast_icache);
385 static void r4k_blast_icache_setup(void)
387 unsigned long ic_lsize = cpu_icache_line_size();
390 r4k_blast_icache = (void *)cache_noop;
391 else if (ic_lsize == 16)
392 r4k_blast_icache = blast_icache16;
393 else if (ic_lsize == 32) {
394 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
395 r4k_blast_icache = blast_r4600_v1_icache32;
396 else if (TX49XX_ICACHE_INDEX_INV_WAR)
397 r4k_blast_icache = tx49_blast_icache32;
398 else if (current_cpu_type() == CPU_LOONGSON2)
399 r4k_blast_icache = loongson2_blast_icache32;
401 r4k_blast_icache = blast_icache32;
402 } else if (ic_lsize == 64)
403 r4k_blast_icache = blast_icache64;
404 else if (ic_lsize == 128)
405 r4k_blast_icache = blast_icache128;
408 static void (* r4k_blast_scache_page)(unsigned long addr);
410 static void r4k_blast_scache_page_setup(void)
412 unsigned long sc_lsize = cpu_scache_line_size();
414 if (scache_size == 0)
415 r4k_blast_scache_page = (void *)cache_noop;
416 else if (sc_lsize == 16)
417 r4k_blast_scache_page = blast_scache16_page;
418 else if (sc_lsize == 32)
419 r4k_blast_scache_page = blast_scache32_page;
420 else if (sc_lsize == 64)
421 r4k_blast_scache_page = blast_scache64_page;
422 else if (sc_lsize == 128)
423 r4k_blast_scache_page = blast_scache128_page;
426 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
428 static void r4k_blast_scache_page_indexed_setup(void)
430 unsigned long sc_lsize = cpu_scache_line_size();
432 if (scache_size == 0)
433 r4k_blast_scache_page_indexed = (void *)cache_noop;
434 else if (sc_lsize == 16)
435 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
436 else if (sc_lsize == 32)
437 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
438 else if (sc_lsize == 64)
439 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
440 else if (sc_lsize == 128)
441 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
444 static void (* r4k_blast_scache)(void);
446 static void r4k_blast_scache_setup(void)
448 unsigned long sc_lsize = cpu_scache_line_size();
450 if (scache_size == 0)
451 r4k_blast_scache = (void *)cache_noop;
452 else if (sc_lsize == 16)
453 r4k_blast_scache = blast_scache16;
454 else if (sc_lsize == 32)
455 r4k_blast_scache = blast_scache32;
456 else if (sc_lsize == 64)
457 r4k_blast_scache = blast_scache64;
458 else if (sc_lsize == 128)
459 r4k_blast_scache = blast_scache128;
462 static void (*r4k_blast_scache_node)(long node);
464 static void r4k_blast_scache_node_setup(void)
466 unsigned long sc_lsize = cpu_scache_line_size();
468 if (current_cpu_type() != CPU_LOONGSON3)
469 r4k_blast_scache_node = (void *)cache_noop;
470 else if (sc_lsize == 16)
471 r4k_blast_scache_node = blast_scache16_node;
472 else if (sc_lsize == 32)
473 r4k_blast_scache_node = blast_scache32_node;
474 else if (sc_lsize == 64)
475 r4k_blast_scache_node = blast_scache64_node;
476 else if (sc_lsize == 128)
477 r4k_blast_scache_node = blast_scache128_node;
480 static inline void local_r4k___flush_cache_all(void * args)
482 switch (current_cpu_type()) {
493 * These caches are inclusive caches, that is, if something
494 * is not cached in the S-cache, we know it also won't be
495 * in one of the primary caches.
501 /* Use get_ebase_cpunum() for both NUMA=y/n */
502 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
517 static void r4k___flush_cache_all(void)
519 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
523 * has_valid_asid() - Determine if an mm already has an ASID.
525 * @type: R4K_HIT or R4K_INDEX, type of cache op.
527 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
528 * of type @type within an r4k_on_each_cpu() call will affect. If
529 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
530 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
531 * will need to be checked.
533 * Must be called in non-preemptive context.
535 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
538 static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
541 const cpumask_t *mask = cpu_present_mask;
543 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
546 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
547 * each foreign core, so we only need to worry about siblings.
548 * Otherwise we need to worry about all present CPUs.
550 if (r4k_op_needs_ipi(type))
551 mask = &cpu_sibling_map[smp_processor_id()];
553 for_each_cpu(i, mask)
554 if (cpu_context(i, mm))
559 static void r4k__flush_cache_vmap(void)
564 static void r4k__flush_cache_vunmap(void)
570 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
571 * whole caches when vma is executable.
573 static inline void local_r4k_flush_cache_range(void * args)
575 struct vm_area_struct *vma = args;
576 int exec = vma->vm_flags & VM_EXEC;
578 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
582 * If dcache can alias, we must blast it since mapping is changing.
583 * If executable, we must ensure any dirty lines are written back far
584 * enough to be visible to icache.
586 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
588 /* If executable, blast stale lines from icache */
593 static void r4k_flush_cache_range(struct vm_area_struct *vma,
594 unsigned long start, unsigned long end)
596 int exec = vma->vm_flags & VM_EXEC;
598 if (cpu_has_dc_aliases || exec)
599 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
602 static inline void local_r4k_flush_cache_mm(void * args)
604 struct mm_struct *mm = args;
606 if (!has_valid_asid(mm, R4K_INDEX))
610 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
611 * only flush the primary caches but R1x000 behave sane ...
612 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
613 * caches, so we can bail out early.
615 if (current_cpu_type() == CPU_R4000SC ||
616 current_cpu_type() == CPU_R4000MC ||
617 current_cpu_type() == CPU_R4400SC ||
618 current_cpu_type() == CPU_R4400MC) {
626 static void r4k_flush_cache_mm(struct mm_struct *mm)
628 if (!cpu_has_dc_aliases)
631 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
634 struct flush_cache_page_args {
635 struct vm_area_struct *vma;
640 static inline void local_r4k_flush_cache_page(void *args)
642 struct flush_cache_page_args *fcp_args = args;
643 struct vm_area_struct *vma = fcp_args->vma;
644 unsigned long addr = fcp_args->addr;
645 struct page *page = pfn_to_page(fcp_args->pfn);
646 int exec = vma->vm_flags & VM_EXEC;
647 struct mm_struct *mm = vma->vm_mm;
648 int map_coherent = 0;
656 * If owns no valid ASID yet, cannot possibly have gotten
657 * this page into the cache.
659 if (!has_valid_asid(mm, R4K_HIT))
663 pgdp = pgd_offset(mm, addr);
664 pudp = pud_offset(pgdp, addr);
665 pmdp = pmd_offset(pudp, addr);
666 ptep = pte_offset(pmdp, addr);
669 * If the page isn't marked valid, the page cannot possibly be
672 if (!(pte_present(*ptep)))
675 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
679 * Use kmap_coherent or kmap_atomic to do flushes for
680 * another ASID than the current one.
682 map_coherent = (cpu_has_dc_aliases &&
683 page_mapcount(page) &&
684 !Page_dcache_dirty(page));
686 vaddr = kmap_coherent(page, addr);
688 vaddr = kmap_atomic(page);
689 addr = (unsigned long)vaddr;
692 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
693 vaddr ? r4k_blast_dcache_page(addr) :
694 r4k_blast_dcache_user_page(addr);
695 if (exec && !cpu_icache_snoops_remote_store)
696 r4k_blast_scache_page(addr);
699 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
700 drop_mmu_context(mm);
702 vaddr ? r4k_blast_icache_page(addr) :
703 r4k_blast_icache_user_page(addr);
710 kunmap_atomic(vaddr);
714 static void r4k_flush_cache_page(struct vm_area_struct *vma,
715 unsigned long addr, unsigned long pfn)
717 struct flush_cache_page_args args;
723 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
726 static inline void local_r4k_flush_data_cache_page(void * addr)
728 r4k_blast_dcache_page((unsigned long) addr);
731 static void r4k_flush_data_cache_page(unsigned long addr)
734 local_r4k_flush_data_cache_page((void *)addr);
736 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
740 struct flush_icache_range_args {
747 static inline void __local_r4k_flush_icache_range(unsigned long start,
752 if (!cpu_has_ic_fills_f_dc) {
753 if (type == R4K_INDEX ||
754 (type & R4K_INDEX && end - start >= dcache_size)) {
757 R4600_HIT_CACHEOP_WAR_IMPL;
759 protected_blast_dcache_range(start, end);
761 blast_dcache_range(start, end);
765 if (type == R4K_INDEX ||
766 (type & R4K_INDEX && end - start > icache_size))
769 switch (boot_cpu_type()) {
771 protected_loongson2_blast_icache_range(start, end);
776 protected_blast_icache_range(start, end);
778 blast_icache_range(start, end);
784 static inline void local_r4k_flush_icache_range(unsigned long start,
787 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
790 static inline void local_r4k_flush_icache_user_range(unsigned long start,
793 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
796 static inline void local_r4k_flush_icache_range_ipi(void *args)
798 struct flush_icache_range_args *fir_args = args;
799 unsigned long start = fir_args->start;
800 unsigned long end = fir_args->end;
801 unsigned int type = fir_args->type;
802 bool user = fir_args->user;
804 __local_r4k_flush_icache_range(start, end, type, user);
807 static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
810 struct flush_icache_range_args args;
811 unsigned long size, cache_size;
815 args.type = R4K_HIT | R4K_INDEX;
819 * Indexed cache ops require an SMP call.
820 * Consider if that can or should be avoided.
823 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
825 * If address-based cache ops don't require an SMP call, then
826 * use them exclusively for small flushes.
829 cache_size = icache_size;
830 if (!cpu_has_ic_fills_f_dc) {
832 cache_size += dcache_size;
834 if (size <= cache_size)
835 args.type &= ~R4K_INDEX;
837 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
839 instruction_hazard();
842 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
844 return __r4k_flush_icache_range(start, end, false);
847 static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
849 return __r4k_flush_icache_range(start, end, true);
852 #ifdef CONFIG_DMA_NONCOHERENT
854 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
856 /* Catch bad driver code */
857 if (WARN_ON(size == 0))
861 if (cpu_has_inclusive_pcaches) {
862 if (size >= scache_size) {
863 if (current_cpu_type() != CPU_LOONGSON3)
866 r4k_blast_scache_node(pa_to_nid(addr));
868 blast_scache_range(addr, addr + size);
876 * Either no secondary cache or the available caches don't have the
877 * subset property so we have to flush the primary caches
879 * If we would need IPI to perform an INDEX-type operation, then
880 * we have to use the HIT-type alternative as IPI cannot be used
881 * here due to interrupts possibly being disabled.
883 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
886 R4600_HIT_CACHEOP_WAR_IMPL;
887 blast_dcache_range(addr, addr + size);
891 bc_wback_inv(addr, size);
895 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
897 /* Catch bad driver code */
898 if (WARN_ON(size == 0))
902 if (cpu_has_inclusive_pcaches) {
903 if (size >= scache_size) {
904 if (current_cpu_type() != CPU_LOONGSON3)
907 r4k_blast_scache_node(pa_to_nid(addr));
910 * There is no clearly documented alignment requirement
911 * for the cache instruction on MIPS processors and
912 * some processors, among them the RM5200 and RM7000
913 * QED processors will throw an address error for cache
914 * hit ops with insufficient alignment. Solved by
915 * aligning the address to cache line size.
917 blast_inv_scache_range(addr, addr + size);
924 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
927 R4600_HIT_CACHEOP_WAR_IMPL;
928 blast_inv_dcache_range(addr, addr + size);
935 #endif /* CONFIG_DMA_NONCOHERENT */
937 struct flush_cache_sigtramp_args {
938 struct mm_struct *mm;
944 * While we're protected against bad userland addresses we don't care
945 * very much about what happens in that case. Usually a segmentation
946 * fault will dump the process later on anyway ...
948 static void local_r4k_flush_cache_sigtramp(void *args)
950 struct flush_cache_sigtramp_args *fcs_args = args;
951 unsigned long addr = fcs_args->addr;
952 struct page *page = fcs_args->page;
953 struct mm_struct *mm = fcs_args->mm;
954 int map_coherent = 0;
957 unsigned long ic_lsize = cpu_icache_line_size();
958 unsigned long dc_lsize = cpu_dcache_line_size();
959 unsigned long sc_lsize = cpu_scache_line_size();
962 * If owns no valid ASID yet, cannot possibly have gotten
963 * this page into the cache.
965 if (!has_valid_asid(mm, R4K_HIT))
968 if (mm == current->active_mm) {
972 * Use kmap_coherent or kmap_atomic to do flushes for
973 * another ASID than the current one.
975 map_coherent = (cpu_has_dc_aliases &&
976 page_mapcount(page) &&
977 !Page_dcache_dirty(page));
979 vaddr = kmap_coherent(page, addr);
981 vaddr = kmap_atomic(page);
982 addr = (unsigned long)vaddr + (addr & ~PAGE_MASK);
985 R4600_HIT_CACHEOP_WAR_IMPL;
986 if (!cpu_has_ic_fills_f_dc) {
988 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
989 : protected_writeback_dcache_line(
990 addr & ~(dc_lsize - 1));
991 if (!cpu_icache_snoops_remote_store && scache_size)
992 vaddr ? flush_scache_line(addr & ~(sc_lsize - 1))
993 : protected_writeback_scache_line(
994 addr & ~(sc_lsize - 1));
997 vaddr ? flush_icache_line(addr & ~(ic_lsize - 1))
998 : protected_flush_icache_line(addr & ~(ic_lsize - 1));
1004 kunmap_atomic(vaddr);
1007 if (MIPS4K_ICACHE_REFILL_WAR) {
1008 __asm__ __volatile__ (
1011 ".set "MIPS_ISA_LEVEL"\n\t"
1018 "cache %0,($at)\n\t"
1023 : "i" (Hit_Invalidate_I));
1025 if (MIPS_CACHE_SYNC_WAR)
1026 __asm__ __volatile__ ("sync");
1029 static void r4k_flush_cache_sigtramp(unsigned long addr)
1031 struct flush_cache_sigtramp_args args;
1034 down_read(¤t->mm->mmap_sem);
1036 npages = get_user_pages_fast(addr, 1, 0, &args.page);
1040 args.mm = current->mm;
1043 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args);
1045 put_page(args.page);
1047 up_read(¤t->mm->mmap_sem);
1050 static void r4k_flush_icache_all(void)
1052 if (cpu_has_vtag_icache)
1056 struct flush_kernel_vmap_range_args {
1057 unsigned long vaddr;
1061 static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
1064 * Aliases only affect the primary caches so don't bother with
1065 * S-caches or T-caches.
1070 static inline void local_r4k_flush_kernel_vmap_range(void *args)
1072 struct flush_kernel_vmap_range_args *vmra = args;
1073 unsigned long vaddr = vmra->vaddr;
1074 int size = vmra->size;
1077 * Aliases only affect the primary caches so don't bother with
1078 * S-caches or T-caches.
1080 R4600_HIT_CACHEOP_WAR_IMPL;
1081 blast_dcache_range(vaddr, vaddr + size);
1084 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
1086 struct flush_kernel_vmap_range_args args;
1088 args.vaddr = (unsigned long) vaddr;
1091 if (size >= dcache_size)
1092 r4k_on_each_cpu(R4K_INDEX,
1093 local_r4k_flush_kernel_vmap_range_index, NULL);
1095 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
1099 static inline void rm7k_erratum31(void)
1101 const unsigned long ic_lsize = 32;
1104 /* RM7000 erratum #31. The icache is screwed at startup. */
1108 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
1109 __asm__ __volatile__ (
1111 ".set noreorder\n\t"
1113 "cache\t%1, 0(%0)\n\t"
1114 "cache\t%1, 0x1000(%0)\n\t"
1115 "cache\t%1, 0x2000(%0)\n\t"
1116 "cache\t%1, 0x3000(%0)\n\t"
1117 "cache\t%2, 0(%0)\n\t"
1118 "cache\t%2, 0x1000(%0)\n\t"
1119 "cache\t%2, 0x2000(%0)\n\t"
1120 "cache\t%2, 0x3000(%0)\n\t"
1121 "cache\t%1, 0(%0)\n\t"
1122 "cache\t%1, 0x1000(%0)\n\t"
1123 "cache\t%1, 0x2000(%0)\n\t"
1124 "cache\t%1, 0x3000(%0)\n\t"
1127 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
1131 static inline int alias_74k_erratum(struct cpuinfo_mips *c)
1133 unsigned int imp = c->processor_id & PRID_IMP_MASK;
1134 unsigned int rev = c->processor_id & PRID_REV_MASK;
1138 * Early versions of the 74K do not update the cache tags on a
1139 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
1140 * aliases. In this case it is better to treat the cache as always
1141 * having aliases. Also disable the synonym tag update feature
1142 * where available. In this case no opportunistic tag update will
1143 * happen where a load causes a virtual address miss but a physical
1144 * address hit during a D-cache look-up.
1148 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
1150 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
1151 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1153 case PRID_IMP_1074K:
1154 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
1156 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
1166 static void b5k_instruction_hazard(void)
1170 __asm__ __volatile__(
1171 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1172 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1173 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1174 " nop; nop; nop; nop; nop; nop; nop; nop\n"
1178 static char *way_string[] = { NULL, "direct mapped", "2-way",
1179 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
1180 "9-way", "10-way", "11-way", "12-way",
1181 "13-way", "14-way", "15-way", "16-way",
1184 static void probe_pcache(void)
1186 struct cpuinfo_mips *c = ¤t_cpu_data;
1187 unsigned int config = read_c0_config();
1188 unsigned int prid = read_c0_prid();
1189 int has_74k_erratum = 0;
1190 unsigned long config1;
1193 switch (current_cpu_type()) {
1194 case CPU_R4600: /* QED style two way caches? */
1198 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1199 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1201 c->icache.waybit = __ffs(icache_size/2);
1203 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1204 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1206 c->dcache.waybit= __ffs(dcache_size/2);
1208 c->options |= MIPS_CPU_CACHE_CDEX_P;
1213 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1214 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1216 c->icache.waybit= 0;
1218 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1219 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1221 c->dcache.waybit = 0;
1223 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1227 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1228 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1230 c->icache.waybit= 0;
1232 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1233 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1235 c->dcache.waybit = 0;
1237 c->options |= MIPS_CPU_CACHE_CDEX_P;
1238 c->options |= MIPS_CPU_PREFETCH;
1248 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1249 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1251 c->icache.waybit = 0; /* doesn't matter */
1253 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1254 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1256 c->dcache.waybit = 0; /* does not matter */
1258 c->options |= MIPS_CPU_CACHE_CDEX_P;
1265 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1266 c->icache.linesz = 64;
1268 c->icache.waybit = 0;
1270 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1271 c->dcache.linesz = 32;
1273 c->dcache.waybit = 0;
1275 c->options |= MIPS_CPU_PREFETCH;
1279 write_c0_config(config & ~VR41_CONF_P4K);
1282 /* Workaround for cache instruction bug of VR4131 */
1283 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1284 c->processor_id == 0x0c82U) {
1285 config |= 0x00400000U;
1286 if (c->processor_id == 0x0c80U)
1287 config |= VR41_CONF_BP;
1288 write_c0_config(config);
1290 c->options |= MIPS_CPU_CACHE_CDEX_P;
1292 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1293 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1295 c->icache.waybit = __ffs(icache_size/2);
1297 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1298 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1300 c->dcache.waybit = __ffs(dcache_size/2);
1309 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1310 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1312 c->icache.waybit = 0; /* doesn't matter */
1314 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1315 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1317 c->dcache.waybit = 0; /* does not matter */
1319 c->options |= MIPS_CPU_CACHE_CDEX_P;
1325 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1326 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1328 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1330 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1331 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1333 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1335 c->options |= MIPS_CPU_CACHE_CDEX_P;
1336 c->options |= MIPS_CPU_PREFETCH;
1340 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1341 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1346 c->icache.waybit = 0;
1348 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1349 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1354 c->dcache.waybit = 0;
1358 config1 = read_c0_config1();
1359 lsize = (config1 >> 19) & 7;
1361 c->icache.linesz = 2 << lsize;
1363 c->icache.linesz = 0;
1364 c->icache.sets = 64 << ((config1 >> 22) & 7);
1365 c->icache.ways = 1 + ((config1 >> 16) & 7);
1366 icache_size = c->icache.sets *
1369 c->icache.waybit = 0;
1371 lsize = (config1 >> 10) & 7;
1373 c->dcache.linesz = 2 << lsize;
1375 c->dcache.linesz = 0;
1376 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1377 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1378 dcache_size = c->dcache.sets *
1381 c->dcache.waybit = 0;
1382 if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)
1383 c->options |= MIPS_CPU_PREFETCH;
1386 case CPU_CAVIUM_OCTEON3:
1387 /* For now lie about the number of ways. */
1388 c->icache.linesz = 128;
1389 c->icache.sets = 16;
1391 c->icache.flags |= MIPS_CACHE_VTAG;
1392 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1394 c->dcache.linesz = 128;
1397 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1398 c->options |= MIPS_CPU_PREFETCH;
1402 if (!(config & MIPS_CONF_M))
1403 panic("Don't know how to probe P-caches on this cpu.");
1406 * So we seem to be a MIPS32 or MIPS64 CPU
1407 * So let's probe the I-cache ...
1409 config1 = read_c0_config1();
1411 lsize = (config1 >> 19) & 7;
1413 /* IL == 7 is reserved */
1415 panic("Invalid icache line size");
1417 c->icache.linesz = lsize ? 2 << lsize : 0;
1419 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1420 c->icache.ways = 1 + ((config1 >> 16) & 7);
1422 icache_size = c->icache.sets *
1425 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1427 if (config & MIPS_CONF_VI)
1428 c->icache.flags |= MIPS_CACHE_VTAG;
1431 * Now probe the MIPS32 / MIPS64 data cache.
1433 c->dcache.flags = 0;
1435 lsize = (config1 >> 10) & 7;
1437 /* DL == 7 is reserved */
1439 panic("Invalid dcache line size");
1441 c->dcache.linesz = lsize ? 2 << lsize : 0;
1443 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1444 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1446 dcache_size = c->dcache.sets *
1449 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1451 c->options |= MIPS_CPU_PREFETCH;
1456 * Processor configuration sanity check for the R4000SC erratum
1457 * #5. With page sizes larger than 32kB there is no possibility
1458 * to get a VCE exception anymore so we don't care about this
1459 * misconfiguration. The case is rather theoretical anyway;
1460 * presumably no vendor is shipping his hardware in the "bad"
1463 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1464 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1465 !(config & CONF_SC) && c->icache.linesz != 16 &&
1466 PAGE_SIZE <= 0x8000)
1467 panic("Improper R4000SC processor configuration detected");
1469 /* compute a couple of other cache variables */
1470 c->icache.waysize = icache_size / c->icache.ways;
1471 c->dcache.waysize = dcache_size / c->dcache.ways;
1473 c->icache.sets = c->icache.linesz ?
1474 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1475 c->dcache.sets = c->dcache.linesz ?
1476 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1479 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1480 * virtually indexed so normally would suffer from aliases. So
1481 * normally they'd suffer from aliases but magic in the hardware deals
1482 * with that for us so we don't need to take care ourselves.
1484 switch (current_cpu_type()) {
1492 c->dcache.flags |= MIPS_CACHE_PINDEX;
1503 has_74k_erratum = alias_74k_erratum(c);
1510 case CPU_INTERAPTIV:
1514 case CPU_QEMU_GENERIC:
1517 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1518 (c->icache.waysize > PAGE_SIZE))
1519 c->icache.flags |= MIPS_CACHE_ALIASES;
1520 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1522 * Effectively physically indexed dcache,
1523 * thus no virtual aliases.
1525 c->dcache.flags |= MIPS_CACHE_PINDEX;
1530 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1531 c->dcache.flags |= MIPS_CACHE_ALIASES;
1534 /* Physically indexed caches don't suffer from virtual aliasing */
1535 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1536 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1539 * In systems with CM the icache fills from L2 or closer caches, and
1540 * thus sees remote stores without needing to write them back any
1541 * further than that.
1543 if (mips_cm_present())
1544 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1546 switch (current_cpu_type()) {
1549 * Some older 20Kc chips doesn't have the 'VI' bit in
1550 * the config register.
1552 c->icache.flags |= MIPS_CACHE_VTAG;
1558 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1562 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1563 /* Cache aliases are handled in hardware; allow HIGHMEM */
1564 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1569 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1570 * one op will act on all 4 ways
1575 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1577 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1578 way_string[c->icache.ways], c->icache.linesz);
1580 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1581 dcache_size >> 10, way_string[c->dcache.ways],
1582 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1583 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1584 "cache aliases" : "no aliases",
1588 static void probe_vcache(void)
1590 struct cpuinfo_mips *c = ¤t_cpu_data;
1591 unsigned int config2, lsize;
1593 if (current_cpu_type() != CPU_LOONGSON3)
1596 config2 = read_c0_config2();
1597 if ((lsize = ((config2 >> 20) & 15)))
1598 c->vcache.linesz = 2 << lsize;
1600 c->vcache.linesz = lsize;
1602 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1603 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1605 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1607 c->vcache.waybit = 0;
1608 c->vcache.waysize = vcache_size / c->vcache.ways;
1610 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1611 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1615 * If you even _breathe_ on this function, look at the gcc output and make sure
1616 * it does not pop things on and off the stack for the cache sizing loop that
1617 * executes in KSEG1 space or else you will crash and burn badly. You have
1620 static int probe_scache(void)
1622 unsigned long flags, addr, begin, end, pow2;
1623 unsigned int config = read_c0_config();
1624 struct cpuinfo_mips *c = ¤t_cpu_data;
1626 if (config & CONF_SC)
1629 begin = (unsigned long) &_stext;
1630 begin &= ~((4 * 1024 * 1024) - 1);
1631 end = begin + (4 * 1024 * 1024);
1634 * This is such a bitch, you'd think they would make it easy to do
1635 * this. Away you daemons of stupidity!
1637 local_irq_save(flags);
1639 /* Fill each size-multiple cache line with a valid tag. */
1641 for (addr = begin; addr < end; addr = (begin + pow2)) {
1642 unsigned long *p = (unsigned long *) addr;
1643 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1647 /* Load first line with zero (therefore invalid) tag. */
1650 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1651 cache_op(Index_Store_Tag_I, begin);
1652 cache_op(Index_Store_Tag_D, begin);
1653 cache_op(Index_Store_Tag_SD, begin);
1655 /* Now search for the wrap around point. */
1656 pow2 = (128 * 1024);
1657 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1658 cache_op(Index_Load_Tag_SD, addr);
1659 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1660 if (!read_c0_taglo())
1664 local_irq_restore(flags);
1668 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1670 c->scache.waybit = 0; /* does not matter */
1675 static void __init loongson2_sc_init(void)
1677 struct cpuinfo_mips *c = ¤t_cpu_data;
1679 scache_size = 512*1024;
1680 c->scache.linesz = 32;
1682 c->scache.waybit = 0;
1683 c->scache.waysize = scache_size / (c->scache.ways);
1684 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1685 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1686 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1688 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1691 static void __init loongson3_sc_init(void)
1693 struct cpuinfo_mips *c = ¤t_cpu_data;
1694 unsigned int config2, lsize;
1696 config2 = read_c0_config2();
1697 lsize = (config2 >> 4) & 15;
1699 c->scache.linesz = 2 << lsize;
1701 c->scache.linesz = 0;
1702 c->scache.sets = 64 << ((config2 >> 8) & 15);
1703 c->scache.ways = 1 + (config2 & 15);
1705 scache_size = c->scache.sets *
1708 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1710 c->scache.waybit = 0;
1711 c->scache.waysize = scache_size / c->scache.ways;
1712 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1713 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1715 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1719 extern int r5k_sc_init(void);
1720 extern int rm7k_sc_init(void);
1721 extern int mips_sc_init(void);
1723 static void setup_scache(void)
1725 struct cpuinfo_mips *c = ¤t_cpu_data;
1726 unsigned int config = read_c0_config();
1730 * Do the probing thing on R4000SC and R4400SC processors. Other
1731 * processors don't have a S-cache that would be relevant to the
1732 * Linux memory management.
1734 switch (current_cpu_type()) {
1739 sc_present = run_uncached(probe_scache);
1741 c->options |= MIPS_CPU_CACHE_CDEX_S;
1748 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1749 c->scache.linesz = 64 << ((config >> 13) & 1);
1751 c->scache.waybit= 0;
1757 #ifdef CONFIG_R5000_CPU_SCACHE
1763 #ifdef CONFIG_RM7000_CPU_SCACHE
1769 loongson2_sc_init();
1773 loongson3_sc_init();
1776 case CPU_CAVIUM_OCTEON3:
1778 /* don't need to worry about L2, fully coherent */
1782 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1783 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1784 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1785 #ifdef CONFIG_MIPS_CPU_SCACHE
1786 if (mips_sc_init ()) {
1787 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1788 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1790 way_string[c->scache.ways], c->scache.linesz);
1793 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1794 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1804 /* compute a couple of other cache variables */
1805 c->scache.waysize = scache_size / c->scache.ways;
1807 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1809 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1810 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1812 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1815 void au1x00_fixup_config_od(void)
1818 * c0_config.od (bit 19) was write only (and read as 0)
1819 * on the early revisions of Alchemy SOCs. It disables the bus
1820 * transaction overlapping and needs to be set to fix various errata.
1822 switch (read_c0_prid()) {
1823 case 0x00030100: /* Au1000 DA */
1824 case 0x00030201: /* Au1000 HA */
1825 case 0x00030202: /* Au1000 HB */
1826 case 0x01030200: /* Au1500 AB */
1828 * Au1100 errata actually keeps silence about this bit, so we set it
1829 * just in case for those revisions that require it to be set according
1830 * to the (now gone) cpu table.
1832 case 0x02030200: /* Au1100 AB */
1833 case 0x02030201: /* Au1100 BA */
1834 case 0x02030202: /* Au1100 BC */
1835 set_c0_config(1 << 19);
1840 /* CP0 hazard avoidance. */
1841 #define NXP_BARRIER() \
1842 __asm__ __volatile__( \
1843 ".set noreorder\n\t" \
1844 "nop; nop; nop; nop; nop; nop;\n\t" \
1847 static void nxp_pr4450_fixup_config(void)
1849 unsigned long config0;
1851 config0 = read_c0_config();
1853 /* clear all three cache coherency fields */
1854 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1855 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1856 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1857 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1858 write_c0_config(config0);
1862 static int cca = -1;
1864 static int __init cca_setup(char *str)
1866 get_option(&str, &cca);
1871 early_param("cca", cca_setup);
1873 static void coherency_setup(void)
1875 if (cca < 0 || cca > 7)
1876 cca = read_c0_config() & CONF_CM_CMASK;
1877 _page_cachable_default = cca << _CACHE_SHIFT;
1879 pr_debug("Using cache attribute %d\n", cca);
1880 change_c0_config(CONF_CM_CMASK, cca);
1883 * c0_status.cu=0 specifies that updates by the sc instruction use
1884 * the coherency mode specified by the TLB; 1 means cachable
1885 * coherent update on write will be used. Not all processors have
1886 * this bit and; some wire it to zero, others like Toshiba had the
1887 * silly idea of putting something else there ...
1889 switch (current_cpu_type()) {
1896 clear_c0_config(CONF_CU);
1899 * We need to catch the early Alchemy SOCs with
1900 * the write-only co_config.od bit and set it back to one on:
1901 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1904 au1x00_fixup_config_od();
1907 case PRID_IMP_PR4450:
1908 nxp_pr4450_fixup_config();
1913 static void r4k_cache_error_setup(void)
1915 extern char __weak except_vec2_generic;
1916 extern char __weak except_vec2_sb1;
1918 switch (current_cpu_type()) {
1921 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1925 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1930 void r4k_cache_init(void)
1932 extern void build_clear_page(void);
1933 extern void build_copy_page(void);
1934 struct cpuinfo_mips *c = ¤t_cpu_data;
1940 r4k_blast_dcache_page_setup();
1941 r4k_blast_dcache_page_indexed_setup();
1942 r4k_blast_dcache_setup();
1943 r4k_blast_icache_page_setup();
1944 r4k_blast_icache_page_indexed_setup();
1945 r4k_blast_icache_setup();
1946 r4k_blast_scache_page_setup();
1947 r4k_blast_scache_page_indexed_setup();
1948 r4k_blast_scache_setup();
1949 r4k_blast_scache_node_setup();
1951 r4k_blast_dcache_user_page_setup();
1952 r4k_blast_icache_user_page_setup();
1956 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1957 * This code supports virtually indexed processors and will be
1958 * unnecessarily inefficient on physically indexed processors.
1960 if (c->dcache.linesz && cpu_has_dc_aliases)
1961 shm_align_mask = max_t( unsigned long,
1962 c->dcache.sets * c->dcache.linesz - 1,
1965 shm_align_mask = PAGE_SIZE-1;
1967 __flush_cache_vmap = r4k__flush_cache_vmap;
1968 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1970 flush_cache_all = cache_noop;
1971 __flush_cache_all = r4k___flush_cache_all;
1972 flush_cache_mm = r4k_flush_cache_mm;
1973 flush_cache_page = r4k_flush_cache_page;
1974 flush_cache_range = r4k_flush_cache_range;
1976 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1978 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1979 flush_icache_all = r4k_flush_icache_all;
1980 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1981 flush_data_cache_page = r4k_flush_data_cache_page;
1982 flush_icache_range = r4k_flush_icache_range;
1983 local_flush_icache_range = local_r4k_flush_icache_range;
1984 __flush_icache_user_range = r4k_flush_icache_user_range;
1985 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1987 #ifdef CONFIG_DMA_NONCOHERENT
1988 #ifdef CONFIG_DMA_MAYBE_COHERENT
1989 if (coherentio == IO_COHERENCE_ENABLED ||
1990 (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
1991 _dma_cache_wback_inv = (void *)cache_noop;
1992 _dma_cache_wback = (void *)cache_noop;
1993 _dma_cache_inv = (void *)cache_noop;
1995 #endif /* CONFIG_DMA_MAYBE_COHERENT */
1997 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1998 _dma_cache_wback = r4k_dma_cache_wback_inv;
1999 _dma_cache_inv = r4k_dma_cache_inv;
2001 #endif /* CONFIG_DMA_NONCOHERENT */
2007 * We want to run CMP kernels on core with and without coherent
2008 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
2009 * or not to flush caches.
2011 local_r4k___flush_cache_all(NULL);
2014 board_cache_error_setup = r4k_cache_error_setup;
2019 switch (current_cpu_type()) {
2022 /* No IPI is needed because all CPUs share the same D$ */
2023 flush_data_cache_page = r4k_blast_dcache_page;
2026 /* We lose our superpowers if L2 is disabled */
2027 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
2030 /* I$ fills from D$ just by emptying the write buffers */
2031 flush_cache_page = (void *)b5k_instruction_hazard;
2032 flush_cache_range = (void *)b5k_instruction_hazard;
2033 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
2034 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
2035 flush_data_cache_page = (void *)b5k_instruction_hazard;
2036 flush_icache_range = (void *)b5k_instruction_hazard;
2037 local_flush_icache_range = (void *)b5k_instruction_hazard;
2040 /* Optimization: an L2 flush implicitly flushes the L1 */
2041 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
2044 /* Loongson-3 maintains cache coherency by hardware */
2045 __flush_cache_all = cache_noop;
2046 __flush_cache_vmap = cache_noop;
2047 __flush_cache_vunmap = cache_noop;
2048 __flush_kernel_vmap_range = (void *)cache_noop;
2049 flush_cache_mm = (void *)cache_noop;
2050 flush_cache_page = (void *)cache_noop;
2051 flush_cache_range = (void *)cache_noop;
2052 flush_cache_sigtramp = (void *)cache_noop;
2053 flush_icache_all = (void *)cache_noop;
2054 flush_data_cache_page = (void *)cache_noop;
2055 local_flush_data_cache_page = (void *)cache_noop;
2060 static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
2064 case CPU_PM_ENTER_FAILED:
2073 static struct notifier_block r4k_cache_pm_notifier_block = {
2074 .notifier_call = r4k_cache_pm_notifier,
2077 int __init r4k_cache_init_pm(void)
2079 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
2081 arch_initcall(r4k_cache_init_pm);