2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2007 Cavium Networks
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/smp.h>
13 #include <linux/bitops.h>
14 #include <linux/cpu.h>
17 #include <asm/bcache.h>
18 #include <asm/bootinfo.h>
19 #include <asm/cacheops.h>
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
23 #include <asm/pgtable.h>
24 #include <asm/r4kcache.h>
25 #include <asm/traps.h>
26 #include <asm/mmu_context.h>
29 #include <asm/octeon/octeon.h>
31 unsigned long long cache_err_dcache[NR_CPUS];
32 EXPORT_SYMBOL_GPL(cache_err_dcache);
35 * Octeon automatically flushes the dcache on tlb changes, so
36 * from Linux's viewpoint it acts much like a physically
37 * tagged cache. No flushing is needed
40 static void octeon_flush_data_cache_page(unsigned long addr)
45 static inline void octeon_local_flush_icache(void)
47 asm volatile ("synci 0($0)");
51 * Flush local I-cache for the specified range.
53 static void local_octeon_flush_icache_range(unsigned long start,
56 octeon_local_flush_icache();
60 * Flush caches as necessary for all cores affected by a
61 * vma. If no vma is supplied, all cores are flushed.
63 * @vma: VMA to flush or NULL to flush all icaches.
65 static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
67 extern void octeon_send_ipi_single(int cpu, unsigned int action);
74 octeon_local_flush_icache();
77 cpu = smp_processor_id();
80 * If we have a vma structure, we only need to worry about
81 * cores it has been used on
84 mask = *mm_cpumask(vma->vm_mm);
86 mask = *cpu_online_mask;
87 cpumask_clear_cpu(cpu, &mask);
88 for_each_cpu(cpu, &mask)
89 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
97 * Called to flush the icache on all cores
99 static void octeon_flush_icache_all(void)
101 octeon_flush_icache_all_cores(NULL);
106 * Called to flush all memory associated with a memory
109 * @mm: Memory context to flush
111 static void octeon_flush_cache_mm(struct mm_struct *mm)
114 * According to the R4K version of this file, CPUs without
115 * dcache aliases don't need to do anything here
121 * Flush a range of kernel addresses out of the icache
124 static void octeon_flush_icache_range(unsigned long start, unsigned long end)
126 octeon_flush_icache_all_cores(NULL);
131 * Flush a range out of a vma
137 static void octeon_flush_cache_range(struct vm_area_struct *vma,
138 unsigned long start, unsigned long end)
140 if (vma->vm_flags & VM_EXEC)
141 octeon_flush_icache_all_cores(vma);
146 * Flush a specific page of a vma
148 * @vma: VMA to flush page for
149 * @page: Page to flush
152 static void octeon_flush_cache_page(struct vm_area_struct *vma,
153 unsigned long page, unsigned long pfn)
155 if (vma->vm_flags & VM_EXEC)
156 octeon_flush_icache_all_cores(vma);
159 static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
165 * Probe Octeon's caches
168 static void probe_octeon(void)
170 unsigned long icache_size;
171 unsigned long dcache_size;
172 unsigned int config1;
173 struct cpuinfo_mips *c = ¤t_cpu_data;
174 int cputype = current_cpu_type();
176 config1 = read_c0_config1();
178 case CPU_CAVIUM_OCTEON:
179 case CPU_CAVIUM_OCTEON_PLUS:
180 c->icache.linesz = 2 << ((config1 >> 19) & 7);
181 c->icache.sets = 64 << ((config1 >> 22) & 7);
182 c->icache.ways = 1 + ((config1 >> 16) & 7);
183 c->icache.flags |= MIPS_CACHE_VTAG;
185 c->icache.sets * c->icache.ways * c->icache.linesz;
186 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
187 c->dcache.linesz = 128;
188 if (cputype == CPU_CAVIUM_OCTEON_PLUS)
189 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
191 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
194 c->dcache.sets * c->dcache.ways * c->dcache.linesz;
195 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
196 c->options |= MIPS_CPU_PREFETCH;
199 case CPU_CAVIUM_OCTEON2:
200 c->icache.linesz = 2 << ((config1 >> 19) & 7);
203 c->icache.flags |= MIPS_CACHE_VTAG;
204 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
206 c->dcache.linesz = 128;
209 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
210 c->options |= MIPS_CPU_PREFETCH;
213 case CPU_CAVIUM_OCTEON3:
214 c->icache.linesz = 128;
217 c->icache.flags |= MIPS_CACHE_VTAG;
218 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
220 c->dcache.linesz = 128;
223 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
224 c->options |= MIPS_CPU_PREFETCH;
228 panic("Unsupported Cavium Networks CPU type");
232 /* compute a couple of other cache variables */
233 c->icache.waysize = icache_size / c->icache.ways;
234 c->dcache.waysize = dcache_size / c->dcache.ways;
236 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
237 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
239 if (smp_processor_id() == 0) {
240 pr_info("Primary instruction cache %ldkB, %s, %d way, "
241 "%d sets, linesize %d bytes.\n",
243 cpu_has_vtag_icache ?
244 "virtually tagged" : "physically tagged",
245 c->icache.ways, c->icache.sets, c->icache.linesz);
247 pr_info("Primary data cache %ldkB, %d-way, %d sets, "
248 "linesize %d bytes.\n",
249 dcache_size >> 10, c->dcache.ways,
250 c->dcache.sets, c->dcache.linesz);
254 static void octeon_cache_error_setup(void)
256 extern char except_vec2_octeon;
257 set_handler(0x100, &except_vec2_octeon, 0x80);
261 * Setup the Octeon cache flush routines
264 void octeon_cache_init(void)
268 shm_align_mask = PAGE_SIZE - 1;
270 flush_cache_all = octeon_flush_icache_all;
271 __flush_cache_all = octeon_flush_icache_all;
272 flush_cache_mm = octeon_flush_cache_mm;
273 flush_cache_page = octeon_flush_cache_page;
274 flush_cache_range = octeon_flush_cache_range;
275 flush_icache_all = octeon_flush_icache_all;
276 flush_data_cache_page = octeon_flush_data_cache_page;
277 flush_icache_range = octeon_flush_icache_range;
278 local_flush_icache_range = local_octeon_flush_icache_range;
279 __flush_icache_user_range = octeon_flush_icache_range;
280 __local_flush_icache_user_range = local_octeon_flush_icache_range;
282 __flush_kernel_vmap_range = octeon_flush_kernel_vmap_range;
287 board_cache_error_setup = octeon_cache_error_setup;
291 * Handle a cache error exception
293 static RAW_NOTIFIER_HEAD(co_cache_error_chain);
295 int register_co_cache_error_notifier(struct notifier_block *nb)
297 return raw_notifier_chain_register(&co_cache_error_chain, nb);
299 EXPORT_SYMBOL_GPL(register_co_cache_error_notifier);
301 int unregister_co_cache_error_notifier(struct notifier_block *nb)
303 return raw_notifier_chain_unregister(&co_cache_error_chain, nb);
305 EXPORT_SYMBOL_GPL(unregister_co_cache_error_notifier);
307 static void co_cache_error_call_notifiers(unsigned long val)
309 int rv = raw_notifier_call_chain(&co_cache_error_chain, val, NULL);
310 if ((rv & ~NOTIFY_STOP_MASK) != NOTIFY_OK) {
312 unsigned long coreid = cvmx_get_core_num();
313 u64 icache_err = read_octeon_c0_icacheerr();
316 dcache_err = cache_err_dcache[coreid];
317 cache_err_dcache[coreid] = 0;
319 dcache_err = read_octeon_c0_dcacheerr();
322 pr_err("Core%lu: Cache error exception:\n", coreid);
323 pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
324 if (icache_err & 1) {
325 pr_err("CacheErr (Icache) == %llx\n",
326 (unsigned long long)icache_err);
327 write_octeon_c0_icacheerr(0);
329 if (dcache_err & 1) {
330 pr_err("CacheErr (Dcache) == %llx\n",
331 (unsigned long long)dcache_err);
337 * Called when the the exception is recoverable
340 asmlinkage void cache_parity_error_octeon_recoverable(void)
342 co_cache_error_call_notifiers(0);
346 * Called when the the exception is not recoverable
349 asmlinkage void cache_parity_error_octeon_non_recoverable(void)
351 co_cache_error_call_notifiers(1);
352 panic("Can't handle cache error: nested exception");