1 // SPDX-License-Identifier: GPL-2.0-only
2 /* IEEE754 floating point arithmetic
6 * MIPS floating point support
7 * Copyright (C) 1994-2000 Algorithmics Ltd.
10 #include <linux/compiler.h>
12 #include "ieee754sp.h"
14 int ieee754sp_class(union ieee754sp x)
21 static inline int ieee754sp_isnan(union ieee754sp x)
23 return ieee754_class_nan(ieee754sp_class(x));
26 static inline int ieee754sp_issnan(union ieee754sp x)
30 assert(ieee754sp_isnan(x));
31 qbit = (SPMANT(x) & SP_MBIT(SP_FBITS - 1)) == SP_MBIT(SP_FBITS - 1);
32 return ieee754_csr.nan2008 ^ qbit;
37 * Raise the Invalid Operation IEEE 754 exception
38 * and convert the signaling NaN supplied to a quiet NaN.
40 union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r)
42 assert(ieee754sp_issnan(r));
44 ieee754_setcx(IEEE754_INVALID_OPERATION);
45 if (ieee754_csr.nan2008) {
46 SPMANT(r) |= SP_MBIT(SP_FBITS - 1);
48 SPMANT(r) &= ~SP_MBIT(SP_FBITS - 1);
49 if (!ieee754sp_isnan(r))
50 SPMANT(r) |= SP_MBIT(SP_FBITS - 2);
56 static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm)
58 /* inexact must round of 3 bits
60 if (xm & (SP_MBIT(3) - 1)) {
61 switch (ieee754_csr.rm) {
65 xm += 0x3 + ((xm >> 3) & 1);
66 /* xm += (xm&0x8)?0x4:0x3 */
68 case FPU_CSR_RU: /* toward +Infinity */
72 case FPU_CSR_RD: /* toward -Infinity */
82 /* generate a normal/denormal number with over,under handling
84 * xe is an unbiased exponent
85 * xm is 3bit extended precision value.
87 union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm)
89 assert(xm); /* we don't gen exact zeros (probably should) */
91 assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */
92 assert(xm & (SP_HIDDEN_BIT << 3));
95 /* strip lower bits */
96 int es = SP_EMIN - xe;
98 if (ieee754_csr.nod) {
99 ieee754_setcx(IEEE754_UNDERFLOW);
100 ieee754_setcx(IEEE754_INEXACT);
102 switch(ieee754_csr.rm) {
105 return ieee754sp_zero(sn);
106 case FPU_CSR_RU: /* toward +Infinity */
108 return ieee754sp_min(0);
110 return ieee754sp_zero(1);
111 case FPU_CSR_RD: /* toward -Infinity */
113 return ieee754sp_zero(0);
115 return ieee754sp_min(1);
119 if (xe == SP_EMIN - 1 &&
120 ieee754sp_get_rounding(sn, xm) >> (SP_FBITS + 1 + 3))
122 /* Not tiny after rounding */
123 ieee754_setcx(IEEE754_INEXACT);
124 xm = ieee754sp_get_rounding(sn, xm);
127 xm &= ~(SP_MBIT(3) - 1);
130 /* sticky right shift es bits
134 assert((xm & (SP_HIDDEN_BIT << 3)) == 0);
135 assert(xe == SP_EMIN);
138 if (xm & (SP_MBIT(3) - 1)) {
139 ieee754_setcx(IEEE754_INEXACT);
140 if ((xm & (SP_HIDDEN_BIT << 3)) == 0) {
141 ieee754_setcx(IEEE754_UNDERFLOW);
144 /* inexact must round of 3 bits
146 xm = ieee754sp_get_rounding(sn, xm);
147 /* adjust exponent for rounding add overflowing
149 if (xm >> (SP_FBITS + 1 + 3)) {
150 /* add causes mantissa overflow */
158 assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
159 assert(xe >= SP_EMIN);
162 ieee754_setcx(IEEE754_OVERFLOW);
163 ieee754_setcx(IEEE754_INEXACT);
164 /* -O can be table indexed by (rm,sn) */
165 switch (ieee754_csr.rm) {
167 return ieee754sp_inf(sn);
169 return ieee754sp_max(sn);
170 case FPU_CSR_RU: /* toward +Infinity */
172 return ieee754sp_inf(0);
174 return ieee754sp_max(1);
175 case FPU_CSR_RD: /* toward -Infinity */
177 return ieee754sp_max(0);
179 return ieee754sp_inf(1);
182 /* gen norm/denorm/zero */
184 if ((xm & SP_HIDDEN_BIT) == 0) {
185 /* we underflow (tiny/zero) */
186 assert(xe == SP_EMIN);
187 if (ieee754_csr.mx & IEEE754_UNDERFLOW)
188 ieee754_setcx(IEEE754_UNDERFLOW);
189 return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
191 assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
192 assert(xm & SP_HIDDEN_BIT);
194 return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);