1 // SPDX-License-Identifier: GPL-2.0-only
2 /* IEEE754 floating point arithmetic
3 * double precision: common utilities
6 * MIPS floating point support
7 * Copyright (C) 1994-2000 Algorithmics Ltd.
10 #include "ieee754dp.h"
12 union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
27 switch (CLPAIR(xc, yc)) {
28 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
29 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
30 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
31 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
32 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
33 return ieee754dp_nanxcpt(y);
35 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
36 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
37 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
38 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
39 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
40 case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
41 return ieee754dp_nanxcpt(x);
43 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
44 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
45 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
46 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
49 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
50 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
51 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
52 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
53 case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
60 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
63 ieee754_setcx(IEEE754_INVALID_OPERATION);
64 return ieee754dp_indef();
66 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
67 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
68 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
69 return ieee754dp_inf(ys ^ 1);
71 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
72 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
73 case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
79 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
83 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
85 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
86 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
89 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
90 case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
95 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
99 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
100 /* normalize ym,ye */
104 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
105 /* normalize xm,xe */
109 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
112 /* flip sign of y and handle as add */
115 assert(xm & DP_HIDDEN_BIT);
116 assert(ym & DP_HIDDEN_BIT);
119 /* provide guard,round and stick bit dpace */
125 * Have to shift y fraction right to align
130 } else if (ye > xe) {
132 * Have to shift x fraction right to align
139 assert(xe <= DP_EMAX);
142 /* generate 28 bit result of adding two 27 bit numbers
146 if (xm >> (DP_FBITS + 1 + 3)) { /* carry out */
147 xm = XDPSRS1(xm); /* shift preserving sticky */
158 if (ieee754_csr.rm == FPU_CSR_RD)
159 return ieee754dp_zero(1); /* round negative inf. => sign = -1 */
161 return ieee754dp_zero(0); /* other round modes => sign = 1 */
164 /* normalize to rounding precision
166 while ((xm >> (DP_FBITS + 3)) == 0) {
172 return ieee754dp_format(xs, xe, xm);