1 // SPDX-License-Identifier: GPL-2.0-only
3 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
5 * MIPS floating point support
6 * Copyright (C) 1994-2000 Algorithmics Ltd.
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * A complete emulator for MIPS coprocessor 1 instructions. This is
12 * required for #float(switch) or #float(trap), where it catches all
13 * COP1 instructions via the "CoProcessor Unusable" exception.
15 * More surprisingly it is also required for #float(ieee), to help out
16 * the hardware FPU at the boundaries of the IEEE-754 representation
17 * (denormalised values, infinities, underflow, etc). It is made
18 * quite nasty because emulation of some non-COP1 instructions is
19 * required, e.g. in branch delay slots.
21 * Note if you know that you won't have an FPU, then you'll get much
22 * better performance by compiling with -msoft-float!
24 #include <linux/sched.h>
25 #include <linux/debugfs.h>
26 #include <linux/percpu-defs.h>
27 #include <linux/perf_event.h>
29 #include <asm/branch.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
33 #include <linux/uaccess.h>
35 #include <asm/cpu-info.h>
36 #include <asm/processor.h>
37 #include <asm/fpu_emulator.h>
39 #include <asm/mips-r2-to-r6-emul.h>
43 /* Function which emulates a floating point instruction. */
45 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
48 static int fpux_emu(struct pt_regs *,
49 struct mips_fpu_struct *, mips_instruction, void __user **);
51 /* Control registers */
53 #define FPCREG_RID 0 /* $0 = revision id */
54 #define FPCREG_FCCR 25 /* $25 = fccr */
55 #define FPCREG_FEXR 26 /* $26 = fexr */
56 #define FPCREG_FENR 28 /* $28 = fenr */
57 #define FPCREG_CSR 31 /* $31 = csr */
59 /* convert condition code register number to csr bit */
60 const unsigned int fpucondbit[8] = {
71 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
72 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
73 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
74 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
75 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
78 * This functions translates a 32-bit microMIPS instruction
79 * into a 32-bit MIPS32 instruction. Returns 0 on success
80 * and SIGILL otherwise.
82 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
84 union mips_instruction insn = *insn_ptr;
85 union mips_instruction mips32_insn = insn;
88 switch (insn.mm_i_format.opcode) {
90 mips32_insn.mm_i_format.opcode = ldc1_op;
91 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
92 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
95 mips32_insn.mm_i_format.opcode = lwc1_op;
96 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
97 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
100 mips32_insn.mm_i_format.opcode = sdc1_op;
101 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
102 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
105 mips32_insn.mm_i_format.opcode = swc1_op;
106 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
107 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
110 /* NOTE: offset is << by 1 if in microMIPS mode. */
111 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
112 (insn.mm_i_format.rt == mm_bc1t_op)) {
113 mips32_insn.fb_format.opcode = cop1_op;
114 mips32_insn.fb_format.bc = bc_op;
115 mips32_insn.fb_format.flag =
116 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
121 switch (insn.mm_fp0_format.func) {
130 op = insn.mm_fp0_format.func;
131 if (op == mm_32f_01_op)
133 else if (op == mm_32f_11_op)
135 else if (op == mm_32f_02_op)
137 else if (op == mm_32f_12_op)
139 else if (op == mm_32f_41_op)
141 else if (op == mm_32f_51_op)
143 else if (op == mm_32f_42_op)
147 mips32_insn.fp6_format.opcode = cop1x_op;
148 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
149 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
150 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
151 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
152 mips32_insn.fp6_format.func = func;
155 func = -1; /* Invalid */
156 op = insn.mm_fp5_format.op & 0x7;
157 if (op == mm_ldxc1_op)
159 else if (op == mm_sdxc1_op)
161 else if (op == mm_lwxc1_op)
163 else if (op == mm_swxc1_op)
167 mips32_insn.r_format.opcode = cop1x_op;
168 mips32_insn.r_format.rs =
169 insn.mm_fp5_format.base;
170 mips32_insn.r_format.rt =
171 insn.mm_fp5_format.index;
172 mips32_insn.r_format.rd = 0;
173 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
174 mips32_insn.r_format.func = func;
179 op = -1; /* Invalid */
180 if (insn.mm_fp2_format.op == mm_fmovt_op)
182 else if (insn.mm_fp2_format.op == mm_fmovf_op)
185 mips32_insn.fp0_format.opcode = cop1_op;
186 mips32_insn.fp0_format.fmt =
187 sdps_format[insn.mm_fp2_format.fmt];
188 mips32_insn.fp0_format.ft =
189 (insn.mm_fp2_format.cc<<2) + op;
190 mips32_insn.fp0_format.fs =
191 insn.mm_fp2_format.fs;
192 mips32_insn.fp0_format.fd =
193 insn.mm_fp2_format.fd;
194 mips32_insn.fp0_format.func = fmovc_op;
199 func = -1; /* Invalid */
200 if (insn.mm_fp0_format.op == mm_fadd_op)
202 else if (insn.mm_fp0_format.op == mm_fsub_op)
204 else if (insn.mm_fp0_format.op == mm_fmul_op)
206 else if (insn.mm_fp0_format.op == mm_fdiv_op)
209 mips32_insn.fp0_format.opcode = cop1_op;
210 mips32_insn.fp0_format.fmt =
211 sdps_format[insn.mm_fp0_format.fmt];
212 mips32_insn.fp0_format.ft =
213 insn.mm_fp0_format.ft;
214 mips32_insn.fp0_format.fs =
215 insn.mm_fp0_format.fs;
216 mips32_insn.fp0_format.fd =
217 insn.mm_fp0_format.fd;
218 mips32_insn.fp0_format.func = func;
223 func = -1; /* Invalid */
224 if (insn.mm_fp0_format.op == mm_fmovn_op)
226 else if (insn.mm_fp0_format.op == mm_fmovz_op)
229 mips32_insn.fp0_format.opcode = cop1_op;
230 mips32_insn.fp0_format.fmt =
231 sdps_format[insn.mm_fp0_format.fmt];
232 mips32_insn.fp0_format.ft =
233 insn.mm_fp0_format.ft;
234 mips32_insn.fp0_format.fs =
235 insn.mm_fp0_format.fs;
236 mips32_insn.fp0_format.fd =
237 insn.mm_fp0_format.fd;
238 mips32_insn.fp0_format.func = func;
242 case mm_32f_73_op: /* POOL32FXF */
243 switch (insn.mm_fp1_format.op) {
248 if ((insn.mm_fp1_format.op & 0x7f) ==
253 mips32_insn.r_format.opcode = spec_op;
254 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
255 mips32_insn.r_format.rt =
256 (insn.mm_fp4_format.cc << 2) + op;
257 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
258 mips32_insn.r_format.re = 0;
259 mips32_insn.r_format.func = movc_op;
265 if ((insn.mm_fp1_format.op & 0x7f) ==
268 fmt = swl_format[insn.mm_fp3_format.fmt];
271 fmt = dwl_format[insn.mm_fp3_format.fmt];
273 mips32_insn.fp0_format.opcode = cop1_op;
274 mips32_insn.fp0_format.fmt = fmt;
275 mips32_insn.fp0_format.ft = 0;
276 mips32_insn.fp0_format.fs =
277 insn.mm_fp3_format.fs;
278 mips32_insn.fp0_format.fd =
279 insn.mm_fp3_format.rt;
280 mips32_insn.fp0_format.func = func;
288 if ((insn.mm_fp1_format.op & 0x7f) ==
291 else if ((insn.mm_fp1_format.op & 0x7f) ==
296 mips32_insn.fp0_format.opcode = cop1_op;
297 mips32_insn.fp0_format.fmt =
298 sdps_format[insn.mm_fp3_format.fmt];
299 mips32_insn.fp0_format.ft = 0;
300 mips32_insn.fp0_format.fs =
301 insn.mm_fp3_format.fs;
302 mips32_insn.fp0_format.fd =
303 insn.mm_fp3_format.rt;
304 mips32_insn.fp0_format.func = func;
316 if (insn.mm_fp1_format.op == mm_ffloorl_op)
318 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
320 else if (insn.mm_fp1_format.op == mm_fceill_op)
322 else if (insn.mm_fp1_format.op == mm_fceilw_op)
324 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
326 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
328 else if (insn.mm_fp1_format.op == mm_froundl_op)
330 else if (insn.mm_fp1_format.op == mm_froundw_op)
332 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
336 mips32_insn.fp0_format.opcode = cop1_op;
337 mips32_insn.fp0_format.fmt =
338 sd_format[insn.mm_fp1_format.fmt];
339 mips32_insn.fp0_format.ft = 0;
340 mips32_insn.fp0_format.fs =
341 insn.mm_fp1_format.fs;
342 mips32_insn.fp0_format.fd =
343 insn.mm_fp1_format.rt;
344 mips32_insn.fp0_format.func = func;
349 if (insn.mm_fp1_format.op == mm_frsqrt_op)
351 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
355 mips32_insn.fp0_format.opcode = cop1_op;
356 mips32_insn.fp0_format.fmt =
357 sdps_format[insn.mm_fp1_format.fmt];
358 mips32_insn.fp0_format.ft = 0;
359 mips32_insn.fp0_format.fs =
360 insn.mm_fp1_format.fs;
361 mips32_insn.fp0_format.fd =
362 insn.mm_fp1_format.rt;
363 mips32_insn.fp0_format.func = func;
371 if (insn.mm_fp1_format.op == mm_mfc1_op)
373 else if (insn.mm_fp1_format.op == mm_mtc1_op)
375 else if (insn.mm_fp1_format.op == mm_cfc1_op)
377 else if (insn.mm_fp1_format.op == mm_ctc1_op)
379 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
383 mips32_insn.fp1_format.opcode = cop1_op;
384 mips32_insn.fp1_format.op = op;
385 mips32_insn.fp1_format.rt =
386 insn.mm_fp1_format.rt;
387 mips32_insn.fp1_format.fs =
388 insn.mm_fp1_format.fs;
389 mips32_insn.fp1_format.fd = 0;
390 mips32_insn.fp1_format.func = 0;
396 case mm_32f_74_op: /* c.cond.fmt */
397 mips32_insn.fp0_format.opcode = cop1_op;
398 mips32_insn.fp0_format.fmt =
399 sdps_format[insn.mm_fp4_format.fmt];
400 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
401 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
402 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
403 mips32_insn.fp0_format.func =
404 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
414 *insn_ptr = mips32_insn;
419 * Redundant with logic already in kernel/branch.c,
420 * embedded in compute_return_epc. At some point,
421 * a single subroutine should be used across both
424 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
425 unsigned long *contpc)
427 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
429 unsigned int bit = 0;
433 switch (insn.i_format.opcode) {
435 switch (insn.r_format.func) {
437 if (insn.r_format.rd != 0) {
438 regs->regs[insn.r_format.rd] =
439 regs->cp0_epc + dec_insn.pc_inc +
440 dec_insn.next_pc_inc;
444 /* For R6, JR already emulated in jalr_op */
445 if (NO_R6EMU && insn.r_format.func == jr_op)
447 *contpc = regs->regs[insn.r_format.rs];
452 switch (insn.i_format.rt) {
455 if (NO_R6EMU && (insn.i_format.rs ||
456 insn.i_format.rt == bltzall_op))
459 regs->regs[31] = regs->cp0_epc +
461 dec_insn.next_pc_inc;
468 if ((long)regs->regs[insn.i_format.rs] < 0)
469 *contpc = regs->cp0_epc +
471 (insn.i_format.simmediate << 2);
473 *contpc = regs->cp0_epc +
475 dec_insn.next_pc_inc;
479 if (NO_R6EMU && (insn.i_format.rs ||
480 insn.i_format.rt == bgezall_op))
483 regs->regs[31] = regs->cp0_epc +
485 dec_insn.next_pc_inc;
492 if ((long)regs->regs[insn.i_format.rs] >= 0)
493 *contpc = regs->cp0_epc +
495 (insn.i_format.simmediate << 2);
497 *contpc = regs->cp0_epc +
499 dec_insn.next_pc_inc;
507 regs->regs[31] = regs->cp0_epc +
509 dec_insn.next_pc_inc;
512 *contpc = regs->cp0_epc + dec_insn.pc_inc;
515 *contpc |= (insn.j_format.target << 2);
516 /* Set microMIPS mode bit: XOR for jalx. */
524 if (regs->regs[insn.i_format.rs] ==
525 regs->regs[insn.i_format.rt])
526 *contpc = regs->cp0_epc +
528 (insn.i_format.simmediate << 2);
530 *contpc = regs->cp0_epc +
532 dec_insn.next_pc_inc;
539 if (regs->regs[insn.i_format.rs] !=
540 regs->regs[insn.i_format.rt])
541 *contpc = regs->cp0_epc +
543 (insn.i_format.simmediate << 2);
545 *contpc = regs->cp0_epc +
547 dec_insn.next_pc_inc;
550 if (!insn.i_format.rt && NO_R6EMU)
556 * Compact branches for R6 for the
557 * blez and blezl opcodes.
558 * BLEZ | rs = 0 | rt != 0 == BLEZALC
559 * BLEZ | rs = rt != 0 == BGEZALC
560 * BLEZ | rs != 0 | rt != 0 == BGEUC
561 * BLEZL | rs = 0 | rt != 0 == BLEZC
562 * BLEZL | rs = rt != 0 == BGEZC
563 * BLEZL | rs != 0 | rt != 0 == BGEC
565 * For real BLEZ{,L}, rt is always 0.
567 if (cpu_has_mips_r6 && insn.i_format.rt) {
568 if ((insn.i_format.opcode == blez_op) &&
569 ((!insn.i_format.rs && insn.i_format.rt) ||
570 (insn.i_format.rs == insn.i_format.rt)))
571 regs->regs[31] = regs->cp0_epc +
573 *contpc = regs->cp0_epc + dec_insn.pc_inc +
574 dec_insn.next_pc_inc;
578 if ((long)regs->regs[insn.i_format.rs] <= 0)
579 *contpc = regs->cp0_epc +
581 (insn.i_format.simmediate << 2);
583 *contpc = regs->cp0_epc +
585 dec_insn.next_pc_inc;
588 if (!insn.i_format.rt && NO_R6EMU)
593 * Compact branches for R6 for the
594 * bgtz and bgtzl opcodes.
595 * BGTZ | rs = 0 | rt != 0 == BGTZALC
596 * BGTZ | rs = rt != 0 == BLTZALC
597 * BGTZ | rs != 0 | rt != 0 == BLTUC
598 * BGTZL | rs = 0 | rt != 0 == BGTZC
599 * BGTZL | rs = rt != 0 == BLTZC
600 * BGTZL | rs != 0 | rt != 0 == BLTC
602 * *ZALC varint for BGTZ &&& rt != 0
603 * For real GTZ{,L}, rt is always 0.
605 if (cpu_has_mips_r6 && insn.i_format.rt) {
606 if ((insn.i_format.opcode == blez_op) &&
607 ((!insn.i_format.rs && insn.i_format.rt) ||
608 (insn.i_format.rs == insn.i_format.rt)))
609 regs->regs[31] = regs->cp0_epc +
611 *contpc = regs->cp0_epc + dec_insn.pc_inc +
612 dec_insn.next_pc_inc;
617 if ((long)regs->regs[insn.i_format.rs] > 0)
618 *contpc = regs->cp0_epc +
620 (insn.i_format.simmediate << 2);
622 *contpc = regs->cp0_epc +
624 dec_insn.next_pc_inc;
628 if (!cpu_has_mips_r6)
630 if (insn.i_format.rt && !insn.i_format.rs)
631 regs->regs[31] = regs->cp0_epc + 4;
632 *contpc = regs->cp0_epc + dec_insn.pc_inc +
633 dec_insn.next_pc_inc;
636 #ifdef CONFIG_CPU_CAVIUM_OCTEON
637 case lwc2_op: /* This is bbit0 on Octeon */
638 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
639 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
641 *contpc = regs->cp0_epc + 8;
643 case ldc2_op: /* This is bbit032 on Octeon */
644 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
645 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
647 *contpc = regs->cp0_epc + 8;
649 case swc2_op: /* This is bbit1 on Octeon */
650 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
651 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
653 *contpc = regs->cp0_epc + 8;
655 case sdc2_op: /* This is bbit132 on Octeon */
656 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
657 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
659 *contpc = regs->cp0_epc + 8;
664 * Only valid for MIPS R6 but we can still end up
665 * here from a broken userland so just tell emulator
666 * this is not a branch and let it break later on.
668 if (!cpu_has_mips_r6)
670 *contpc = regs->cp0_epc + dec_insn.pc_inc +
671 dec_insn.next_pc_inc;
675 if (!cpu_has_mips_r6)
677 regs->regs[31] = regs->cp0_epc + 4;
678 *contpc = regs->cp0_epc + dec_insn.pc_inc +
679 dec_insn.next_pc_inc;
683 if (!cpu_has_mips_r6)
685 *contpc = regs->cp0_epc + dec_insn.pc_inc +
686 dec_insn.next_pc_inc;
690 if (!cpu_has_mips_r6)
692 if (!insn.i_format.rs)
693 regs->regs[31] = regs->cp0_epc + 4;
694 *contpc = regs->cp0_epc + dec_insn.pc_inc +
695 dec_insn.next_pc_inc;
701 /* Need to check for R6 bc1nez and bc1eqz branches */
702 if (cpu_has_mips_r6 &&
703 ((insn.i_format.rs == bc1eqz_op) ||
704 (insn.i_format.rs == bc1nez_op))) {
706 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
707 bit0 = get_fpr32(fpr, 0) & 0x1;
708 switch (insn.i_format.rs) {
717 *contpc = regs->cp0_epc +
719 (insn.i_format.simmediate << 2);
721 *contpc = regs->cp0_epc +
723 dec_insn.next_pc_inc;
727 /* R2/R6 compatible cop1 instruction */
731 if (insn.i_format.rs == bc_op) {
734 fcr31 = read_32bit_cp1_register(CP1_STATUS);
736 fcr31 = current->thread.fpu.fcr31;
739 bit = (insn.i_format.rt >> 2);
742 switch (insn.i_format.rt & 3) {
745 if (~fcr31 & (1 << bit))
746 *contpc = regs->cp0_epc +
748 (insn.i_format.simmediate << 2);
750 *contpc = regs->cp0_epc +
752 dec_insn.next_pc_inc;
756 if (fcr31 & (1 << bit))
757 *contpc = regs->cp0_epc +
759 (insn.i_format.simmediate << 2);
761 *contpc = regs->cp0_epc +
763 dec_insn.next_pc_inc;
773 * In the Linux kernel, we support selection of FPR format on the
774 * basis of the Status.FR bit. If an FPU is not present, the FR bit
775 * is hardwired to zero, which would imply a 32-bit FPU even for
776 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
777 * FPU emu is slow and bulky and optimizing this function offers fairly
778 * sizeable benefits so we try to be clever and make this function return
779 * a constant whenever possible, that is on 64-bit kernels without O32
780 * compatibility enabled and on 32-bit without 64-bit FPU support.
782 static inline int cop1_64bit(struct pt_regs *xcp)
784 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
786 else if (IS_ENABLED(CONFIG_32BIT) &&
787 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
790 return !test_thread_flag(TIF_32BIT_FPREGS);
793 static inline bool hybrid_fprs(void)
795 return test_thread_flag(TIF_HYBRID_FPREGS);
798 #define SIFROMREG(si, x) \
800 if (cop1_64bit(xcp) && !hybrid_fprs()) \
801 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
803 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
806 #define SITOREG(si, x) \
808 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
810 set_fpr32(&ctx->fpr[x], 0, si); \
811 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
812 set_fpr32(&ctx->fpr[x], i, 0); \
814 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
818 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
820 #define SITOHREG(si, x) \
823 set_fpr32(&ctx->fpr[x], 1, si); \
824 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
825 set_fpr32(&ctx->fpr[x], i, 0); \
828 #define DIFROMREG(di, x) \
829 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
831 #define DITOREG(di, x) \
833 unsigned int fpr, i; \
834 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
835 set_fpr64(&ctx->fpr[fpr], 0, di); \
836 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
837 set_fpr64(&ctx->fpr[fpr], i, 0); \
840 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
841 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
842 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
843 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
846 * Emulate a CFC1 instruction.
848 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
851 u32 fcr31 = ctx->fcr31;
854 switch (MIPSInst_RD(ir)) {
857 pr_debug("%p gpr[%d]<-csr=%08x\n",
858 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
864 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
867 pr_debug("%p gpr[%d]<-enr=%08x\n",
868 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
874 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
875 pr_debug("%p gpr[%d]<-exr=%08x\n",
876 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
882 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
885 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
886 pr_debug("%p gpr[%d]<-ccr=%08x\n",
887 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
891 value = boot_cpu_data.fpu_id;
899 xcp->regs[MIPSInst_RT(ir)] = value;
903 * Emulate a CTC1 instruction.
905 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
908 u32 fcr31 = ctx->fcr31;
912 if (MIPSInst_RT(ir) == 0)
915 value = xcp->regs[MIPSInst_RT(ir)];
917 switch (MIPSInst_RD(ir)) {
919 pr_debug("%p gpr[%d]->csr=%08x\n",
920 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
922 /* Preserve read-only bits. */
923 mask = boot_cpu_data.fpu_msk31;
924 fcr31 = (value & ~mask) | (fcr31 & mask);
930 pr_debug("%p gpr[%d]->enr=%08x\n",
931 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
932 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
933 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
941 pr_debug("%p gpr[%d]->exr=%08x\n",
942 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
943 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
944 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
950 pr_debug("%p gpr[%d]->ccr=%08x\n",
951 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
952 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
953 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
967 * Emulate the single floating point instruction pointed at by EPC.
968 * Two instructions if the instruction is in a branch delay slot.
971 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
972 struct mm_decoded_insn dec_insn, void __user **fault_addr)
974 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
975 unsigned int cond, cbit, bit0;
986 * These are giving gcc a gentle hint about what to expect in
987 * dec_inst in order to do better optimization.
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
992 /* XXX NEC Vr54xx bug workaround */
993 if (delay_slot(xcp)) {
994 if (dec_insn.micro_mips_mode) {
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
996 clear_delay_slot(xcp);
998 if (!isBranchInstr(xcp, dec_insn, &contpc))
999 clear_delay_slot(xcp);
1003 if (delay_slot(xcp)) {
1005 * The instruction to be emulated is in a branch delay slot
1006 * which means that we have to emulate the branch instruction
1007 * BEFORE we do the cop1 instruction.
1009 * This branch could be a COP1 branch, but in that case we
1010 * would have had a trap for that instruction, and would not
1011 * come through this route.
1013 * Linux MIPS branch emulator operates on context, updating the
1016 ir = dec_insn.next_insn; /* process delay slot instr */
1017 pc_inc = dec_insn.next_pc_inc;
1019 ir = dec_insn.insn; /* process current instr */
1020 pc_inc = dec_insn.pc_inc;
1024 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025 * instructions, we want to convert microMIPS FPU instructions
1026 * into MIPS32 instructions so that we could reuse all of the
1027 * FPU emulation code.
1029 * NOTE: We cannot do this for branch instructions since they
1030 * are not a subset. Example: Cannot emulate a 16-bit
1031 * aligned target address with a MIPS32 instruction.
1033 if (dec_insn.micro_mips_mode) {
1035 * If next instruction is a 16-bit instruction, then it
1036 * it cannot be a FPU instruction. This could happen
1037 * since we can be called for non-FPU instructions.
1039 if ((pc_inc == 2) ||
1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1046 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1047 MIPS_FPU_EMU_INC_STATS(emulated);
1048 switch (MIPSInst_OPCODE(ir)) {
1050 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1052 MIPS_FPU_EMU_INC_STATS(loads);
1054 if (!access_ok(dva, sizeof(u64))) {
1055 MIPS_FPU_EMU_INC_STATS(errors);
1059 if (__get_user(dval, dva)) {
1060 MIPS_FPU_EMU_INC_STATS(errors);
1064 DITOREG(dval, MIPSInst_RT(ir));
1068 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1070 MIPS_FPU_EMU_INC_STATS(stores);
1071 DIFROMREG(dval, MIPSInst_RT(ir));
1072 if (!access_ok(dva, sizeof(u64))) {
1073 MIPS_FPU_EMU_INC_STATS(errors);
1077 if (__put_user(dval, dva)) {
1078 MIPS_FPU_EMU_INC_STATS(errors);
1085 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1087 MIPS_FPU_EMU_INC_STATS(loads);
1088 if (!access_ok(wva, sizeof(u32))) {
1089 MIPS_FPU_EMU_INC_STATS(errors);
1093 if (__get_user(wval, wva)) {
1094 MIPS_FPU_EMU_INC_STATS(errors);
1098 SITOREG(wval, MIPSInst_RT(ir));
1102 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1104 MIPS_FPU_EMU_INC_STATS(stores);
1105 SIFROMREG(wval, MIPSInst_RT(ir));
1106 if (!access_ok(wva, sizeof(u32))) {
1107 MIPS_FPU_EMU_INC_STATS(errors);
1111 if (__put_user(wval, wva)) {
1112 MIPS_FPU_EMU_INC_STATS(errors);
1119 switch (MIPSInst_RS(ir)) {
1121 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1124 /* copregister fs -> gpr[rt] */
1125 if (MIPSInst_RT(ir) != 0) {
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1132 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1135 /* copregister fs <- rt */
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1140 if (!cpu_has_mips_r2_r6)
1143 /* copregister rd -> gpr[rt] */
1144 if (MIPSInst_RT(ir) != 0) {
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1151 if (!cpu_has_mips_r2_r6)
1154 /* copregister rd <- gpr[rt] */
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1159 /* copregister rd -> gpr[rt] */
1160 if (MIPSInst_RT(ir) != 0) {
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1167 /* copregister rd <- rt */
1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1172 /* cop control register rd -> gpr[rt] */
1173 cop1_cfc(xcp, ctx, ir);
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp, ctx, ir);
1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1186 if (!cpu_has_mips_r6 || delay_slot(xcp))
1191 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1192 bit0 = get_fpr32(fpr, 0) & 0x1;
1193 switch (MIPSInst_RS(ir)) {
1195 MIPS_FPU_EMU_INC_STATS(bc1eqz);
1199 MIPS_FPU_EMU_INC_STATS(bc1nez);
1206 if (delay_slot(xcp))
1209 if (cpu_has_mips_4_5_r)
1210 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1212 cbit = FPU_CSR_COND;
1213 cond = ctx->fcr31 & cbit;
1216 switch (MIPSInst_RT(ir) & 3) {
1218 if (cpu_has_mips_2_3_4_5_r)
1225 if (cpu_has_mips_2_3_4_5_r)
1232 MIPS_FPU_EMU_INC_STATS(branches);
1233 set_delay_slot(xcp);
1236 * Branch taken: emulate dslot instruction
1241 * Remember EPC at the branch to point back
1242 * at so that any delay-slot instruction
1243 * signal is not silently ignored.
1245 bcpc = xcp->cp0_epc;
1246 xcp->cp0_epc += dec_insn.pc_inc;
1248 contpc = MIPSInst_SIMM(ir);
1249 ir = dec_insn.next_insn;
1250 if (dec_insn.micro_mips_mode) {
1251 contpc = (xcp->cp0_epc + (contpc << 1));
1253 /* If 16-bit instruction, not FPU. */
1254 if ((dec_insn.next_pc_inc == 2) ||
1255 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1258 * Since this instruction will
1259 * be put on the stack with
1260 * 32-bit words, get around
1261 * this problem by putting a
1262 * NOP16 as the second one.
1264 if (dec_insn.next_pc_inc == 2)
1265 ir = (ir & (~0xffff)) | MM_NOP16;
1268 * Single step the non-CP1
1269 * instruction in the dslot.
1271 sig = mips_dsemul(xcp, ir,
1276 xcp->cp0_epc = bcpc;
1278 * SIGILL forces out of
1279 * the emulation loop.
1281 return sig ? sig : SIGILL;
1284 contpc = (xcp->cp0_epc + (contpc << 2));
1286 switch (MIPSInst_OPCODE(ir)) {
1293 if (cpu_has_mips_2_3_4_5_r)
1302 if (cpu_has_mips_4_5_64_r2_r6)
1303 /* its one of ours */
1309 switch (MIPSInst_FUNC(ir)) {
1311 if (cpu_has_mips_4_5_r)
1319 xcp->cp0_epc = bcpc;
1324 * Single step the non-cp1
1325 * instruction in the dslot
1327 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1331 xcp->cp0_epc = bcpc;
1332 /* SIGILL forces out of the emulation loop. */
1333 return sig ? sig : SIGILL;
1334 } else if (likely) { /* branch not taken */
1336 * branch likely nullifies
1337 * dslot if not taken
1339 xcp->cp0_epc += dec_insn.pc_inc;
1340 contpc += dec_insn.pc_inc;
1342 * else continue & execute
1343 * dslot as normal insn
1349 if (!(MIPSInst_RS(ir) & 0x10))
1352 /* a real fpu computation instruction */
1353 sig = fpu_emu(xcp, ctx, ir);
1360 if (!cpu_has_mips_4_5_64_r2_r6)
1363 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1369 if (!cpu_has_mips_4_5_r)
1372 if (MIPSInst_FUNC(ir) != movc_op)
1374 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1375 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1376 xcp->regs[MIPSInst_RD(ir)] =
1377 xcp->regs[MIPSInst_RS(ir)];
1384 xcp->cp0_epc = contpc;
1385 clear_delay_slot(xcp);
1391 * Conversion table from MIPS compare ops 48-63
1392 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1394 static const unsigned char cmptab[8] = {
1395 0, /* cmp_0 (sig) cmp_sf */
1396 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1397 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1398 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1399 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1400 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1401 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1402 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1405 static const unsigned char negative_cmptab[8] = {
1407 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1408 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1409 IEEE754_CLT | IEEE754_CGT,
1415 * Additional MIPS4 instructions
1418 #define DEF3OP(name, p, f1, f2, f3) \
1419 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1420 union ieee754##p s, union ieee754##p t) \
1422 struct _ieee754_csr ieee754_csr_save; \
1424 ieee754_csr_save = ieee754_csr; \
1426 ieee754_csr_save.cx |= ieee754_csr.cx; \
1427 ieee754_csr_save.sx |= ieee754_csr.sx; \
1429 ieee754_csr.cx |= ieee754_csr_save.cx; \
1430 ieee754_csr.sx |= ieee754_csr_save.sx; \
1434 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1436 return ieee754dp_div(ieee754dp_one(0), d);
1439 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1441 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1444 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1446 return ieee754sp_div(ieee754sp_one(0), s);
1449 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1451 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1454 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1455 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1456 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1457 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1458 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1459 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1460 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1461 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1463 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1464 mips_instruction ir, void __user **fault_addr)
1466 unsigned int rcsr = 0; /* resulting csr */
1468 MIPS_FPU_EMU_INC_STATS(cp1xops);
1470 switch (MIPSInst_FMA_FFMT(ir)) {
1471 case s_fmt:{ /* 0 */
1473 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1474 union ieee754sp fd, fr, fs, ft;
1478 switch (MIPSInst_FUNC(ir)) {
1480 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1481 xcp->regs[MIPSInst_FT(ir)]);
1483 MIPS_FPU_EMU_INC_STATS(loads);
1484 if (!access_ok(va, sizeof(u32))) {
1485 MIPS_FPU_EMU_INC_STATS(errors);
1489 if (__get_user(val, va)) {
1490 MIPS_FPU_EMU_INC_STATS(errors);
1494 SITOREG(val, MIPSInst_FD(ir));
1498 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1499 xcp->regs[MIPSInst_FT(ir)]);
1501 MIPS_FPU_EMU_INC_STATS(stores);
1503 SIFROMREG(val, MIPSInst_FS(ir));
1504 if (!access_ok(va, sizeof(u32))) {
1505 MIPS_FPU_EMU_INC_STATS(errors);
1509 if (put_user(val, va)) {
1510 MIPS_FPU_EMU_INC_STATS(errors);
1517 handler = fpemu_sp_madd;
1520 handler = fpemu_sp_msub;
1523 handler = fpemu_sp_nmadd;
1526 handler = fpemu_sp_nmsub;
1530 SPFROMREG(fr, MIPSInst_FR(ir));
1531 SPFROMREG(fs, MIPSInst_FS(ir));
1532 SPFROMREG(ft, MIPSInst_FT(ir));
1533 fd = (*handler) (fr, fs, ft);
1534 SPTOREG(fd, MIPSInst_FD(ir));
1537 if (ieee754_cxtest(IEEE754_INEXACT)) {
1538 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1539 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1541 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1542 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1543 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1545 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1546 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1547 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1549 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1550 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1551 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1554 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1555 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1556 /*printk ("SIGFPE: FPU csr = %08x\n",
1569 case d_fmt:{ /* 1 */
1570 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1571 union ieee754dp fd, fr, fs, ft;
1575 switch (MIPSInst_FUNC(ir)) {
1577 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1578 xcp->regs[MIPSInst_FT(ir)]);
1580 MIPS_FPU_EMU_INC_STATS(loads);
1581 if (!access_ok(va, sizeof(u64))) {
1582 MIPS_FPU_EMU_INC_STATS(errors);
1586 if (__get_user(val, va)) {
1587 MIPS_FPU_EMU_INC_STATS(errors);
1591 DITOREG(val, MIPSInst_FD(ir));
1595 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1596 xcp->regs[MIPSInst_FT(ir)]);
1598 MIPS_FPU_EMU_INC_STATS(stores);
1599 DIFROMREG(val, MIPSInst_FS(ir));
1600 if (!access_ok(va, sizeof(u64))) {
1601 MIPS_FPU_EMU_INC_STATS(errors);
1605 if (__put_user(val, va)) {
1606 MIPS_FPU_EMU_INC_STATS(errors);
1613 handler = fpemu_dp_madd;
1616 handler = fpemu_dp_msub;
1619 handler = fpemu_dp_nmadd;
1622 handler = fpemu_dp_nmsub;
1626 DPFROMREG(fr, MIPSInst_FR(ir));
1627 DPFROMREG(fs, MIPSInst_FS(ir));
1628 DPFROMREG(ft, MIPSInst_FT(ir));
1629 fd = (*handler) (fr, fs, ft);
1630 DPTOREG(fd, MIPSInst_FD(ir));
1640 if (MIPSInst_FUNC(ir) != pfetch_op)
1643 /* ignore prefx operation */
1656 * Emulate a single COP1 arithmetic instruction.
1658 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1659 mips_instruction ir)
1661 int rfmt; /* resulting format */
1662 unsigned int rcsr = 0; /* resulting csr */
1671 } rv; /* resulting value */
1674 MIPS_FPU_EMU_INC_STATS(cp1ops);
1675 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1676 case s_fmt: { /* 0 */
1678 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1679 union ieee754sp(*u) (union ieee754sp);
1681 union ieee754sp fd, fs, ft;
1683 switch (MIPSInst_FUNC(ir)) {
1686 MIPS_FPU_EMU_INC_STATS(add_s);
1687 handler.b = ieee754sp_add;
1690 MIPS_FPU_EMU_INC_STATS(sub_s);
1691 handler.b = ieee754sp_sub;
1694 MIPS_FPU_EMU_INC_STATS(mul_s);
1695 handler.b = ieee754sp_mul;
1698 MIPS_FPU_EMU_INC_STATS(div_s);
1699 handler.b = ieee754sp_div;
1704 if (!cpu_has_mips_2_3_4_5_r)
1707 MIPS_FPU_EMU_INC_STATS(sqrt_s);
1708 handler.u = ieee754sp_sqrt;
1712 * Note that on some MIPS IV implementations such as the
1713 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1714 * achieve full IEEE-754 accuracy - however this emulator does.
1717 if (!cpu_has_mips_4_5_64_r2_r6)
1720 MIPS_FPU_EMU_INC_STATS(rsqrt_s);
1721 handler.u = fpemu_sp_rsqrt;
1725 if (!cpu_has_mips_4_5_64_r2_r6)
1728 MIPS_FPU_EMU_INC_STATS(recip_s);
1729 handler.u = fpemu_sp_recip;
1733 if (!cpu_has_mips_4_5_r)
1736 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1737 if (((ctx->fcr31 & cond) != 0) !=
1738 ((MIPSInst_FT(ir) & 1) != 0))
1740 SPFROMREG(rv.s, MIPSInst_FS(ir));
1744 if (!cpu_has_mips_4_5_r)
1747 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1749 SPFROMREG(rv.s, MIPSInst_FS(ir));
1753 if (!cpu_has_mips_4_5_r)
1756 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1758 SPFROMREG(rv.s, MIPSInst_FS(ir));
1762 if (!cpu_has_mips_r6)
1765 MIPS_FPU_EMU_INC_STATS(seleqz_s);
1766 SPFROMREG(rv.s, MIPSInst_FT(ir));
1770 SPFROMREG(rv.s, MIPSInst_FS(ir));
1774 if (!cpu_has_mips_r6)
1777 MIPS_FPU_EMU_INC_STATS(selnez_s);
1778 SPFROMREG(rv.s, MIPSInst_FT(ir));
1780 SPFROMREG(rv.s, MIPSInst_FS(ir));
1786 union ieee754sp ft, fs, fd;
1788 if (!cpu_has_mips_r6)
1791 MIPS_FPU_EMU_INC_STATS(maddf_s);
1792 SPFROMREG(ft, MIPSInst_FT(ir));
1793 SPFROMREG(fs, MIPSInst_FS(ir));
1794 SPFROMREG(fd, MIPSInst_FD(ir));
1795 rv.s = ieee754sp_maddf(fd, fs, ft);
1800 union ieee754sp ft, fs, fd;
1802 if (!cpu_has_mips_r6)
1805 MIPS_FPU_EMU_INC_STATS(msubf_s);
1806 SPFROMREG(ft, MIPSInst_FT(ir));
1807 SPFROMREG(fs, MIPSInst_FS(ir));
1808 SPFROMREG(fd, MIPSInst_FD(ir));
1809 rv.s = ieee754sp_msubf(fd, fs, ft);
1816 if (!cpu_has_mips_r6)
1819 MIPS_FPU_EMU_INC_STATS(rint_s);
1820 SPFROMREG(fs, MIPSInst_FS(ir));
1821 rv.s = ieee754sp_rint(fs);
1828 if (!cpu_has_mips_r6)
1831 MIPS_FPU_EMU_INC_STATS(class_s);
1832 SPFROMREG(fs, MIPSInst_FS(ir));
1833 rv.w = ieee754sp_2008class(fs);
1839 union ieee754sp fs, ft;
1841 if (!cpu_has_mips_r6)
1844 MIPS_FPU_EMU_INC_STATS(min_s);
1845 SPFROMREG(ft, MIPSInst_FT(ir));
1846 SPFROMREG(fs, MIPSInst_FS(ir));
1847 rv.s = ieee754sp_fmin(fs, ft);
1852 union ieee754sp fs, ft;
1854 if (!cpu_has_mips_r6)
1857 MIPS_FPU_EMU_INC_STATS(mina_s);
1858 SPFROMREG(ft, MIPSInst_FT(ir));
1859 SPFROMREG(fs, MIPSInst_FS(ir));
1860 rv.s = ieee754sp_fmina(fs, ft);
1865 union ieee754sp fs, ft;
1867 if (!cpu_has_mips_r6)
1870 MIPS_FPU_EMU_INC_STATS(max_s);
1871 SPFROMREG(ft, MIPSInst_FT(ir));
1872 SPFROMREG(fs, MIPSInst_FS(ir));
1873 rv.s = ieee754sp_fmax(fs, ft);
1878 union ieee754sp fs, ft;
1880 if (!cpu_has_mips_r6)
1883 MIPS_FPU_EMU_INC_STATS(maxa_s);
1884 SPFROMREG(ft, MIPSInst_FT(ir));
1885 SPFROMREG(fs, MIPSInst_FS(ir));
1886 rv.s = ieee754sp_fmaxa(fs, ft);
1891 MIPS_FPU_EMU_INC_STATS(abs_s);
1892 handler.u = ieee754sp_abs;
1896 MIPS_FPU_EMU_INC_STATS(neg_s);
1897 handler.u = ieee754sp_neg;
1902 MIPS_FPU_EMU_INC_STATS(mov_s);
1903 SPFROMREG(rv.s, MIPSInst_FS(ir));
1906 /* binary op on handler */
1908 SPFROMREG(fs, MIPSInst_FS(ir));
1909 SPFROMREG(ft, MIPSInst_FT(ir));
1911 rv.s = (*handler.b) (fs, ft);
1914 SPFROMREG(fs, MIPSInst_FS(ir));
1915 rv.s = (*handler.u) (fs);
1918 if (ieee754_cxtest(IEEE754_INEXACT)) {
1919 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1920 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1922 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1923 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1924 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1926 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1927 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1928 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1930 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1931 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1932 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1934 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1935 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1936 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1940 /* unary conv ops */
1942 return SIGILL; /* not defined */
1945 MIPS_FPU_EMU_INC_STATS(cvt_d_s);
1946 SPFROMREG(fs, MIPSInst_FS(ir));
1947 rv.d = ieee754dp_fsp(fs);
1952 MIPS_FPU_EMU_INC_STATS(cvt_w_s);
1953 SPFROMREG(fs, MIPSInst_FS(ir));
1954 rv.w = ieee754sp_tint(fs);
1962 if (!cpu_has_mips_2_3_4_5_r)
1965 if (MIPSInst_FUNC(ir) == fceil_op)
1966 MIPS_FPU_EMU_INC_STATS(ceil_w_s);
1967 if (MIPSInst_FUNC(ir) == ffloor_op)
1968 MIPS_FPU_EMU_INC_STATS(floor_w_s);
1969 if (MIPSInst_FUNC(ir) == fround_op)
1970 MIPS_FPU_EMU_INC_STATS(round_w_s);
1971 if (MIPSInst_FUNC(ir) == ftrunc_op)
1972 MIPS_FPU_EMU_INC_STATS(trunc_w_s);
1974 oldrm = ieee754_csr.rm;
1975 SPFROMREG(fs, MIPSInst_FS(ir));
1976 ieee754_csr.rm = MIPSInst_FUNC(ir);
1977 rv.w = ieee754sp_tint(fs);
1978 ieee754_csr.rm = oldrm;
1983 if (!cpu_has_mips_r6)
1986 MIPS_FPU_EMU_INC_STATS(sel_s);
1987 SPFROMREG(fd, MIPSInst_FD(ir));
1989 SPFROMREG(rv.s, MIPSInst_FT(ir));
1991 SPFROMREG(rv.s, MIPSInst_FS(ir));
1995 if (!cpu_has_mips_3_4_5_64_r2_r6)
1998 MIPS_FPU_EMU_INC_STATS(cvt_l_s);
1999 SPFROMREG(fs, MIPSInst_FS(ir));
2000 rv.l = ieee754sp_tlong(fs);
2008 if (!cpu_has_mips_3_4_5_64_r2_r6)
2011 if (MIPSInst_FUNC(ir) == fceill_op)
2012 MIPS_FPU_EMU_INC_STATS(ceil_l_s);
2013 if (MIPSInst_FUNC(ir) == ffloorl_op)
2014 MIPS_FPU_EMU_INC_STATS(floor_l_s);
2015 if (MIPSInst_FUNC(ir) == froundl_op)
2016 MIPS_FPU_EMU_INC_STATS(round_l_s);
2017 if (MIPSInst_FUNC(ir) == ftruncl_op)
2018 MIPS_FPU_EMU_INC_STATS(trunc_l_s);
2020 oldrm = ieee754_csr.rm;
2021 SPFROMREG(fs, MIPSInst_FS(ir));
2022 ieee754_csr.rm = MIPSInst_FUNC(ir);
2023 rv.l = ieee754sp_tlong(fs);
2024 ieee754_csr.rm = oldrm;
2029 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2031 union ieee754sp fs, ft;
2033 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2034 SPFROMREG(fs, MIPSInst_FS(ir));
2035 SPFROMREG(ft, MIPSInst_FT(ir));
2036 rv.w = ieee754sp_cmp(fs, ft,
2037 cmptab[cmpop & 0x7], cmpop & 0x8);
2039 if ((cmpop & 0x8) && ieee754_cxtest
2040 (IEEE754_INVALID_OPERATION))
2041 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2053 union ieee754dp fd, fs, ft;
2055 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2056 union ieee754dp(*u) (union ieee754dp);
2059 switch (MIPSInst_FUNC(ir)) {
2062 MIPS_FPU_EMU_INC_STATS(add_d);
2063 handler.b = ieee754dp_add;
2066 MIPS_FPU_EMU_INC_STATS(sub_d);
2067 handler.b = ieee754dp_sub;
2070 MIPS_FPU_EMU_INC_STATS(mul_d);
2071 handler.b = ieee754dp_mul;
2074 MIPS_FPU_EMU_INC_STATS(div_d);
2075 handler.b = ieee754dp_div;
2080 if (!cpu_has_mips_2_3_4_5_r)
2083 MIPS_FPU_EMU_INC_STATS(sqrt_d);
2084 handler.u = ieee754dp_sqrt;
2087 * Note that on some MIPS IV implementations such as the
2088 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2089 * achieve full IEEE-754 accuracy - however this emulator does.
2092 if (!cpu_has_mips_4_5_64_r2_r6)
2095 MIPS_FPU_EMU_INC_STATS(rsqrt_d);
2096 handler.u = fpemu_dp_rsqrt;
2099 if (!cpu_has_mips_4_5_64_r2_r6)
2102 MIPS_FPU_EMU_INC_STATS(recip_d);
2103 handler.u = fpemu_dp_recip;
2106 if (!cpu_has_mips_4_5_r)
2109 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2110 if (((ctx->fcr31 & cond) != 0) !=
2111 ((MIPSInst_FT(ir) & 1) != 0))
2113 DPFROMREG(rv.d, MIPSInst_FS(ir));
2116 if (!cpu_has_mips_4_5_r)
2119 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2121 DPFROMREG(rv.d, MIPSInst_FS(ir));
2124 if (!cpu_has_mips_4_5_r)
2127 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2129 DPFROMREG(rv.d, MIPSInst_FS(ir));
2133 if (!cpu_has_mips_r6)
2136 MIPS_FPU_EMU_INC_STATS(seleqz_d);
2137 DPFROMREG(rv.d, MIPSInst_FT(ir));
2141 DPFROMREG(rv.d, MIPSInst_FS(ir));
2145 if (!cpu_has_mips_r6)
2148 MIPS_FPU_EMU_INC_STATS(selnez_d);
2149 DPFROMREG(rv.d, MIPSInst_FT(ir));
2151 DPFROMREG(rv.d, MIPSInst_FS(ir));
2157 union ieee754dp ft, fs, fd;
2159 if (!cpu_has_mips_r6)
2162 MIPS_FPU_EMU_INC_STATS(maddf_d);
2163 DPFROMREG(ft, MIPSInst_FT(ir));
2164 DPFROMREG(fs, MIPSInst_FS(ir));
2165 DPFROMREG(fd, MIPSInst_FD(ir));
2166 rv.d = ieee754dp_maddf(fd, fs, ft);
2171 union ieee754dp ft, fs, fd;
2173 if (!cpu_has_mips_r6)
2176 MIPS_FPU_EMU_INC_STATS(msubf_d);
2177 DPFROMREG(ft, MIPSInst_FT(ir));
2178 DPFROMREG(fs, MIPSInst_FS(ir));
2179 DPFROMREG(fd, MIPSInst_FD(ir));
2180 rv.d = ieee754dp_msubf(fd, fs, ft);
2187 if (!cpu_has_mips_r6)
2190 MIPS_FPU_EMU_INC_STATS(rint_d);
2191 DPFROMREG(fs, MIPSInst_FS(ir));
2192 rv.d = ieee754dp_rint(fs);
2199 if (!cpu_has_mips_r6)
2202 MIPS_FPU_EMU_INC_STATS(class_d);
2203 DPFROMREG(fs, MIPSInst_FS(ir));
2204 rv.l = ieee754dp_2008class(fs);
2210 union ieee754dp fs, ft;
2212 if (!cpu_has_mips_r6)
2215 MIPS_FPU_EMU_INC_STATS(min_d);
2216 DPFROMREG(ft, MIPSInst_FT(ir));
2217 DPFROMREG(fs, MIPSInst_FS(ir));
2218 rv.d = ieee754dp_fmin(fs, ft);
2223 union ieee754dp fs, ft;
2225 if (!cpu_has_mips_r6)
2228 MIPS_FPU_EMU_INC_STATS(mina_d);
2229 DPFROMREG(ft, MIPSInst_FT(ir));
2230 DPFROMREG(fs, MIPSInst_FS(ir));
2231 rv.d = ieee754dp_fmina(fs, ft);
2236 union ieee754dp fs, ft;
2238 if (!cpu_has_mips_r6)
2241 MIPS_FPU_EMU_INC_STATS(max_d);
2242 DPFROMREG(ft, MIPSInst_FT(ir));
2243 DPFROMREG(fs, MIPSInst_FS(ir));
2244 rv.d = ieee754dp_fmax(fs, ft);
2249 union ieee754dp fs, ft;
2251 if (!cpu_has_mips_r6)
2254 MIPS_FPU_EMU_INC_STATS(maxa_d);
2255 DPFROMREG(ft, MIPSInst_FT(ir));
2256 DPFROMREG(fs, MIPSInst_FS(ir));
2257 rv.d = ieee754dp_fmaxa(fs, ft);
2262 MIPS_FPU_EMU_INC_STATS(abs_d);
2263 handler.u = ieee754dp_abs;
2267 MIPS_FPU_EMU_INC_STATS(neg_d);
2268 handler.u = ieee754dp_neg;
2273 MIPS_FPU_EMU_INC_STATS(mov_d);
2274 DPFROMREG(rv.d, MIPSInst_FS(ir));
2277 /* binary op on handler */
2279 DPFROMREG(fs, MIPSInst_FS(ir));
2280 DPFROMREG(ft, MIPSInst_FT(ir));
2282 rv.d = (*handler.b) (fs, ft);
2285 DPFROMREG(fs, MIPSInst_FS(ir));
2286 rv.d = (*handler.u) (fs);
2293 MIPS_FPU_EMU_INC_STATS(cvt_s_d);
2294 DPFROMREG(fs, MIPSInst_FS(ir));
2295 rv.s = ieee754sp_fdp(fs);
2300 return SIGILL; /* not defined */
2303 MIPS_FPU_EMU_INC_STATS(cvt_w_d);
2304 DPFROMREG(fs, MIPSInst_FS(ir));
2305 rv.w = ieee754dp_tint(fs); /* wrong */
2313 if (!cpu_has_mips_2_3_4_5_r)
2316 if (MIPSInst_FUNC(ir) == fceil_op)
2317 MIPS_FPU_EMU_INC_STATS(ceil_w_d);
2318 if (MIPSInst_FUNC(ir) == ffloor_op)
2319 MIPS_FPU_EMU_INC_STATS(floor_w_d);
2320 if (MIPSInst_FUNC(ir) == fround_op)
2321 MIPS_FPU_EMU_INC_STATS(round_w_d);
2322 if (MIPSInst_FUNC(ir) == ftrunc_op)
2323 MIPS_FPU_EMU_INC_STATS(trunc_w_d);
2325 oldrm = ieee754_csr.rm;
2326 DPFROMREG(fs, MIPSInst_FS(ir));
2327 ieee754_csr.rm = MIPSInst_FUNC(ir);
2328 rv.w = ieee754dp_tint(fs);
2329 ieee754_csr.rm = oldrm;
2334 if (!cpu_has_mips_r6)
2337 MIPS_FPU_EMU_INC_STATS(sel_d);
2338 DPFROMREG(fd, MIPSInst_FD(ir));
2340 DPFROMREG(rv.d, MIPSInst_FT(ir));
2342 DPFROMREG(rv.d, MIPSInst_FS(ir));
2346 if (!cpu_has_mips_3_4_5_64_r2_r6)
2349 MIPS_FPU_EMU_INC_STATS(cvt_l_d);
2350 DPFROMREG(fs, MIPSInst_FS(ir));
2351 rv.l = ieee754dp_tlong(fs);
2359 if (!cpu_has_mips_3_4_5_64_r2_r6)
2362 if (MIPSInst_FUNC(ir) == fceill_op)
2363 MIPS_FPU_EMU_INC_STATS(ceil_l_d);
2364 if (MIPSInst_FUNC(ir) == ffloorl_op)
2365 MIPS_FPU_EMU_INC_STATS(floor_l_d);
2366 if (MIPSInst_FUNC(ir) == froundl_op)
2367 MIPS_FPU_EMU_INC_STATS(round_l_d);
2368 if (MIPSInst_FUNC(ir) == ftruncl_op)
2369 MIPS_FPU_EMU_INC_STATS(trunc_l_d);
2371 oldrm = ieee754_csr.rm;
2372 DPFROMREG(fs, MIPSInst_FS(ir));
2373 ieee754_csr.rm = MIPSInst_FUNC(ir);
2374 rv.l = ieee754dp_tlong(fs);
2375 ieee754_csr.rm = oldrm;
2380 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2382 union ieee754dp fs, ft;
2384 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2385 DPFROMREG(fs, MIPSInst_FS(ir));
2386 DPFROMREG(ft, MIPSInst_FT(ir));
2387 rv.w = ieee754dp_cmp(fs, ft,
2388 cmptab[cmpop & 0x7], cmpop & 0x8);
2393 (IEEE754_INVALID_OPERATION))
2394 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2410 switch (MIPSInst_FUNC(ir)) {
2412 /* convert word to single precision real */
2413 MIPS_FPU_EMU_INC_STATS(cvt_s_w);
2414 SPFROMREG(fs, MIPSInst_FS(ir));
2415 rv.s = ieee754sp_fint(fs.bits);
2419 /* convert word to double precision real */
2420 MIPS_FPU_EMU_INC_STATS(cvt_d_w);
2421 SPFROMREG(fs, MIPSInst_FS(ir));
2422 rv.d = ieee754dp_fint(fs.bits);
2426 /* Emulating the new CMP.condn.fmt R6 instruction */
2427 #define CMPOP_MASK 0x7
2428 #define SIGN_BIT (0x1 << 3)
2429 #define PREDICATE_BIT (0x1 << 4)
2431 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2432 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2433 union ieee754sp fs, ft;
2435 /* This is an R6 only instruction */
2436 if (!cpu_has_mips_r6 ||
2437 (MIPSInst_FUNC(ir) & 0x20))
2441 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2444 MIPS_FPU_EMU_INC_STATS(cmp_af_s);
2447 MIPS_FPU_EMU_INC_STATS(cmp_un_s);
2450 MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
2453 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
2456 MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
2459 MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
2462 MIPS_FPU_EMU_INC_STATS(cmp_le_s);
2465 MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
2471 MIPS_FPU_EMU_INC_STATS(cmp_or_s);
2474 MIPS_FPU_EMU_INC_STATS(cmp_une_s);
2477 MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
2482 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2485 MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
2488 MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
2491 MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
2494 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
2497 MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
2500 MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
2503 MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
2506 MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
2512 MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
2515 MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
2518 MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
2524 /* fmt is w_fmt for single precision so fix it */
2526 /* default to false */
2530 SPFROMREG(fs, MIPSInst_FS(ir));
2531 SPFROMREG(ft, MIPSInst_FT(ir));
2533 /* positive predicates */
2534 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2535 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2537 rv.w = -1; /* true, all 1s */
2539 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2540 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2544 /* negative predicates */
2549 if (ieee754sp_cmp(fs, ft,
2550 negative_cmptab[cmpop],
2552 rv.w = -1; /* true, all 1s */
2554 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2555 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2560 /* Reserved R6 ops */
2572 if (!cpu_has_mips_3_4_5_64_r2_r6)
2575 DIFROMREG(bits, MIPSInst_FS(ir));
2577 switch (MIPSInst_FUNC(ir)) {
2579 /* convert long to single precision real */
2580 MIPS_FPU_EMU_INC_STATS(cvt_s_l);
2581 rv.s = ieee754sp_flong(bits);
2585 /* convert long to double precision real */
2586 MIPS_FPU_EMU_INC_STATS(cvt_d_l);
2587 rv.d = ieee754dp_flong(bits);
2591 /* Emulating the new CMP.condn.fmt R6 instruction */
2592 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2593 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2594 union ieee754dp fs, ft;
2596 if (!cpu_has_mips_r6 ||
2597 (MIPSInst_FUNC(ir) & 0x20))
2601 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2604 MIPS_FPU_EMU_INC_STATS(cmp_af_d);
2607 MIPS_FPU_EMU_INC_STATS(cmp_un_d);
2610 MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
2613 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
2616 MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
2619 MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
2622 MIPS_FPU_EMU_INC_STATS(cmp_le_d);
2625 MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
2631 MIPS_FPU_EMU_INC_STATS(cmp_or_d);
2634 MIPS_FPU_EMU_INC_STATS(cmp_une_d);
2637 MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
2642 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2645 MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
2648 MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
2651 MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
2654 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
2657 MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
2660 MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
2663 MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
2666 MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
2672 MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
2675 MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
2678 MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
2684 /* fmt is l_fmt for double precision so fix it */
2686 /* default to false */
2690 DPFROMREG(fs, MIPSInst_FS(ir));
2691 DPFROMREG(ft, MIPSInst_FT(ir));
2693 /* positive predicates */
2694 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2695 if (ieee754dp_cmp(fs, ft,
2696 cmptab[cmpop], sig))
2697 rv.l = -1LL; /* true, all 1s */
2699 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2700 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2704 /* negative predicates */
2709 if (ieee754dp_cmp(fs, ft,
2710 negative_cmptab[cmpop],
2712 rv.l = -1LL; /* true, all 1s */
2714 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2715 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2720 /* Reserved R6 ops */
2734 * Update the fpu CSR register for this operation.
2735 * If an exception is required, generate a tidy SIGFPE exception,
2736 * without updating the result register.
2737 * Note: cause exception bits do not accumulate, they are rewritten
2738 * for each op; only the flag/sticky bits accumulate.
2740 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2741 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2742 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2747 * Now we can safely write the result back to the register file.
2752 if (cpu_has_mips_4_5_r)
2753 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2755 cbit = FPU_CSR_COND;
2759 ctx->fcr31 &= ~cbit;
2763 DPTOREG(rv.d, MIPSInst_FD(ir));
2766 SPTOREG(rv.s, MIPSInst_FD(ir));
2769 SITOREG(rv.w, MIPSInst_FD(ir));
2772 if (!cpu_has_mips_3_4_5_64_r2_r6)
2775 DITOREG(rv.l, MIPSInst_FD(ir));
2785 * Emulate FPU instructions.
2787 * If we use FPU hardware, then we have been typically called to handle
2788 * an unimplemented operation, such as where an operand is a NaN or
2789 * denormalized. In that case exit the emulation loop after a single
2790 * iteration so as to let hardware execute any subsequent instructions.
2792 * If we have no FPU hardware or it has been disabled, then continue
2793 * emulating floating-point instructions until one of these conditions
2796 * - a non-FPU instruction has been encountered,
2798 * - an attempt to emulate has ended with a signal,
2800 * - the ISA mode has been switched.
2802 * We need to terminate the emulation loop if we got switched to the
2803 * MIPS16 mode, whether supported or not, so that we do not attempt
2804 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2805 * Similarly if we got switched to the microMIPS mode and only the
2806 * regular MIPS mode is supported, so that we do not attempt to emulate
2807 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2808 * we got switched to the regular MIPS mode and only the microMIPS mode
2809 * is supported, so that we do not attempt to emulate a regular MIPS
2810 * instruction that should cause an Address Error exception instead.
2811 * For simplicity we always terminate upon an ISA mode switch.
2813 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2814 int has_fpu, void __user **fault_addr)
2816 unsigned long oldepc, prevepc;
2817 struct mm_decoded_insn dec_insn;
2823 * Initialize context if it hasn't been used already, otherwise ensure
2824 * it has been saved to struct thread_struct.
2826 if (!init_fp_ctx(current))
2829 oldepc = xcp->cp0_epc;
2831 prevepc = xcp->cp0_epc;
2833 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2835 * Get next 2 microMIPS instructions and convert them
2836 * into 32-bit instructions.
2838 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2839 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2840 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2841 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2842 MIPS_FPU_EMU_INC_STATS(errors);
2847 /* Get first instruction. */
2848 if (mm_insn_16bit(*instr_ptr)) {
2849 /* Duplicate the half-word. */
2850 dec_insn.insn = (*instr_ptr << 16) |
2852 /* 16-bit instruction. */
2853 dec_insn.pc_inc = 2;
2856 dec_insn.insn = (*instr_ptr << 16) |
2858 /* 32-bit instruction. */
2859 dec_insn.pc_inc = 4;
2862 /* Get second instruction. */
2863 if (mm_insn_16bit(*instr_ptr)) {
2864 /* Duplicate the half-word. */
2865 dec_insn.next_insn = (*instr_ptr << 16) |
2867 /* 16-bit instruction. */
2868 dec_insn.next_pc_inc = 2;
2870 dec_insn.next_insn = (*instr_ptr << 16) |
2872 /* 32-bit instruction. */
2873 dec_insn.next_pc_inc = 4;
2875 dec_insn.micro_mips_mode = 1;
2877 if ((get_user(dec_insn.insn,
2878 (mips_instruction __user *) xcp->cp0_epc)) ||
2879 (get_user(dec_insn.next_insn,
2880 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2881 MIPS_FPU_EMU_INC_STATS(errors);
2884 dec_insn.pc_inc = 4;
2885 dec_insn.next_pc_inc = 4;
2886 dec_insn.micro_mips_mode = 0;
2889 if ((dec_insn.insn == 0) ||
2890 ((dec_insn.pc_inc == 2) &&
2891 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2892 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2895 * The 'ieee754_csr' is an alias of ctx->fcr31.
2896 * No need to copy ctx->fcr31 to ieee754_csr.
2898 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2906 * We have to check for the ISA bit explicitly here,
2907 * because `get_isa16_mode' may return 0 if support
2908 * for code compression has been globally disabled,
2909 * or otherwise we may produce the wrong signal or
2910 * even proceed successfully where we must not.
2912 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2916 } while (xcp->cp0_epc > prevepc);
2918 /* SIGILL indicates a non-fpu instruction */
2919 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2920 /* but if EPC has advanced, then ignore it */