2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/percpu-defs.h>
39 #include <linux/perf_event.h>
41 #include <asm/branch.h>
43 #include <asm/ptrace.h>
44 #include <asm/signal.h>
45 #include <linux/uaccess.h>
47 #include <asm/cpu-info.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
51 #include <asm/mips-r2-to-r6-emul.h>
55 /* Function which emulates a floating point instruction. */
57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
60 static int fpux_emu(struct pt_regs *,
61 struct mips_fpu_struct *, mips_instruction, void __user **);
63 /* Control registers */
65 #define FPCREG_RID 0 /* $0 = revision id */
66 #define FPCREG_FCCR 25 /* $25 = fccr */
67 #define FPCREG_FEXR 26 /* $26 = fexr */
68 #define FPCREG_FENR 28 /* $28 = fenr */
69 #define FPCREG_CSR 31 /* $31 = csr */
71 /* convert condition code register number to csr bit */
72 const unsigned int fpucondbit[8] = {
83 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
84 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
85 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
86 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
87 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
90 * This functions translates a 32-bit microMIPS instruction
91 * into a 32-bit MIPS32 instruction. Returns 0 on success
92 * and SIGILL otherwise.
94 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 union mips_instruction insn = *insn_ptr;
97 union mips_instruction mips32_insn = insn;
100 switch (insn.mm_i_format.opcode) {
102 mips32_insn.mm_i_format.opcode = ldc1_op;
103 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
104 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
107 mips32_insn.mm_i_format.opcode = lwc1_op;
108 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
109 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
112 mips32_insn.mm_i_format.opcode = sdc1_op;
113 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
114 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
117 mips32_insn.mm_i_format.opcode = swc1_op;
118 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
119 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
122 /* NOTE: offset is << by 1 if in microMIPS mode. */
123 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
124 (insn.mm_i_format.rt == mm_bc1t_op)) {
125 mips32_insn.fb_format.opcode = cop1_op;
126 mips32_insn.fb_format.bc = bc_op;
127 mips32_insn.fb_format.flag =
128 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
133 switch (insn.mm_fp0_format.func) {
142 op = insn.mm_fp0_format.func;
143 if (op == mm_32f_01_op)
145 else if (op == mm_32f_11_op)
147 else if (op == mm_32f_02_op)
149 else if (op == mm_32f_12_op)
151 else if (op == mm_32f_41_op)
153 else if (op == mm_32f_51_op)
155 else if (op == mm_32f_42_op)
159 mips32_insn.fp6_format.opcode = cop1x_op;
160 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
161 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
162 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
163 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
164 mips32_insn.fp6_format.func = func;
167 func = -1; /* Invalid */
168 op = insn.mm_fp5_format.op & 0x7;
169 if (op == mm_ldxc1_op)
171 else if (op == mm_sdxc1_op)
173 else if (op == mm_lwxc1_op)
175 else if (op == mm_swxc1_op)
179 mips32_insn.r_format.opcode = cop1x_op;
180 mips32_insn.r_format.rs =
181 insn.mm_fp5_format.base;
182 mips32_insn.r_format.rt =
183 insn.mm_fp5_format.index;
184 mips32_insn.r_format.rd = 0;
185 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
186 mips32_insn.r_format.func = func;
191 op = -1; /* Invalid */
192 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 else if (insn.mm_fp2_format.op == mm_fmovf_op)
197 mips32_insn.fp0_format.opcode = cop1_op;
198 mips32_insn.fp0_format.fmt =
199 sdps_format[insn.mm_fp2_format.fmt];
200 mips32_insn.fp0_format.ft =
201 (insn.mm_fp2_format.cc<<2) + op;
202 mips32_insn.fp0_format.fs =
203 insn.mm_fp2_format.fs;
204 mips32_insn.fp0_format.fd =
205 insn.mm_fp2_format.fd;
206 mips32_insn.fp0_format.func = fmovc_op;
211 func = -1; /* Invalid */
212 if (insn.mm_fp0_format.op == mm_fadd_op)
214 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 else if (insn.mm_fp0_format.op == mm_fdiv_op)
221 mips32_insn.fp0_format.opcode = cop1_op;
222 mips32_insn.fp0_format.fmt =
223 sdps_format[insn.mm_fp0_format.fmt];
224 mips32_insn.fp0_format.ft =
225 insn.mm_fp0_format.ft;
226 mips32_insn.fp0_format.fs =
227 insn.mm_fp0_format.fs;
228 mips32_insn.fp0_format.fd =
229 insn.mm_fp0_format.fd;
230 mips32_insn.fp0_format.func = func;
235 func = -1; /* Invalid */
236 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 else if (insn.mm_fp0_format.op == mm_fmovz_op)
241 mips32_insn.fp0_format.opcode = cop1_op;
242 mips32_insn.fp0_format.fmt =
243 sdps_format[insn.mm_fp0_format.fmt];
244 mips32_insn.fp0_format.ft =
245 insn.mm_fp0_format.ft;
246 mips32_insn.fp0_format.fs =
247 insn.mm_fp0_format.fs;
248 mips32_insn.fp0_format.fd =
249 insn.mm_fp0_format.fd;
250 mips32_insn.fp0_format.func = func;
254 case mm_32f_73_op: /* POOL32FXF */
255 switch (insn.mm_fp1_format.op) {
260 if ((insn.mm_fp1_format.op & 0x7f) ==
265 mips32_insn.r_format.opcode = spec_op;
266 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
267 mips32_insn.r_format.rt =
268 (insn.mm_fp4_format.cc << 2) + op;
269 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
270 mips32_insn.r_format.re = 0;
271 mips32_insn.r_format.func = movc_op;
277 if ((insn.mm_fp1_format.op & 0x7f) ==
280 fmt = swl_format[insn.mm_fp3_format.fmt];
283 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 mips32_insn.fp0_format.opcode = cop1_op;
286 mips32_insn.fp0_format.fmt = fmt;
287 mips32_insn.fp0_format.ft = 0;
288 mips32_insn.fp0_format.fs =
289 insn.mm_fp3_format.fs;
290 mips32_insn.fp0_format.fd =
291 insn.mm_fp3_format.rt;
292 mips32_insn.fp0_format.func = func;
300 if ((insn.mm_fp1_format.op & 0x7f) ==
303 else if ((insn.mm_fp1_format.op & 0x7f) ==
308 mips32_insn.fp0_format.opcode = cop1_op;
309 mips32_insn.fp0_format.fmt =
310 sdps_format[insn.mm_fp3_format.fmt];
311 mips32_insn.fp0_format.ft = 0;
312 mips32_insn.fp0_format.fs =
313 insn.mm_fp3_format.fs;
314 mips32_insn.fp0_format.fd =
315 insn.mm_fp3_format.rt;
316 mips32_insn.fp0_format.func = func;
328 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
348 mips32_insn.fp0_format.opcode = cop1_op;
349 mips32_insn.fp0_format.fmt =
350 sd_format[insn.mm_fp1_format.fmt];
351 mips32_insn.fp0_format.ft = 0;
352 mips32_insn.fp0_format.fs =
353 insn.mm_fp1_format.fs;
354 mips32_insn.fp0_format.fd =
355 insn.mm_fp1_format.rt;
356 mips32_insn.fp0_format.func = func;
361 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
367 mips32_insn.fp0_format.opcode = cop1_op;
368 mips32_insn.fp0_format.fmt =
369 sdps_format[insn.mm_fp1_format.fmt];
370 mips32_insn.fp0_format.ft = 0;
371 mips32_insn.fp0_format.fs =
372 insn.mm_fp1_format.fs;
373 mips32_insn.fp0_format.fd =
374 insn.mm_fp1_format.rt;
375 mips32_insn.fp0_format.func = func;
383 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
395 mips32_insn.fp1_format.opcode = cop1_op;
396 mips32_insn.fp1_format.op = op;
397 mips32_insn.fp1_format.rt =
398 insn.mm_fp1_format.rt;
399 mips32_insn.fp1_format.fs =
400 insn.mm_fp1_format.fs;
401 mips32_insn.fp1_format.fd = 0;
402 mips32_insn.fp1_format.func = 0;
408 case mm_32f_74_op: /* c.cond.fmt */
409 mips32_insn.fp0_format.opcode = cop1_op;
410 mips32_insn.fp0_format.fmt =
411 sdps_format[insn.mm_fp4_format.fmt];
412 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
413 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
414 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
415 mips32_insn.fp0_format.func =
416 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
426 *insn_ptr = mips32_insn;
431 * Redundant with logic already in kernel/branch.c,
432 * embedded in compute_return_epc. At some point,
433 * a single subroutine should be used across both
436 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
437 unsigned long *contpc)
439 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int bit = 0;
445 switch (insn.i_format.opcode) {
447 switch (insn.r_format.func) {
449 if (insn.r_format.rd != 0) {
450 regs->regs[insn.r_format.rd] =
451 regs->cp0_epc + dec_insn.pc_inc +
452 dec_insn.next_pc_inc;
456 /* For R6, JR already emulated in jalr_op */
457 if (NO_R6EMU && insn.r_format.func == jr_op)
459 *contpc = regs->regs[insn.r_format.rs];
464 switch (insn.i_format.rt) {
467 if (NO_R6EMU && (insn.i_format.rs ||
468 insn.i_format.rt == bltzall_op))
471 regs->regs[31] = regs->cp0_epc +
473 dec_insn.next_pc_inc;
480 if ((long)regs->regs[insn.i_format.rs] < 0)
481 *contpc = regs->cp0_epc +
483 (insn.i_format.simmediate << 2);
485 *contpc = regs->cp0_epc +
487 dec_insn.next_pc_inc;
491 if (NO_R6EMU && (insn.i_format.rs ||
492 insn.i_format.rt == bgezall_op))
495 regs->regs[31] = regs->cp0_epc +
497 dec_insn.next_pc_inc;
504 if ((long)regs->regs[insn.i_format.rs] >= 0)
505 *contpc = regs->cp0_epc +
507 (insn.i_format.simmediate << 2);
509 *contpc = regs->cp0_epc +
511 dec_insn.next_pc_inc;
519 regs->regs[31] = regs->cp0_epc +
521 dec_insn.next_pc_inc;
524 *contpc = regs->cp0_epc + dec_insn.pc_inc;
527 *contpc |= (insn.j_format.target << 2);
528 /* Set microMIPS mode bit: XOR for jalx. */
536 if (regs->regs[insn.i_format.rs] ==
537 regs->regs[insn.i_format.rt])
538 *contpc = regs->cp0_epc +
540 (insn.i_format.simmediate << 2);
542 *contpc = regs->cp0_epc +
544 dec_insn.next_pc_inc;
551 if (regs->regs[insn.i_format.rs] !=
552 regs->regs[insn.i_format.rt])
553 *contpc = regs->cp0_epc +
555 (insn.i_format.simmediate << 2);
557 *contpc = regs->cp0_epc +
559 dec_insn.next_pc_inc;
562 if (!insn.i_format.rt && NO_R6EMU)
568 * Compact branches for R6 for the
569 * blez and blezl opcodes.
570 * BLEZ | rs = 0 | rt != 0 == BLEZALC
571 * BLEZ | rs = rt != 0 == BGEZALC
572 * BLEZ | rs != 0 | rt != 0 == BGEUC
573 * BLEZL | rs = 0 | rt != 0 == BLEZC
574 * BLEZL | rs = rt != 0 == BGEZC
575 * BLEZL | rs != 0 | rt != 0 == BGEC
577 * For real BLEZ{,L}, rt is always 0.
579 if (cpu_has_mips_r6 && insn.i_format.rt) {
580 if ((insn.i_format.opcode == blez_op) &&
581 ((!insn.i_format.rs && insn.i_format.rt) ||
582 (insn.i_format.rs == insn.i_format.rt)))
583 regs->regs[31] = regs->cp0_epc +
585 *contpc = regs->cp0_epc + dec_insn.pc_inc +
586 dec_insn.next_pc_inc;
590 if ((long)regs->regs[insn.i_format.rs] <= 0)
591 *contpc = regs->cp0_epc +
593 (insn.i_format.simmediate << 2);
595 *contpc = regs->cp0_epc +
597 dec_insn.next_pc_inc;
600 if (!insn.i_format.rt && NO_R6EMU)
605 * Compact branches for R6 for the
606 * bgtz and bgtzl opcodes.
607 * BGTZ | rs = 0 | rt != 0 == BGTZALC
608 * BGTZ | rs = rt != 0 == BLTZALC
609 * BGTZ | rs != 0 | rt != 0 == BLTUC
610 * BGTZL | rs = 0 | rt != 0 == BGTZC
611 * BGTZL | rs = rt != 0 == BLTZC
612 * BGTZL | rs != 0 | rt != 0 == BLTC
614 * *ZALC varint for BGTZ &&& rt != 0
615 * For real GTZ{,L}, rt is always 0.
617 if (cpu_has_mips_r6 && insn.i_format.rt) {
618 if ((insn.i_format.opcode == blez_op) &&
619 ((!insn.i_format.rs && insn.i_format.rt) ||
620 (insn.i_format.rs == insn.i_format.rt)))
621 regs->regs[31] = regs->cp0_epc +
623 *contpc = regs->cp0_epc + dec_insn.pc_inc +
624 dec_insn.next_pc_inc;
629 if ((long)regs->regs[insn.i_format.rs] > 0)
630 *contpc = regs->cp0_epc +
632 (insn.i_format.simmediate << 2);
634 *contpc = regs->cp0_epc +
636 dec_insn.next_pc_inc;
640 if (!cpu_has_mips_r6)
642 if (insn.i_format.rt && !insn.i_format.rs)
643 regs->regs[31] = regs->cp0_epc + 4;
644 *contpc = regs->cp0_epc + dec_insn.pc_inc +
645 dec_insn.next_pc_inc;
648 #ifdef CONFIG_CPU_CAVIUM_OCTEON
649 case lwc2_op: /* This is bbit0 on Octeon */
650 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
651 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
653 *contpc = regs->cp0_epc + 8;
655 case ldc2_op: /* This is bbit032 on Octeon */
656 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
657 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
659 *contpc = regs->cp0_epc + 8;
661 case swc2_op: /* This is bbit1 on Octeon */
662 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
663 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
665 *contpc = regs->cp0_epc + 8;
667 case sdc2_op: /* This is bbit132 on Octeon */
668 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
669 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
671 *contpc = regs->cp0_epc + 8;
676 * Only valid for MIPS R6 but we can still end up
677 * here from a broken userland so just tell emulator
678 * this is not a branch and let it break later on.
680 if (!cpu_has_mips_r6)
682 *contpc = regs->cp0_epc + dec_insn.pc_inc +
683 dec_insn.next_pc_inc;
687 if (!cpu_has_mips_r6)
689 regs->regs[31] = regs->cp0_epc + 4;
690 *contpc = regs->cp0_epc + dec_insn.pc_inc +
691 dec_insn.next_pc_inc;
695 if (!cpu_has_mips_r6)
697 *contpc = regs->cp0_epc + dec_insn.pc_inc +
698 dec_insn.next_pc_inc;
702 if (!cpu_has_mips_r6)
704 if (!insn.i_format.rs)
705 regs->regs[31] = regs->cp0_epc + 4;
706 *contpc = regs->cp0_epc + dec_insn.pc_inc +
707 dec_insn.next_pc_inc;
713 /* Need to check for R6 bc1nez and bc1eqz branches */
714 if (cpu_has_mips_r6 &&
715 ((insn.i_format.rs == bc1eqz_op) ||
716 (insn.i_format.rs == bc1nez_op))) {
718 fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
719 bit0 = get_fpr32(fpr, 0) & 0x1;
720 switch (insn.i_format.rs) {
729 *contpc = regs->cp0_epc +
731 (insn.i_format.simmediate << 2);
733 *contpc = regs->cp0_epc +
735 dec_insn.next_pc_inc;
739 /* R2/R6 compatible cop1 instruction */
743 if (insn.i_format.rs == bc_op) {
746 fcr31 = read_32bit_cp1_register(CP1_STATUS);
748 fcr31 = current->thread.fpu.fcr31;
751 bit = (insn.i_format.rt >> 2);
754 switch (insn.i_format.rt & 3) {
757 if (~fcr31 & (1 << bit))
758 *contpc = regs->cp0_epc +
760 (insn.i_format.simmediate << 2);
762 *contpc = regs->cp0_epc +
764 dec_insn.next_pc_inc;
768 if (fcr31 & (1 << bit))
769 *contpc = regs->cp0_epc +
771 (insn.i_format.simmediate << 2);
773 *contpc = regs->cp0_epc +
775 dec_insn.next_pc_inc;
785 * In the Linux kernel, we support selection of FPR format on the
786 * basis of the Status.FR bit. If an FPU is not present, the FR bit
787 * is hardwired to zero, which would imply a 32-bit FPU even for
788 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
789 * FPU emu is slow and bulky and optimizing this function offers fairly
790 * sizeable benefits so we try to be clever and make this function return
791 * a constant whenever possible, that is on 64-bit kernels without O32
792 * compatibility enabled and on 32-bit without 64-bit FPU support.
794 static inline int cop1_64bit(struct pt_regs *xcp)
796 if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
798 else if (IS_ENABLED(CONFIG_32BIT) &&
799 !IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
802 return !test_thread_flag(TIF_32BIT_FPREGS);
805 static inline bool hybrid_fprs(void)
807 return test_thread_flag(TIF_HYBRID_FPREGS);
810 #define SIFROMREG(si, x) \
812 if (cop1_64bit(xcp) && !hybrid_fprs()) \
813 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
815 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
818 #define SITOREG(si, x) \
820 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
822 set_fpr32(&ctx->fpr[x], 0, si); \
823 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
824 set_fpr32(&ctx->fpr[x], i, 0); \
826 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
830 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
832 #define SITOHREG(si, x) \
835 set_fpr32(&ctx->fpr[x], 1, si); \
836 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
837 set_fpr32(&ctx->fpr[x], i, 0); \
840 #define DIFROMREG(di, x) \
841 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
843 #define DITOREG(di, x) \
845 unsigned int fpr, i; \
846 fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
847 set_fpr64(&ctx->fpr[fpr], 0, di); \
848 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
849 set_fpr64(&ctx->fpr[fpr], i, 0); \
852 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
853 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
854 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
855 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
858 * Emulate a CFC1 instruction.
860 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
863 u32 fcr31 = ctx->fcr31;
866 switch (MIPSInst_RD(ir)) {
869 pr_debug("%p gpr[%d]<-csr=%08x\n",
870 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
876 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
878 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
879 pr_debug("%p gpr[%d]<-enr=%08x\n",
880 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
886 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
887 pr_debug("%p gpr[%d]<-exr=%08x\n",
888 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
894 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
896 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
897 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
898 pr_debug("%p gpr[%d]<-ccr=%08x\n",
899 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
903 value = boot_cpu_data.fpu_id;
911 xcp->regs[MIPSInst_RT(ir)] = value;
915 * Emulate a CTC1 instruction.
917 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
920 u32 fcr31 = ctx->fcr31;
924 if (MIPSInst_RT(ir) == 0)
927 value = xcp->regs[MIPSInst_RT(ir)];
929 switch (MIPSInst_RD(ir)) {
931 pr_debug("%p gpr[%d]->csr=%08x\n",
932 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
934 /* Preserve read-only bits. */
935 mask = boot_cpu_data.fpu_msk31;
936 fcr31 = (value & ~mask) | (fcr31 & mask);
942 pr_debug("%p gpr[%d]->enr=%08x\n",
943 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
945 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
947 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
953 pr_debug("%p gpr[%d]->exr=%08x\n",
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
955 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
956 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
962 pr_debug("%p gpr[%d]->ccr=%08x\n",
963 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
964 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
965 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
967 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
979 * Emulate the single floating point instruction pointed at by EPC.
980 * Two instructions if the instruction is in a branch delay slot.
983 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
984 struct mm_decoded_insn dec_insn, void __user **fault_addr)
986 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
987 unsigned int cond, cbit, bit0;
998 * These are giving gcc a gentle hint about what to expect in
999 * dec_inst in order to do better optimization.
1001 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
1004 /* XXX NEC Vr54xx bug workaround */
1005 if (delay_slot(xcp)) {
1006 if (dec_insn.micro_mips_mode) {
1007 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
1008 clear_delay_slot(xcp);
1010 if (!isBranchInstr(xcp, dec_insn, &contpc))
1011 clear_delay_slot(xcp);
1015 if (delay_slot(xcp)) {
1017 * The instruction to be emulated is in a branch delay slot
1018 * which means that we have to emulate the branch instruction
1019 * BEFORE we do the cop1 instruction.
1021 * This branch could be a COP1 branch, but in that case we
1022 * would have had a trap for that instruction, and would not
1023 * come through this route.
1025 * Linux MIPS branch emulator operates on context, updating the
1028 ir = dec_insn.next_insn; /* process delay slot instr */
1029 pc_inc = dec_insn.next_pc_inc;
1031 ir = dec_insn.insn; /* process current instr */
1032 pc_inc = dec_insn.pc_inc;
1036 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1037 * instructions, we want to convert microMIPS FPU instructions
1038 * into MIPS32 instructions so that we could reuse all of the
1039 * FPU emulation code.
1041 * NOTE: We cannot do this for branch instructions since they
1042 * are not a subset. Example: Cannot emulate a 16-bit
1043 * aligned target address with a MIPS32 instruction.
1045 if (dec_insn.micro_mips_mode) {
1047 * If next instruction is a 16-bit instruction, then it
1048 * it cannot be a FPU instruction. This could happen
1049 * since we can be called for non-FPU instructions.
1051 if ((pc_inc == 2) ||
1052 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1058 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1059 MIPS_FPU_EMU_INC_STATS(emulated);
1060 switch (MIPSInst_OPCODE(ir)) {
1062 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1064 MIPS_FPU_EMU_INC_STATS(loads);
1066 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1067 MIPS_FPU_EMU_INC_STATS(errors);
1071 if (__get_user(dval, dva)) {
1072 MIPS_FPU_EMU_INC_STATS(errors);
1076 DITOREG(dval, MIPSInst_RT(ir));
1080 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1082 MIPS_FPU_EMU_INC_STATS(stores);
1083 DIFROMREG(dval, MIPSInst_RT(ir));
1084 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1085 MIPS_FPU_EMU_INC_STATS(errors);
1089 if (__put_user(dval, dva)) {
1090 MIPS_FPU_EMU_INC_STATS(errors);
1097 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1099 MIPS_FPU_EMU_INC_STATS(loads);
1100 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1101 MIPS_FPU_EMU_INC_STATS(errors);
1105 if (__get_user(wval, wva)) {
1106 MIPS_FPU_EMU_INC_STATS(errors);
1110 SITOREG(wval, MIPSInst_RT(ir));
1114 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1116 MIPS_FPU_EMU_INC_STATS(stores);
1117 SIFROMREG(wval, MIPSInst_RT(ir));
1118 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1119 MIPS_FPU_EMU_INC_STATS(errors);
1123 if (__put_user(wval, wva)) {
1124 MIPS_FPU_EMU_INC_STATS(errors);
1131 switch (MIPSInst_RS(ir)) {
1133 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1136 /* copregister fs -> gpr[rt] */
1137 if (MIPSInst_RT(ir) != 0) {
1138 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1144 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1147 /* copregister fs <- rt */
1148 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1152 if (!cpu_has_mips_r2_r6)
1155 /* copregister rd -> gpr[rt] */
1156 if (MIPSInst_RT(ir) != 0) {
1157 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1163 if (!cpu_has_mips_r2_r6)
1166 /* copregister rd <- gpr[rt] */
1167 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1171 /* copregister rd -> gpr[rt] */
1172 if (MIPSInst_RT(ir) != 0) {
1173 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1179 /* copregister rd <- rt */
1180 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1184 /* cop control register rd -> gpr[rt] */
1185 cop1_cfc(xcp, ctx, ir);
1189 /* copregister rd <- rt */
1190 cop1_ctc(xcp, ctx, ir);
1191 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1198 if (!cpu_has_mips_r6 || delay_slot(xcp))
1203 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1204 bit0 = get_fpr32(fpr, 0) & 0x1;
1205 switch (MIPSInst_RS(ir)) {
1207 MIPS_FPU_EMU_INC_STATS(bc1eqz);
1211 MIPS_FPU_EMU_INC_STATS(bc1nez);
1218 if (delay_slot(xcp))
1221 if (cpu_has_mips_4_5_r)
1222 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1224 cbit = FPU_CSR_COND;
1225 cond = ctx->fcr31 & cbit;
1228 switch (MIPSInst_RT(ir) & 3) {
1230 if (cpu_has_mips_2_3_4_5_r)
1237 if (cpu_has_mips_2_3_4_5_r)
1244 MIPS_FPU_EMU_INC_STATS(branches);
1245 set_delay_slot(xcp);
1248 * Branch taken: emulate dslot instruction
1253 * Remember EPC at the branch to point back
1254 * at so that any delay-slot instruction
1255 * signal is not silently ignored.
1257 bcpc = xcp->cp0_epc;
1258 xcp->cp0_epc += dec_insn.pc_inc;
1260 contpc = MIPSInst_SIMM(ir);
1261 ir = dec_insn.next_insn;
1262 if (dec_insn.micro_mips_mode) {
1263 contpc = (xcp->cp0_epc + (contpc << 1));
1265 /* If 16-bit instruction, not FPU. */
1266 if ((dec_insn.next_pc_inc == 2) ||
1267 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1270 * Since this instruction will
1271 * be put on the stack with
1272 * 32-bit words, get around
1273 * this problem by putting a
1274 * NOP16 as the second one.
1276 if (dec_insn.next_pc_inc == 2)
1277 ir = (ir & (~0xffff)) | MM_NOP16;
1280 * Single step the non-CP1
1281 * instruction in the dslot.
1283 sig = mips_dsemul(xcp, ir,
1288 xcp->cp0_epc = bcpc;
1290 * SIGILL forces out of
1291 * the emulation loop.
1293 return sig ? sig : SIGILL;
1296 contpc = (xcp->cp0_epc + (contpc << 2));
1298 switch (MIPSInst_OPCODE(ir)) {
1305 if (cpu_has_mips_2_3_4_5_r)
1314 if (cpu_has_mips_4_5_64_r2_r6)
1315 /* its one of ours */
1321 switch (MIPSInst_FUNC(ir)) {
1323 if (cpu_has_mips_4_5_r)
1331 xcp->cp0_epc = bcpc;
1336 * Single step the non-cp1
1337 * instruction in the dslot
1339 sig = mips_dsemul(xcp, ir, bcpc, contpc);
1343 xcp->cp0_epc = bcpc;
1344 /* SIGILL forces out of the emulation loop. */
1345 return sig ? sig : SIGILL;
1346 } else if (likely) { /* branch not taken */
1348 * branch likely nullifies
1349 * dslot if not taken
1351 xcp->cp0_epc += dec_insn.pc_inc;
1352 contpc += dec_insn.pc_inc;
1354 * else continue & execute
1355 * dslot as normal insn
1361 if (!(MIPSInst_RS(ir) & 0x10))
1364 /* a real fpu computation instruction */
1365 sig = fpu_emu(xcp, ctx, ir);
1372 if (!cpu_has_mips_4_5_64_r2_r6)
1375 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1381 if (!cpu_has_mips_4_5_r)
1384 if (MIPSInst_FUNC(ir) != movc_op)
1386 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1387 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1388 xcp->regs[MIPSInst_RD(ir)] =
1389 xcp->regs[MIPSInst_RS(ir)];
1396 xcp->cp0_epc = contpc;
1397 clear_delay_slot(xcp);
1403 * Conversion table from MIPS compare ops 48-63
1404 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1406 static const unsigned char cmptab[8] = {
1407 0, /* cmp_0 (sig) cmp_sf */
1408 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1409 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1410 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1411 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1412 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1413 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1414 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1417 static const unsigned char negative_cmptab[8] = {
1419 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1420 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1421 IEEE754_CLT | IEEE754_CGT,
1427 * Additional MIPS4 instructions
1430 #define DEF3OP(name, p, f1, f2, f3) \
1431 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1432 union ieee754##p s, union ieee754##p t) \
1434 struct _ieee754_csr ieee754_csr_save; \
1436 ieee754_csr_save = ieee754_csr; \
1438 ieee754_csr_save.cx |= ieee754_csr.cx; \
1439 ieee754_csr_save.sx |= ieee754_csr.sx; \
1441 ieee754_csr.cx |= ieee754_csr_save.cx; \
1442 ieee754_csr.sx |= ieee754_csr_save.sx; \
1446 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1448 return ieee754dp_div(ieee754dp_one(0), d);
1451 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1453 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1456 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1458 return ieee754sp_div(ieee754sp_one(0), s);
1461 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1463 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1466 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1467 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1468 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1469 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1470 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1471 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1472 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1473 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1475 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1476 mips_instruction ir, void __user **fault_addr)
1478 unsigned int rcsr = 0; /* resulting csr */
1480 MIPS_FPU_EMU_INC_STATS(cp1xops);
1482 switch (MIPSInst_FMA_FFMT(ir)) {
1483 case s_fmt:{ /* 0 */
1485 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1486 union ieee754sp fd, fr, fs, ft;
1490 switch (MIPSInst_FUNC(ir)) {
1492 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1493 xcp->regs[MIPSInst_FT(ir)]);
1495 MIPS_FPU_EMU_INC_STATS(loads);
1496 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1497 MIPS_FPU_EMU_INC_STATS(errors);
1501 if (__get_user(val, va)) {
1502 MIPS_FPU_EMU_INC_STATS(errors);
1506 SITOREG(val, MIPSInst_FD(ir));
1510 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1511 xcp->regs[MIPSInst_FT(ir)]);
1513 MIPS_FPU_EMU_INC_STATS(stores);
1515 SIFROMREG(val, MIPSInst_FS(ir));
1516 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1517 MIPS_FPU_EMU_INC_STATS(errors);
1521 if (put_user(val, va)) {
1522 MIPS_FPU_EMU_INC_STATS(errors);
1529 handler = fpemu_sp_madd;
1532 handler = fpemu_sp_msub;
1535 handler = fpemu_sp_nmadd;
1538 handler = fpemu_sp_nmsub;
1542 SPFROMREG(fr, MIPSInst_FR(ir));
1543 SPFROMREG(fs, MIPSInst_FS(ir));
1544 SPFROMREG(ft, MIPSInst_FT(ir));
1545 fd = (*handler) (fr, fs, ft);
1546 SPTOREG(fd, MIPSInst_FD(ir));
1549 if (ieee754_cxtest(IEEE754_INEXACT)) {
1550 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1551 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1553 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1554 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1555 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1557 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1558 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1559 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1561 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1562 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1563 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1566 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1567 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1568 /*printk ("SIGFPE: FPU csr = %08x\n",
1581 case d_fmt:{ /* 1 */
1582 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1583 union ieee754dp fd, fr, fs, ft;
1587 switch (MIPSInst_FUNC(ir)) {
1589 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1590 xcp->regs[MIPSInst_FT(ir)]);
1592 MIPS_FPU_EMU_INC_STATS(loads);
1593 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1594 MIPS_FPU_EMU_INC_STATS(errors);
1598 if (__get_user(val, va)) {
1599 MIPS_FPU_EMU_INC_STATS(errors);
1603 DITOREG(val, MIPSInst_FD(ir));
1607 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1608 xcp->regs[MIPSInst_FT(ir)]);
1610 MIPS_FPU_EMU_INC_STATS(stores);
1611 DIFROMREG(val, MIPSInst_FS(ir));
1612 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1613 MIPS_FPU_EMU_INC_STATS(errors);
1617 if (__put_user(val, va)) {
1618 MIPS_FPU_EMU_INC_STATS(errors);
1625 handler = fpemu_dp_madd;
1628 handler = fpemu_dp_msub;
1631 handler = fpemu_dp_nmadd;
1634 handler = fpemu_dp_nmsub;
1638 DPFROMREG(fr, MIPSInst_FR(ir));
1639 DPFROMREG(fs, MIPSInst_FS(ir));
1640 DPFROMREG(ft, MIPSInst_FT(ir));
1641 fd = (*handler) (fr, fs, ft);
1642 DPTOREG(fd, MIPSInst_FD(ir));
1652 if (MIPSInst_FUNC(ir) != pfetch_op)
1655 /* ignore prefx operation */
1668 * Emulate a single COP1 arithmetic instruction.
1670 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1671 mips_instruction ir)
1673 int rfmt; /* resulting format */
1674 unsigned int rcsr = 0; /* resulting csr */
1683 } rv; /* resulting value */
1686 MIPS_FPU_EMU_INC_STATS(cp1ops);
1687 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1688 case s_fmt: { /* 0 */
1690 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1691 union ieee754sp(*u) (union ieee754sp);
1693 union ieee754sp fd, fs, ft;
1695 switch (MIPSInst_FUNC(ir)) {
1698 MIPS_FPU_EMU_INC_STATS(add_s);
1699 handler.b = ieee754sp_add;
1702 MIPS_FPU_EMU_INC_STATS(sub_s);
1703 handler.b = ieee754sp_sub;
1706 MIPS_FPU_EMU_INC_STATS(mul_s);
1707 handler.b = ieee754sp_mul;
1710 MIPS_FPU_EMU_INC_STATS(div_s);
1711 handler.b = ieee754sp_div;
1716 if (!cpu_has_mips_2_3_4_5_r)
1719 MIPS_FPU_EMU_INC_STATS(sqrt_s);
1720 handler.u = ieee754sp_sqrt;
1724 * Note that on some MIPS IV implementations such as the
1725 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1726 * achieve full IEEE-754 accuracy - however this emulator does.
1729 if (!cpu_has_mips_4_5_64_r2_r6)
1732 MIPS_FPU_EMU_INC_STATS(rsqrt_s);
1733 handler.u = fpemu_sp_rsqrt;
1737 if (!cpu_has_mips_4_5_64_r2_r6)
1740 MIPS_FPU_EMU_INC_STATS(recip_s);
1741 handler.u = fpemu_sp_recip;
1745 if (!cpu_has_mips_4_5_r)
1748 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1749 if (((ctx->fcr31 & cond) != 0) !=
1750 ((MIPSInst_FT(ir) & 1) != 0))
1752 SPFROMREG(rv.s, MIPSInst_FS(ir));
1756 if (!cpu_has_mips_4_5_r)
1759 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1761 SPFROMREG(rv.s, MIPSInst_FS(ir));
1765 if (!cpu_has_mips_4_5_r)
1768 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1770 SPFROMREG(rv.s, MIPSInst_FS(ir));
1774 if (!cpu_has_mips_r6)
1777 MIPS_FPU_EMU_INC_STATS(seleqz_s);
1778 SPFROMREG(rv.s, MIPSInst_FT(ir));
1782 SPFROMREG(rv.s, MIPSInst_FS(ir));
1786 if (!cpu_has_mips_r6)
1789 MIPS_FPU_EMU_INC_STATS(selnez_s);
1790 SPFROMREG(rv.s, MIPSInst_FT(ir));
1792 SPFROMREG(rv.s, MIPSInst_FS(ir));
1798 union ieee754sp ft, fs, fd;
1800 if (!cpu_has_mips_r6)
1803 MIPS_FPU_EMU_INC_STATS(maddf_s);
1804 SPFROMREG(ft, MIPSInst_FT(ir));
1805 SPFROMREG(fs, MIPSInst_FS(ir));
1806 SPFROMREG(fd, MIPSInst_FD(ir));
1807 rv.s = ieee754sp_maddf(fd, fs, ft);
1812 union ieee754sp ft, fs, fd;
1814 if (!cpu_has_mips_r6)
1817 MIPS_FPU_EMU_INC_STATS(msubf_s);
1818 SPFROMREG(ft, MIPSInst_FT(ir));
1819 SPFROMREG(fs, MIPSInst_FS(ir));
1820 SPFROMREG(fd, MIPSInst_FD(ir));
1821 rv.s = ieee754sp_msubf(fd, fs, ft);
1828 if (!cpu_has_mips_r6)
1831 MIPS_FPU_EMU_INC_STATS(rint_s);
1832 SPFROMREG(fs, MIPSInst_FS(ir));
1833 rv.s = ieee754sp_rint(fs);
1840 if (!cpu_has_mips_r6)
1843 MIPS_FPU_EMU_INC_STATS(class_s);
1844 SPFROMREG(fs, MIPSInst_FS(ir));
1845 rv.w = ieee754sp_2008class(fs);
1851 union ieee754sp fs, ft;
1853 if (!cpu_has_mips_r6)
1856 MIPS_FPU_EMU_INC_STATS(min_s);
1857 SPFROMREG(ft, MIPSInst_FT(ir));
1858 SPFROMREG(fs, MIPSInst_FS(ir));
1859 rv.s = ieee754sp_fmin(fs, ft);
1864 union ieee754sp fs, ft;
1866 if (!cpu_has_mips_r6)
1869 MIPS_FPU_EMU_INC_STATS(mina_s);
1870 SPFROMREG(ft, MIPSInst_FT(ir));
1871 SPFROMREG(fs, MIPSInst_FS(ir));
1872 rv.s = ieee754sp_fmina(fs, ft);
1877 union ieee754sp fs, ft;
1879 if (!cpu_has_mips_r6)
1882 MIPS_FPU_EMU_INC_STATS(max_s);
1883 SPFROMREG(ft, MIPSInst_FT(ir));
1884 SPFROMREG(fs, MIPSInst_FS(ir));
1885 rv.s = ieee754sp_fmax(fs, ft);
1890 union ieee754sp fs, ft;
1892 if (!cpu_has_mips_r6)
1895 MIPS_FPU_EMU_INC_STATS(maxa_s);
1896 SPFROMREG(ft, MIPSInst_FT(ir));
1897 SPFROMREG(fs, MIPSInst_FS(ir));
1898 rv.s = ieee754sp_fmaxa(fs, ft);
1903 MIPS_FPU_EMU_INC_STATS(abs_s);
1904 handler.u = ieee754sp_abs;
1908 MIPS_FPU_EMU_INC_STATS(neg_s);
1909 handler.u = ieee754sp_neg;
1914 MIPS_FPU_EMU_INC_STATS(mov_s);
1915 SPFROMREG(rv.s, MIPSInst_FS(ir));
1918 /* binary op on handler */
1920 SPFROMREG(fs, MIPSInst_FS(ir));
1921 SPFROMREG(ft, MIPSInst_FT(ir));
1923 rv.s = (*handler.b) (fs, ft);
1926 SPFROMREG(fs, MIPSInst_FS(ir));
1927 rv.s = (*handler.u) (fs);
1930 if (ieee754_cxtest(IEEE754_INEXACT)) {
1931 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1932 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1934 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1935 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1936 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1938 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1939 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1940 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1942 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1943 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1944 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1946 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1947 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1948 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1952 /* unary conv ops */
1954 return SIGILL; /* not defined */
1957 MIPS_FPU_EMU_INC_STATS(cvt_d_s);
1958 SPFROMREG(fs, MIPSInst_FS(ir));
1959 rv.d = ieee754dp_fsp(fs);
1964 MIPS_FPU_EMU_INC_STATS(cvt_w_s);
1965 SPFROMREG(fs, MIPSInst_FS(ir));
1966 rv.w = ieee754sp_tint(fs);
1974 if (!cpu_has_mips_2_3_4_5_r)
1977 if (MIPSInst_FUNC(ir) == fceil_op)
1978 MIPS_FPU_EMU_INC_STATS(ceil_w_s);
1979 if (MIPSInst_FUNC(ir) == ffloor_op)
1980 MIPS_FPU_EMU_INC_STATS(floor_w_s);
1981 if (MIPSInst_FUNC(ir) == fround_op)
1982 MIPS_FPU_EMU_INC_STATS(round_w_s);
1983 if (MIPSInst_FUNC(ir) == ftrunc_op)
1984 MIPS_FPU_EMU_INC_STATS(trunc_w_s);
1986 oldrm = ieee754_csr.rm;
1987 SPFROMREG(fs, MIPSInst_FS(ir));
1988 ieee754_csr.rm = MIPSInst_FUNC(ir);
1989 rv.w = ieee754sp_tint(fs);
1990 ieee754_csr.rm = oldrm;
1995 if (!cpu_has_mips_r6)
1998 MIPS_FPU_EMU_INC_STATS(sel_s);
1999 SPFROMREG(fd, MIPSInst_FD(ir));
2001 SPFROMREG(rv.s, MIPSInst_FT(ir));
2003 SPFROMREG(rv.s, MIPSInst_FS(ir));
2007 if (!cpu_has_mips_3_4_5_64_r2_r6)
2010 MIPS_FPU_EMU_INC_STATS(cvt_l_s);
2011 SPFROMREG(fs, MIPSInst_FS(ir));
2012 rv.l = ieee754sp_tlong(fs);
2020 if (!cpu_has_mips_3_4_5_64_r2_r6)
2023 if (MIPSInst_FUNC(ir) == fceill_op)
2024 MIPS_FPU_EMU_INC_STATS(ceil_l_s);
2025 if (MIPSInst_FUNC(ir) == ffloorl_op)
2026 MIPS_FPU_EMU_INC_STATS(floor_l_s);
2027 if (MIPSInst_FUNC(ir) == froundl_op)
2028 MIPS_FPU_EMU_INC_STATS(round_l_s);
2029 if (MIPSInst_FUNC(ir) == ftruncl_op)
2030 MIPS_FPU_EMU_INC_STATS(trunc_l_s);
2032 oldrm = ieee754_csr.rm;
2033 SPFROMREG(fs, MIPSInst_FS(ir));
2034 ieee754_csr.rm = MIPSInst_FUNC(ir);
2035 rv.l = ieee754sp_tlong(fs);
2036 ieee754_csr.rm = oldrm;
2041 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2043 union ieee754sp fs, ft;
2045 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2046 SPFROMREG(fs, MIPSInst_FS(ir));
2047 SPFROMREG(ft, MIPSInst_FT(ir));
2048 rv.w = ieee754sp_cmp(fs, ft,
2049 cmptab[cmpop & 0x7], cmpop & 0x8);
2051 if ((cmpop & 0x8) && ieee754_cxtest
2052 (IEEE754_INVALID_OPERATION))
2053 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2065 union ieee754dp fd, fs, ft;
2067 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2068 union ieee754dp(*u) (union ieee754dp);
2071 switch (MIPSInst_FUNC(ir)) {
2074 MIPS_FPU_EMU_INC_STATS(add_d);
2075 handler.b = ieee754dp_add;
2078 MIPS_FPU_EMU_INC_STATS(sub_d);
2079 handler.b = ieee754dp_sub;
2082 MIPS_FPU_EMU_INC_STATS(mul_d);
2083 handler.b = ieee754dp_mul;
2086 MIPS_FPU_EMU_INC_STATS(div_d);
2087 handler.b = ieee754dp_div;
2092 if (!cpu_has_mips_2_3_4_5_r)
2095 MIPS_FPU_EMU_INC_STATS(sqrt_d);
2096 handler.u = ieee754dp_sqrt;
2099 * Note that on some MIPS IV implementations such as the
2100 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2101 * achieve full IEEE-754 accuracy - however this emulator does.
2104 if (!cpu_has_mips_4_5_64_r2_r6)
2107 MIPS_FPU_EMU_INC_STATS(rsqrt_d);
2108 handler.u = fpemu_dp_rsqrt;
2111 if (!cpu_has_mips_4_5_64_r2_r6)
2114 MIPS_FPU_EMU_INC_STATS(recip_d);
2115 handler.u = fpemu_dp_recip;
2118 if (!cpu_has_mips_4_5_r)
2121 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2122 if (((ctx->fcr31 & cond) != 0) !=
2123 ((MIPSInst_FT(ir) & 1) != 0))
2125 DPFROMREG(rv.d, MIPSInst_FS(ir));
2128 if (!cpu_has_mips_4_5_r)
2131 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2133 DPFROMREG(rv.d, MIPSInst_FS(ir));
2136 if (!cpu_has_mips_4_5_r)
2139 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2141 DPFROMREG(rv.d, MIPSInst_FS(ir));
2145 if (!cpu_has_mips_r6)
2148 MIPS_FPU_EMU_INC_STATS(seleqz_d);
2149 DPFROMREG(rv.d, MIPSInst_FT(ir));
2153 DPFROMREG(rv.d, MIPSInst_FS(ir));
2157 if (!cpu_has_mips_r6)
2160 MIPS_FPU_EMU_INC_STATS(selnez_d);
2161 DPFROMREG(rv.d, MIPSInst_FT(ir));
2163 DPFROMREG(rv.d, MIPSInst_FS(ir));
2169 union ieee754dp ft, fs, fd;
2171 if (!cpu_has_mips_r6)
2174 MIPS_FPU_EMU_INC_STATS(maddf_d);
2175 DPFROMREG(ft, MIPSInst_FT(ir));
2176 DPFROMREG(fs, MIPSInst_FS(ir));
2177 DPFROMREG(fd, MIPSInst_FD(ir));
2178 rv.d = ieee754dp_maddf(fd, fs, ft);
2183 union ieee754dp ft, fs, fd;
2185 if (!cpu_has_mips_r6)
2188 MIPS_FPU_EMU_INC_STATS(msubf_d);
2189 DPFROMREG(ft, MIPSInst_FT(ir));
2190 DPFROMREG(fs, MIPSInst_FS(ir));
2191 DPFROMREG(fd, MIPSInst_FD(ir));
2192 rv.d = ieee754dp_msubf(fd, fs, ft);
2199 if (!cpu_has_mips_r6)
2202 MIPS_FPU_EMU_INC_STATS(rint_d);
2203 DPFROMREG(fs, MIPSInst_FS(ir));
2204 rv.d = ieee754dp_rint(fs);
2211 if (!cpu_has_mips_r6)
2214 MIPS_FPU_EMU_INC_STATS(class_d);
2215 DPFROMREG(fs, MIPSInst_FS(ir));
2216 rv.l = ieee754dp_2008class(fs);
2222 union ieee754dp fs, ft;
2224 if (!cpu_has_mips_r6)
2227 MIPS_FPU_EMU_INC_STATS(min_d);
2228 DPFROMREG(ft, MIPSInst_FT(ir));
2229 DPFROMREG(fs, MIPSInst_FS(ir));
2230 rv.d = ieee754dp_fmin(fs, ft);
2235 union ieee754dp fs, ft;
2237 if (!cpu_has_mips_r6)
2240 MIPS_FPU_EMU_INC_STATS(mina_d);
2241 DPFROMREG(ft, MIPSInst_FT(ir));
2242 DPFROMREG(fs, MIPSInst_FS(ir));
2243 rv.d = ieee754dp_fmina(fs, ft);
2248 union ieee754dp fs, ft;
2250 if (!cpu_has_mips_r6)
2253 MIPS_FPU_EMU_INC_STATS(max_d);
2254 DPFROMREG(ft, MIPSInst_FT(ir));
2255 DPFROMREG(fs, MIPSInst_FS(ir));
2256 rv.d = ieee754dp_fmax(fs, ft);
2261 union ieee754dp fs, ft;
2263 if (!cpu_has_mips_r6)
2266 MIPS_FPU_EMU_INC_STATS(maxa_d);
2267 DPFROMREG(ft, MIPSInst_FT(ir));
2268 DPFROMREG(fs, MIPSInst_FS(ir));
2269 rv.d = ieee754dp_fmaxa(fs, ft);
2274 MIPS_FPU_EMU_INC_STATS(abs_d);
2275 handler.u = ieee754dp_abs;
2279 MIPS_FPU_EMU_INC_STATS(neg_d);
2280 handler.u = ieee754dp_neg;
2285 MIPS_FPU_EMU_INC_STATS(mov_d);
2286 DPFROMREG(rv.d, MIPSInst_FS(ir));
2289 /* binary op on handler */
2291 DPFROMREG(fs, MIPSInst_FS(ir));
2292 DPFROMREG(ft, MIPSInst_FT(ir));
2294 rv.d = (*handler.b) (fs, ft);
2297 DPFROMREG(fs, MIPSInst_FS(ir));
2298 rv.d = (*handler.u) (fs);
2305 MIPS_FPU_EMU_INC_STATS(cvt_s_d);
2306 DPFROMREG(fs, MIPSInst_FS(ir));
2307 rv.s = ieee754sp_fdp(fs);
2312 return SIGILL; /* not defined */
2315 MIPS_FPU_EMU_INC_STATS(cvt_w_d);
2316 DPFROMREG(fs, MIPSInst_FS(ir));
2317 rv.w = ieee754dp_tint(fs); /* wrong */
2325 if (!cpu_has_mips_2_3_4_5_r)
2328 if (MIPSInst_FUNC(ir) == fceil_op)
2329 MIPS_FPU_EMU_INC_STATS(ceil_w_d);
2330 if (MIPSInst_FUNC(ir) == ffloor_op)
2331 MIPS_FPU_EMU_INC_STATS(floor_w_d);
2332 if (MIPSInst_FUNC(ir) == fround_op)
2333 MIPS_FPU_EMU_INC_STATS(round_w_d);
2334 if (MIPSInst_FUNC(ir) == ftrunc_op)
2335 MIPS_FPU_EMU_INC_STATS(trunc_w_d);
2337 oldrm = ieee754_csr.rm;
2338 DPFROMREG(fs, MIPSInst_FS(ir));
2339 ieee754_csr.rm = MIPSInst_FUNC(ir);
2340 rv.w = ieee754dp_tint(fs);
2341 ieee754_csr.rm = oldrm;
2346 if (!cpu_has_mips_r6)
2349 MIPS_FPU_EMU_INC_STATS(sel_d);
2350 DPFROMREG(fd, MIPSInst_FD(ir));
2352 DPFROMREG(rv.d, MIPSInst_FT(ir));
2354 DPFROMREG(rv.d, MIPSInst_FS(ir));
2358 if (!cpu_has_mips_3_4_5_64_r2_r6)
2361 MIPS_FPU_EMU_INC_STATS(cvt_l_d);
2362 DPFROMREG(fs, MIPSInst_FS(ir));
2363 rv.l = ieee754dp_tlong(fs);
2371 if (!cpu_has_mips_3_4_5_64_r2_r6)
2374 if (MIPSInst_FUNC(ir) == fceill_op)
2375 MIPS_FPU_EMU_INC_STATS(ceil_l_d);
2376 if (MIPSInst_FUNC(ir) == ffloorl_op)
2377 MIPS_FPU_EMU_INC_STATS(floor_l_d);
2378 if (MIPSInst_FUNC(ir) == froundl_op)
2379 MIPS_FPU_EMU_INC_STATS(round_l_d);
2380 if (MIPSInst_FUNC(ir) == ftruncl_op)
2381 MIPS_FPU_EMU_INC_STATS(trunc_l_d);
2383 oldrm = ieee754_csr.rm;
2384 DPFROMREG(fs, MIPSInst_FS(ir));
2385 ieee754_csr.rm = MIPSInst_FUNC(ir);
2386 rv.l = ieee754dp_tlong(fs);
2387 ieee754_csr.rm = oldrm;
2392 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2394 union ieee754dp fs, ft;
2396 cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2397 DPFROMREG(fs, MIPSInst_FS(ir));
2398 DPFROMREG(ft, MIPSInst_FT(ir));
2399 rv.w = ieee754dp_cmp(fs, ft,
2400 cmptab[cmpop & 0x7], cmpop & 0x8);
2405 (IEEE754_INVALID_OPERATION))
2406 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2422 switch (MIPSInst_FUNC(ir)) {
2424 /* convert word to single precision real */
2425 MIPS_FPU_EMU_INC_STATS(cvt_s_w);
2426 SPFROMREG(fs, MIPSInst_FS(ir));
2427 rv.s = ieee754sp_fint(fs.bits);
2431 /* convert word to double precision real */
2432 MIPS_FPU_EMU_INC_STATS(cvt_d_w);
2433 SPFROMREG(fs, MIPSInst_FS(ir));
2434 rv.d = ieee754dp_fint(fs.bits);
2438 /* Emulating the new CMP.condn.fmt R6 instruction */
2439 #define CMPOP_MASK 0x7
2440 #define SIGN_BIT (0x1 << 3)
2441 #define PREDICATE_BIT (0x1 << 4)
2443 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2444 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2445 union ieee754sp fs, ft;
2447 /* This is an R6 only instruction */
2448 if (!cpu_has_mips_r6 ||
2449 (MIPSInst_FUNC(ir) & 0x20))
2453 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2456 MIPS_FPU_EMU_INC_STATS(cmp_af_s);
2459 MIPS_FPU_EMU_INC_STATS(cmp_un_s);
2462 MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
2465 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
2468 MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
2471 MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
2474 MIPS_FPU_EMU_INC_STATS(cmp_le_s);
2477 MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
2483 MIPS_FPU_EMU_INC_STATS(cmp_or_s);
2486 MIPS_FPU_EMU_INC_STATS(cmp_une_s);
2489 MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
2494 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2497 MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
2500 MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
2503 MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
2506 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
2509 MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
2512 MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
2515 MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
2518 MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
2524 MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
2527 MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
2530 MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
2536 /* fmt is w_fmt for single precision so fix it */
2538 /* default to false */
2542 SPFROMREG(fs, MIPSInst_FS(ir));
2543 SPFROMREG(ft, MIPSInst_FT(ir));
2545 /* positive predicates */
2546 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2547 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2549 rv.w = -1; /* true, all 1s */
2551 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2552 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2556 /* negative predicates */
2561 if (ieee754sp_cmp(fs, ft,
2562 negative_cmptab[cmpop],
2564 rv.w = -1; /* true, all 1s */
2566 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2567 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2572 /* Reserved R6 ops */
2584 if (!cpu_has_mips_3_4_5_64_r2_r6)
2587 DIFROMREG(bits, MIPSInst_FS(ir));
2589 switch (MIPSInst_FUNC(ir)) {
2591 /* convert long to single precision real */
2592 MIPS_FPU_EMU_INC_STATS(cvt_s_l);
2593 rv.s = ieee754sp_flong(bits);
2597 /* convert long to double precision real */
2598 MIPS_FPU_EMU_INC_STATS(cvt_d_l);
2599 rv.d = ieee754dp_flong(bits);
2603 /* Emulating the new CMP.condn.fmt R6 instruction */
2604 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2605 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2606 union ieee754dp fs, ft;
2608 if (!cpu_has_mips_r6 ||
2609 (MIPSInst_FUNC(ir) & 0x20))
2613 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2616 MIPS_FPU_EMU_INC_STATS(cmp_af_d);
2619 MIPS_FPU_EMU_INC_STATS(cmp_un_d);
2622 MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
2625 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
2628 MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
2631 MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
2634 MIPS_FPU_EMU_INC_STATS(cmp_le_d);
2637 MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
2643 MIPS_FPU_EMU_INC_STATS(cmp_or_d);
2646 MIPS_FPU_EMU_INC_STATS(cmp_une_d);
2649 MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
2654 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2657 MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
2660 MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
2663 MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
2666 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
2669 MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
2672 MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
2675 MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
2678 MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
2684 MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
2687 MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
2690 MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
2696 /* fmt is l_fmt for double precision so fix it */
2698 /* default to false */
2702 DPFROMREG(fs, MIPSInst_FS(ir));
2703 DPFROMREG(ft, MIPSInst_FT(ir));
2705 /* positive predicates */
2706 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2707 if (ieee754dp_cmp(fs, ft,
2708 cmptab[cmpop], sig))
2709 rv.l = -1LL; /* true, all 1s */
2711 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2712 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2716 /* negative predicates */
2721 if (ieee754dp_cmp(fs, ft,
2722 negative_cmptab[cmpop],
2724 rv.l = -1LL; /* true, all 1s */
2726 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2727 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2732 /* Reserved R6 ops */
2746 * Update the fpu CSR register for this operation.
2747 * If an exception is required, generate a tidy SIGFPE exception,
2748 * without updating the result register.
2749 * Note: cause exception bits do not accumulate, they are rewritten
2750 * for each op; only the flag/sticky bits accumulate.
2752 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2753 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2754 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2759 * Now we can safely write the result back to the register file.
2764 if (cpu_has_mips_4_5_r)
2765 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2767 cbit = FPU_CSR_COND;
2771 ctx->fcr31 &= ~cbit;
2775 DPTOREG(rv.d, MIPSInst_FD(ir));
2778 SPTOREG(rv.s, MIPSInst_FD(ir));
2781 SITOREG(rv.w, MIPSInst_FD(ir));
2784 if (!cpu_has_mips_3_4_5_64_r2_r6)
2787 DITOREG(rv.l, MIPSInst_FD(ir));
2797 * Emulate FPU instructions.
2799 * If we use FPU hardware, then we have been typically called to handle
2800 * an unimplemented operation, such as where an operand is a NaN or
2801 * denormalized. In that case exit the emulation loop after a single
2802 * iteration so as to let hardware execute any subsequent instructions.
2804 * If we have no FPU hardware or it has been disabled, then continue
2805 * emulating floating-point instructions until one of these conditions
2808 * - a non-FPU instruction has been encountered,
2810 * - an attempt to emulate has ended with a signal,
2812 * - the ISA mode has been switched.
2814 * We need to terminate the emulation loop if we got switched to the
2815 * MIPS16 mode, whether supported or not, so that we do not attempt
2816 * to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
2817 * Similarly if we got switched to the microMIPS mode and only the
2818 * regular MIPS mode is supported, so that we do not attempt to emulate
2819 * a microMIPS instruction as a regular MIPS FPU instruction. Or if
2820 * we got switched to the regular MIPS mode and only the microMIPS mode
2821 * is supported, so that we do not attempt to emulate a regular MIPS
2822 * instruction that should cause an Address Error exception instead.
2823 * For simplicity we always terminate upon an ISA mode switch.
2825 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2826 int has_fpu, void __user **fault_addr)
2828 unsigned long oldepc, prevepc;
2829 struct mm_decoded_insn dec_insn;
2834 oldepc = xcp->cp0_epc;
2836 prevepc = xcp->cp0_epc;
2838 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2840 * Get next 2 microMIPS instructions and convert them
2841 * into 32-bit instructions.
2843 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2844 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2845 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2846 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2847 MIPS_FPU_EMU_INC_STATS(errors);
2852 /* Get first instruction. */
2853 if (mm_insn_16bit(*instr_ptr)) {
2854 /* Duplicate the half-word. */
2855 dec_insn.insn = (*instr_ptr << 16) |
2857 /* 16-bit instruction. */
2858 dec_insn.pc_inc = 2;
2861 dec_insn.insn = (*instr_ptr << 16) |
2863 /* 32-bit instruction. */
2864 dec_insn.pc_inc = 4;
2867 /* Get second instruction. */
2868 if (mm_insn_16bit(*instr_ptr)) {
2869 /* Duplicate the half-word. */
2870 dec_insn.next_insn = (*instr_ptr << 16) |
2872 /* 16-bit instruction. */
2873 dec_insn.next_pc_inc = 2;
2875 dec_insn.next_insn = (*instr_ptr << 16) |
2877 /* 32-bit instruction. */
2878 dec_insn.next_pc_inc = 4;
2880 dec_insn.micro_mips_mode = 1;
2882 if ((get_user(dec_insn.insn,
2883 (mips_instruction __user *) xcp->cp0_epc)) ||
2884 (get_user(dec_insn.next_insn,
2885 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2886 MIPS_FPU_EMU_INC_STATS(errors);
2889 dec_insn.pc_inc = 4;
2890 dec_insn.next_pc_inc = 4;
2891 dec_insn.micro_mips_mode = 0;
2894 if ((dec_insn.insn == 0) ||
2895 ((dec_insn.pc_inc == 2) &&
2896 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2897 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2900 * The 'ieee754_csr' is an alias of ctx->fcr31.
2901 * No need to copy ctx->fcr31 to ieee754_csr.
2903 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2911 * We have to check for the ISA bit explicitly here,
2912 * because `get_isa16_mode' may return 0 if support
2913 * for code compression has been globally disabled,
2914 * or otherwise we may produce the wrong signal or
2915 * even proceed successfully where we must not.
2917 if ((xcp->cp0_epc ^ prevepc) & 0x1)
2921 } while (xcp->cp0_epc > prevepc);
2923 /* SIGILL indicates a non-fpu instruction */
2924 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2925 /* but if EPC has advanced, then ignore it */