arch/mips/loongson64/env.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Based on Ocelot Linux port, which is
   4  * Copyright 2001 MontaVista Software Inc.
   5  * Author: jsun@mvista.com or jsun@junsun.net
   6  *
   7  * Copyright 2003 ICT CAS
   8  * Author: Michael Guo <guoyi@ict.ac.cn>
   9  *
  10  * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
  11  * Author: Fuxin Zhang, zhangfx@lemote.com
  12  *
  13  * Copyright (C) 2009 Lemote Inc.
  14  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  15  */
  16 #include <linux/export.h>
  17 #include <linux/pci_ids.h>
  18 #include <asm/bootinfo.h>
  19 #include <loongson.h>
  20 #include <boot_param.h>
  21 #include <builtin_dtbs.h>
  22 #include <workarounds.h>
  23
  24 #define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
  25
  26 u32 cpu_clock_freq;
  27 EXPORT_SYMBOL(cpu_clock_freq);
  28 struct efi_memory_map_loongson *loongson_memmap;
  29 struct loongson_system_configuration loongson_sysconf;
  30
  31 u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
  32 u64 loongson_chiptemp[MAX_PACKAGES];
  33 u64 loongson_freqctrl[MAX_PACKAGES];
  34
  35 unsigned long long smp_group[4];
  36
  37 const char *get_system_type(void)
  38 {
  39         return "Generic Loongson64 System";
  40 }
  41
  42 void __init prom_init_env(void)
  43 {
  44         struct boot_params *boot_p;
  45         struct loongson_params *loongson_p;
  46         struct system_loongson *esys;
  47         struct efi_cpuinfo_loongson *ecpu;
  48         struct irq_source_routing_table *eirq_source;
  49         u32 id;
  50         u16 vendor, device;
  51
  52         /* firmware arguments are initialized in head.S */
  53         boot_p = (struct boot_params *)fw_arg2;
  54         loongson_p = &(boot_p->efi.smbios.lp);
  55
  56         esys = (struct system_loongson *)
  57                 ((u64)loongson_p + loongson_p->system_offset);
  58         ecpu = (struct efi_cpuinfo_loongson *)
  59                 ((u64)loongson_p + loongson_p->cpu_offset);
  60         eirq_source = (struct irq_source_routing_table *)
  61                 ((u64)loongson_p + loongson_p->irq_offset);
  62         loongson_memmap = (struct efi_memory_map_loongson *)
  63                 ((u64)loongson_p + loongson_p->memory_offset);
  64
  65         cpu_clock_freq = ecpu->cpu_clock_freq;
  66         loongson_sysconf.cputype = ecpu->cputype;
  67         switch (ecpu->cputype) {
  68         case Legacy_3A:
  69         case Loongson_3A:
  70                 loongson_sysconf.cores_per_node = 4;
  71                 loongson_sysconf.cores_per_package = 4;
  72                 smp_group[0] = 0x900000003ff01000;
  73                 smp_group[1] = 0x900010003ff01000;
  74                 smp_group[2] = 0x900020003ff01000;
  75                 smp_group[3] = 0x900030003ff01000;
  76                 loongson_chipcfg[0] = 0x900000001fe00180;
  77                 loongson_chipcfg[1] = 0x900010001fe00180;
  78                 loongson_chipcfg[2] = 0x900020001fe00180;
  79                 loongson_chipcfg[3] = 0x900030001fe00180;
  80                 loongson_chiptemp[0] = 0x900000001fe0019c;
  81                 loongson_chiptemp[1] = 0x900010001fe0019c;
  82                 loongson_chiptemp[2] = 0x900020001fe0019c;
  83                 loongson_chiptemp[3] = 0x900030001fe0019c;
  84                 loongson_freqctrl[0] = 0x900000001fe001d0;
  85                 loongson_freqctrl[1] = 0x900010001fe001d0;
  86                 loongson_freqctrl[2] = 0x900020001fe001d0;
  87                 loongson_freqctrl[3] = 0x900030001fe001d0;
  88                 loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
  89                 loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
  90                 break;
  91         case Legacy_3B:
  92         case Loongson_3B:
  93                 loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
  94                 loongson_sysconf.cores_per_package = 8;
  95                 smp_group[0] = 0x900000003ff01000;
  96                 smp_group[1] = 0x900010003ff05000;
  97                 smp_group[2] = 0x900020003ff09000;
  98                 smp_group[3] = 0x900030003ff0d000;
  99                 loongson_chipcfg[0] = 0x900000001fe00180;
 100                 loongson_chipcfg[1] = 0x900020001fe00180;
 101                 loongson_chipcfg[2] = 0x900040001fe00180;
 102                 loongson_chipcfg[3] = 0x900060001fe00180;
 103                 loongson_chiptemp[0] = 0x900000001fe0019c;
 104                 loongson_chiptemp[1] = 0x900020001fe0019c;
 105                 loongson_chiptemp[2] = 0x900040001fe0019c;
 106                 loongson_chiptemp[3] = 0x900060001fe0019c;
 107                 loongson_freqctrl[0] = 0x900000001fe001d0;
 108                 loongson_freqctrl[1] = 0x900020001fe001d0;
 109                 loongson_freqctrl[2] = 0x900040001fe001d0;
 110                 loongson_freqctrl[3] = 0x900060001fe001d0;
 111                 loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
 112                 loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
 113                 break;
 114         default:
 115                 loongson_sysconf.cores_per_node = 1;
 116                 loongson_sysconf.cores_per_package = 1;
 117                 loongson_chipcfg[0] = 0x900000001fe00180;
 118         }
 119
 120         loongson_sysconf.nr_cpus = ecpu->nr_cpus;
 121         loongson_sysconf.boot_cpu_id = ecpu->cpu_startup_core_id;
 122         loongson_sysconf.reserved_cpus_mask = ecpu->reserved_cores_mask;
 123         if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
 124                 loongson_sysconf.nr_cpus = NR_CPUS;
 125         loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
 126                 loongson_sysconf.cores_per_node - 1) /
 127                 loongson_sysconf.cores_per_node;
 128
 129         loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
 130         loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
 131         loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
 132         loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
 133         if (loongson_sysconf.dma_mask_bits < 32 ||
 134                 loongson_sysconf.dma_mask_bits > 64)
 135                 loongson_sysconf.dma_mask_bits = 32;
 136
 137         loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
 138         loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
 139         loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
 140
 141         loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
 142         pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
 143                 loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
 144                 loongson_sysconf.vgabios_addr);
 145
 146         memset(loongson_sysconf.ecname, 0, 32);
 147         if (esys->has_ec)
 148                 memcpy(loongson_sysconf.ecname, esys->ec_name, 32);
 149         loongson_sysconf.workarounds |= esys->workarounds;
 150
 151         loongson_sysconf.nr_uarts = esys->nr_uarts;
 152         if (esys->nr_uarts < 1 || esys->nr_uarts > MAX_UARTS)
 153                 loongson_sysconf.nr_uarts = 1;
 154         memcpy(loongson_sysconf.uarts, esys->uarts,
 155                 sizeof(struct uart_device) * loongson_sysconf.nr_uarts);
 156
 157         loongson_sysconf.nr_sensors = esys->nr_sensors;
 158         if (loongson_sysconf.nr_sensors > MAX_SENSORS)
 159                 loongson_sysconf.nr_sensors = 0;
 160         if (loongson_sysconf.nr_sensors)
 161                 memcpy(loongson_sysconf.sensors, esys->sensors,
 162                         sizeof(struct sensor_device) * loongson_sysconf.nr_sensors);
 163         pr_info("CpuClock = %u\n", cpu_clock_freq);
 164
 165         /* Read the ID of PCI host bridge to detect bridge type */
 166         id = readl(HOST_BRIDGE_CONFIG_ADDR);
 167         vendor = id & 0xffff;
 168         device = (id >> 16) & 0xffff;
 169
 170         switch (vendor) {
 171         case PCI_VENDOR_ID_LOONGSON:
 172                 pr_info("The bridge chip is LS7A\n");
 173                 loongson_sysconf.bridgetype = LS7A;
 174                 loongson_sysconf.early_config = ls7a_early_config;
 175                 break;
 176         case PCI_VENDOR_ID_AMD:
 177         case PCI_VENDOR_ID_ATI:
 178                 pr_info("The bridge chip is RS780E or SR5690\n");
 179                 loongson_sysconf.bridgetype = RS780E;
 180                 loongson_sysconf.early_config = rs780e_early_config;
 181                 break;
 182         default:
 183                 pr_info("The bridge chip is VIRTUAL\n");
 184                 loongson_sysconf.bridgetype = VIRTUAL;
 185                 loongson_sysconf.early_config = virtual_early_config;
 186                 loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
 187                 break;
 188         }
 189
 190         if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
 191                 switch (read_c0_prid() & PRID_REV_MASK) {
 192                 case PRID_REV_LOONGSON3A_R1:
 193                 case PRID_REV_LOONGSON3A_R2_0:
 194                 case PRID_REV_LOONGSON3A_R2_1:
 195                 case PRID_REV_LOONGSON3A_R3_0:
 196                 case PRID_REV_LOONGSON3A_R3_1:
 197                         switch (loongson_sysconf.bridgetype) {
 198                         case LS7A:
 199                                 loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
 200                                 break;
 201                         case RS780E:
 202                                 loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
 203                                 break;
 204                         default:
 205                                 break;
 206                         }
 207                         break;
 208                 case PRID_REV_LOONGSON3B_R1:
 209                 case PRID_REV_LOONGSON3B_R2:
 210                         if (loongson_sysconf.bridgetype == RS780E)
 211                                 loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
 212                         break;
 213                 default:
 214                         break;
 215                 }
 216         } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
 217                 if (loongson_sysconf.bridgetype == LS7A)
 218                         loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
 219         }
 220
 221         if (!loongson_fdt_blob)
 222                 pr_err("Failed to determine built-in Loongson64 dtb\n");
 223 }