2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/memblock.h>
22 #include <linux/pgtable.h>
26 #include <asm/cacheflush.h>
27 #include <asm/mmu_context.h>
28 #include <asm/pgalloc.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 struct kvm_stats_debugfs_item debugfs_entries[] = {
43 VCPU_STAT("wait", wait_exits),
44 VCPU_STAT("cache", cache_exits),
45 VCPU_STAT("signal", signal_exits),
46 VCPU_STAT("interrupt", int_exits),
47 VCPU_STAT("cop_unusable", cop_unusable_exits),
48 VCPU_STAT("tlbmod", tlbmod_exits),
49 VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits),
50 VCPU_STAT("tlbmiss_st", tlbmiss_st_exits),
51 VCPU_STAT("addrerr_st", addrerr_st_exits),
52 VCPU_STAT("addrerr_ld", addrerr_ld_exits),
53 VCPU_STAT("syscall", syscall_exits),
54 VCPU_STAT("resvd_inst", resvd_inst_exits),
55 VCPU_STAT("break_inst", break_inst_exits),
56 VCPU_STAT("trap_inst", trap_inst_exits),
57 VCPU_STAT("msa_fpe", msa_fpe_exits),
58 VCPU_STAT("fpe", fpe_exits),
59 VCPU_STAT("msa_disabled", msa_disabled_exits),
60 VCPU_STAT("flush_dcache", flush_dcache_exits),
61 #ifdef CONFIG_KVM_MIPS_VZ
62 VCPU_STAT("vz_gpsi", vz_gpsi_exits),
63 VCPU_STAT("vz_gsfc", vz_gsfc_exits),
64 VCPU_STAT("vz_hc", vz_hc_exits),
65 VCPU_STAT("vz_grr", vz_grr_exits),
66 VCPU_STAT("vz_gva", vz_gva_exits),
67 VCPU_STAT("vz_ghfc", vz_ghfc_exits),
68 VCPU_STAT("vz_gpa", vz_gpa_exits),
69 VCPU_STAT("vz_resvd", vz_resvd_exits),
70 #ifdef CONFIG_CPU_LOONGSON64
71 VCPU_STAT("vz_cpucfg", vz_cpucfg_exits),
74 VCPU_STAT("halt_successful_poll", halt_successful_poll),
75 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
76 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
77 VCPU_STAT("halt_wakeup", halt_wakeup),
78 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
79 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
83 bool kvm_trace_guest_mode_change;
85 int kvm_guest_mode_change_trace_reg(void)
87 kvm_trace_guest_mode_change = true;
91 void kvm_guest_mode_change_trace_unreg(void)
93 kvm_trace_guest_mode_change = false;
97 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
98 * Config7, so we are "runnable" if interrupts are pending
100 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
102 return !!(vcpu->arch.pending_exceptions);
105 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
110 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
115 int kvm_arch_hardware_enable(void)
117 return kvm_mips_callbacks->hardware_enable();
120 void kvm_arch_hardware_disable(void)
122 kvm_mips_callbacks->hardware_disable();
125 int kvm_arch_hardware_setup(void *opaque)
130 int kvm_arch_check_processor_compat(void *opaque)
135 extern void kvm_init_loongson_ipi(struct kvm *kvm);
137 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
140 case KVM_VM_MIPS_AUTO:
142 #ifdef CONFIG_KVM_MIPS_VZ
149 /* Unsupported KVM type */
153 /* Allocate page table to map GPA -> RPA */
154 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
155 if (!kvm->arch.gpa_mm.pgd)
158 #ifdef CONFIG_CPU_LOONGSON64
159 kvm_init_loongson_ipi(kvm);
165 void kvm_mips_free_vcpus(struct kvm *kvm)
168 struct kvm_vcpu *vcpu;
170 kvm_for_each_vcpu(i, vcpu, kvm) {
171 kvm_vcpu_destroy(vcpu);
174 mutex_lock(&kvm->lock);
176 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
177 kvm->vcpus[i] = NULL;
179 atomic_set(&kvm->online_vcpus, 0);
181 mutex_unlock(&kvm->lock);
184 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
186 /* It should always be safe to remove after flushing the whole range */
187 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
188 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
191 void kvm_arch_destroy_vm(struct kvm *kvm)
193 kvm_mips_free_vcpus(kvm);
194 kvm_mips_free_gpa_pt(kvm);
197 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
203 void kvm_arch_flush_shadow_all(struct kvm *kvm)
205 /* Flush whole GPA */
206 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
208 /* Let implementation do the rest */
209 kvm_mips_callbacks->flush_shadow_all(kvm);
212 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
213 struct kvm_memory_slot *slot)
216 * The slot has been made invalid (ready for moving or deletion), so we
217 * need to ensure that it can no longer be accessed by any guest VCPUs.
220 spin_lock(&kvm->mmu_lock);
221 /* Flush slot from GPA */
222 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
223 slot->base_gfn + slot->npages - 1);
224 /* Let implementation do the rest */
225 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
226 spin_unlock(&kvm->mmu_lock);
229 int kvm_arch_prepare_memory_region(struct kvm *kvm,
230 struct kvm_memory_slot *memslot,
231 const struct kvm_userspace_memory_region *mem,
232 enum kvm_mr_change change)
237 void kvm_arch_commit_memory_region(struct kvm *kvm,
238 const struct kvm_userspace_memory_region *mem,
239 struct kvm_memory_slot *old,
240 const struct kvm_memory_slot *new,
241 enum kvm_mr_change change)
245 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
246 __func__, kvm, mem->slot, mem->guest_phys_addr,
247 mem->memory_size, mem->userspace_addr);
250 * If dirty page logging is enabled, write protect all pages in the slot
251 * ready for dirty logging.
253 * There is no need to do this in any of the following cases:
254 * CREATE: No dirty mappings will already exist.
255 * MOVE/DELETE: The old mappings will already have been cleaned up by
256 * kvm_arch_flush_shadow_memslot()
258 if (change == KVM_MR_FLAGS_ONLY &&
259 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
260 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
261 spin_lock(&kvm->mmu_lock);
262 /* Write protect GPA page table entries */
263 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
264 new->base_gfn + new->npages - 1);
265 /* Let implementation do the rest */
267 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
268 spin_unlock(&kvm->mmu_lock);
272 static inline void dump_handler(const char *symbol, void *start, void *end)
276 pr_debug("LEAF(%s)\n", symbol);
278 pr_debug("\t.set push\n");
279 pr_debug("\t.set noreorder\n");
281 for (p = start; p < (u32 *)end; ++p)
282 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
284 pr_debug("\t.set\tpop\n");
286 pr_debug("\tEND(%s)\n", symbol);
289 /* low level hrtimer wake routine */
290 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
292 struct kvm_vcpu *vcpu;
294 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
296 kvm_mips_callbacks->queue_timer_int(vcpu);
299 rcuwait_wake_up(&vcpu->wait);
301 return kvm_mips_count_timeout(vcpu);
304 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
309 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
312 void *gebase, *p, *handler, *refill_start, *refill_end;
315 kvm_debug("kvm @ %p: create cpu %d at %p\n",
316 vcpu->kvm, vcpu->vcpu_id, vcpu);
318 err = kvm_mips_callbacks->vcpu_init(vcpu);
322 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
324 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
327 * Allocate space for host mode exception handlers that handle
330 if (cpu_has_veic || cpu_has_vint)
331 size = 0x200 + VECTORSPACING * 64;
335 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
339 goto out_uninit_vcpu;
341 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
342 ALIGN(size, PAGE_SIZE), gebase);
345 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
346 * limits us to the low 512MB of physical address space. If the memory
347 * we allocate is out of range, just give up now.
349 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
350 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
353 goto out_free_gebase;
357 vcpu->arch.guest_ebase = gebase;
359 /* Build guest exception vectors dynamically in unmapped memory */
360 handler = gebase + 0x2000;
362 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
363 refill_start = gebase;
364 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
365 refill_start += 0x080;
366 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
368 /* General Exception Entry point */
369 kvm_mips_build_exception(gebase + 0x180, handler);
371 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
372 for (i = 0; i < 8; i++) {
373 kvm_debug("L1 Vectored handler @ %p\n",
374 gebase + 0x200 + (i * VECTORSPACING));
375 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
379 /* General exit handler */
381 p = kvm_mips_build_exit(p);
383 /* Guest entry routine */
384 vcpu->arch.vcpu_run = p;
385 p = kvm_mips_build_vcpu_run(p);
387 /* Dump the generated code */
388 pr_debug("#include <asm/asm.h>\n");
389 pr_debug("#include <asm/regdef.h>\n");
391 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
392 dump_handler("kvm_tlb_refill", refill_start, refill_end);
393 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
394 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
396 /* Invalidate the icache for these ranges */
397 flush_icache_range((unsigned long)gebase,
398 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
401 * Allocate comm page for guest kernel, a TLB will be reserved for
402 * mapping GVA @ 0xFFFF8000 to this page
404 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
406 if (!vcpu->arch.kseg0_commpage) {
408 goto out_free_gebase;
411 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
412 kvm_mips_commpage_init(vcpu);
415 vcpu->arch.last_sched_cpu = -1;
416 vcpu->arch.last_exec_cpu = -1;
418 /* Initial guest state */
419 err = kvm_mips_callbacks->vcpu_setup(vcpu);
421 goto out_free_commpage;
426 kfree(vcpu->arch.kseg0_commpage);
430 kvm_mips_callbacks->vcpu_uninit(vcpu);
434 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
436 hrtimer_cancel(&vcpu->arch.comparecount_timer);
438 kvm_mips_dump_stats(vcpu);
440 kvm_mmu_free_memory_caches(vcpu);
441 kfree(vcpu->arch.guest_ebase);
442 kfree(vcpu->arch.kseg0_commpage);
444 kvm_mips_callbacks->vcpu_uninit(vcpu);
447 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
448 struct kvm_guest_debug *dbg)
453 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
459 kvm_sigset_activate(vcpu);
461 if (vcpu->mmio_needed) {
462 if (!vcpu->mmio_is_write)
463 kvm_mips_complete_mmio_load(vcpu);
464 vcpu->mmio_needed = 0;
467 if (vcpu->run->immediate_exit)
473 guest_enter_irqoff();
474 trace_kvm_enter(vcpu);
477 * Make sure the read of VCPU requests in vcpu_run() callback is not
478 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
479 * flush request while the requester sees the VCPU as outside of guest
480 * mode and not needing an IPI.
482 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
484 r = kvm_mips_callbacks->vcpu_run(vcpu);
491 kvm_sigset_deactivate(vcpu);
497 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
498 struct kvm_mips_interrupt *irq)
500 int intr = (int)irq->irq;
501 struct kvm_vcpu *dvcpu = NULL;
503 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
504 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
505 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
506 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
507 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
513 dvcpu = vcpu->kvm->vcpus[irq->cpu];
515 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
516 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
518 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
519 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
521 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
526 dvcpu->arch.wait = 0;
528 rcuwait_wake_up(&dvcpu->wait);
533 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
534 struct kvm_mp_state *mp_state)
539 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
540 struct kvm_mp_state *mp_state)
545 static u64 kvm_mips_get_one_regs[] = {
579 #ifndef CONFIG_CPU_MIPSR6
586 static u64 kvm_mips_get_one_regs_fpu[] = {
588 KVM_REG_MIPS_FCR_CSR,
591 static u64 kvm_mips_get_one_regs_msa[] = {
593 KVM_REG_MIPS_MSA_CSR,
596 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
600 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
601 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
602 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
604 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
607 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
608 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
609 ret += kvm_mips_callbacks->num_regs(vcpu);
614 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
619 if (copy_to_user(indices, kvm_mips_get_one_regs,
620 sizeof(kvm_mips_get_one_regs)))
622 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
624 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
625 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
626 sizeof(kvm_mips_get_one_regs_fpu)))
628 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
630 for (i = 0; i < 32; ++i) {
631 index = KVM_REG_MIPS_FPR_32(i);
632 if (copy_to_user(indices, &index, sizeof(index)))
636 /* skip odd doubles if no F64 */
637 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
640 index = KVM_REG_MIPS_FPR_64(i);
641 if (copy_to_user(indices, &index, sizeof(index)))
647 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
648 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
649 sizeof(kvm_mips_get_one_regs_msa)))
651 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
653 for (i = 0; i < 32; ++i) {
654 index = KVM_REG_MIPS_VEC_128(i);
655 if (copy_to_user(indices, &index, sizeof(index)))
661 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
664 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
665 const struct kvm_one_reg *reg)
667 struct mips_coproc *cop0 = vcpu->arch.cop0;
668 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
675 /* General purpose registers */
676 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
677 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
679 #ifndef CONFIG_CPU_MIPSR6
680 case KVM_REG_MIPS_HI:
681 v = (long)vcpu->arch.hi;
683 case KVM_REG_MIPS_LO:
684 v = (long)vcpu->arch.lo;
687 case KVM_REG_MIPS_PC:
688 v = (long)vcpu->arch.pc;
691 /* Floating point registers */
692 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
693 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
695 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
696 /* Odd singles in top of even double when FR=0 */
697 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
698 v = get_fpr32(&fpu->fpr[idx], 0);
700 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
702 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
703 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
705 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
706 /* Can't access odd doubles in FR=0 mode */
707 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
709 v = get_fpr64(&fpu->fpr[idx], 0);
711 case KVM_REG_MIPS_FCR_IR:
712 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
714 v = boot_cpu_data.fpu_id;
716 case KVM_REG_MIPS_FCR_CSR:
717 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
722 /* MIPS SIMD Architecture (MSA) registers */
723 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
724 if (!kvm_mips_guest_has_msa(&vcpu->arch))
726 /* Can't access MSA registers in FR=0 mode */
727 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
729 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
730 #ifdef CONFIG_CPU_LITTLE_ENDIAN
731 /* least significant byte first */
732 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
733 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
735 /* most significant byte first */
736 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
737 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
740 case KVM_REG_MIPS_MSA_IR:
741 if (!kvm_mips_guest_has_msa(&vcpu->arch))
743 v = boot_cpu_data.msa_id;
745 case KVM_REG_MIPS_MSA_CSR:
746 if (!kvm_mips_guest_has_msa(&vcpu->arch))
751 /* registers to be handled specially */
753 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
758 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
759 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
761 return put_user(v, uaddr64);
762 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
763 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
766 return put_user(v32, uaddr32);
767 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
768 void __user *uaddr = (void __user *)(long)reg->addr;
770 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
776 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
777 const struct kvm_one_reg *reg)
779 struct mips_coproc *cop0 = vcpu->arch.cop0;
780 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
785 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
786 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
788 if (get_user(v, uaddr64) != 0)
790 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
791 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
794 if (get_user(v32, uaddr32) != 0)
797 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
798 void __user *uaddr = (void __user *)(long)reg->addr;
800 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
806 /* General purpose registers */
807 case KVM_REG_MIPS_R0:
808 /* Silently ignore requests to set $0 */
810 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
811 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
813 #ifndef CONFIG_CPU_MIPSR6
814 case KVM_REG_MIPS_HI:
817 case KVM_REG_MIPS_LO:
821 case KVM_REG_MIPS_PC:
825 /* Floating point registers */
826 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
827 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
829 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
830 /* Odd singles in top of even double when FR=0 */
831 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
832 set_fpr32(&fpu->fpr[idx], 0, v);
834 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
836 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
837 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
839 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
840 /* Can't access odd doubles in FR=0 mode */
841 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
843 set_fpr64(&fpu->fpr[idx], 0, v);
845 case KVM_REG_MIPS_FCR_IR:
846 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
850 case KVM_REG_MIPS_FCR_CSR:
851 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
856 /* MIPS SIMD Architecture (MSA) registers */
857 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
858 if (!kvm_mips_guest_has_msa(&vcpu->arch))
860 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
861 #ifdef CONFIG_CPU_LITTLE_ENDIAN
862 /* least significant byte first */
863 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
864 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
866 /* most significant byte first */
867 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
868 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
871 case KVM_REG_MIPS_MSA_IR:
872 if (!kvm_mips_guest_has_msa(&vcpu->arch))
876 case KVM_REG_MIPS_MSA_CSR:
877 if (!kvm_mips_guest_has_msa(&vcpu->arch))
882 /* registers to be handled specially */
884 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
889 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
890 struct kvm_enable_cap *cap)
894 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
902 case KVM_CAP_MIPS_FPU:
903 vcpu->arch.fpu_enabled = true;
905 case KVM_CAP_MIPS_MSA:
906 vcpu->arch.msa_enabled = true;
916 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
919 struct kvm_vcpu *vcpu = filp->private_data;
920 void __user *argp = (void __user *)arg;
922 if (ioctl == KVM_INTERRUPT) {
923 struct kvm_mips_interrupt irq;
925 if (copy_from_user(&irq, argp, sizeof(irq)))
927 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
930 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
936 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
939 struct kvm_vcpu *vcpu = filp->private_data;
940 void __user *argp = (void __user *)arg;
946 case KVM_SET_ONE_REG:
947 case KVM_GET_ONE_REG: {
948 struct kvm_one_reg reg;
951 if (copy_from_user(®, argp, sizeof(reg)))
953 if (ioctl == KVM_SET_ONE_REG)
954 r = kvm_mips_set_reg(vcpu, ®);
956 r = kvm_mips_get_reg(vcpu, ®);
959 case KVM_GET_REG_LIST: {
960 struct kvm_reg_list __user *user_list = argp;
961 struct kvm_reg_list reg_list;
965 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
968 reg_list.n = kvm_mips_num_regs(vcpu);
969 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
974 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
977 case KVM_ENABLE_CAP: {
978 struct kvm_enable_cap cap;
981 if (copy_from_user(&cap, argp, sizeof(cap)))
983 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
994 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
999 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
1000 struct kvm_memory_slot *memslot)
1002 /* Let implementation handle TLB/GVA invalidation */
1003 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1006 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1018 int kvm_arch_init(void *opaque)
1020 if (kvm_mips_callbacks) {
1021 kvm_err("kvm: module already exists\n");
1025 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1028 void kvm_arch_exit(void)
1030 kvm_mips_callbacks = NULL;
1033 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1034 struct kvm_sregs *sregs)
1036 return -ENOIOCTLCMD;
1039 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1040 struct kvm_sregs *sregs)
1042 return -ENOIOCTLCMD;
1045 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1049 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1051 return -ENOIOCTLCMD;
1054 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1056 return -ENOIOCTLCMD;
1059 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1061 return VM_FAULT_SIGBUS;
1064 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1069 case KVM_CAP_ONE_REG:
1070 case KVM_CAP_ENABLE_CAP:
1071 case KVM_CAP_READONLY_MEM:
1072 case KVM_CAP_SYNC_MMU:
1073 case KVM_CAP_IMMEDIATE_EXIT:
1076 case KVM_CAP_NR_VCPUS:
1077 r = num_online_cpus();
1079 case KVM_CAP_MAX_VCPUS:
1082 case KVM_CAP_MAX_VCPU_ID:
1083 r = KVM_MAX_VCPU_ID;
1085 case KVM_CAP_MIPS_FPU:
1086 /* We don't handle systems with inconsistent cpu_has_fpu */
1087 r = !!raw_cpu_has_fpu;
1089 case KVM_CAP_MIPS_MSA:
1091 * We don't support MSA vector partitioning yet:
1092 * 1) It would require explicit support which can't be tested
1093 * yet due to lack of support in current hardware.
1094 * 2) It extends the state that would need to be saved/restored
1095 * by e.g. QEMU for migration.
1097 * When vector partitioning hardware becomes available, support
1098 * could be added by requiring a flag when enabling
1099 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1100 * to save/restore the appropriate extra state.
1102 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1105 r = kvm_mips_callbacks->check_extension(kvm, ext);
1111 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1113 return kvm_mips_pending_timer(vcpu) ||
1114 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1117 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1120 struct mips_coproc *cop0;
1125 kvm_debug("VCPU Register Dump:\n");
1126 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1127 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1129 for (i = 0; i < 32; i += 4) {
1130 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1132 vcpu->arch.gprs[i + 1],
1133 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1135 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1136 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1138 cop0 = vcpu->arch.cop0;
1139 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1140 kvm_read_c0_guest_status(cop0),
1141 kvm_read_c0_guest_cause(cop0));
1143 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1148 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1154 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1155 vcpu->arch.gprs[i] = regs->gpr[i];
1156 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1157 vcpu->arch.hi = regs->hi;
1158 vcpu->arch.lo = regs->lo;
1159 vcpu->arch.pc = regs->pc;
1165 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1171 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1172 regs->gpr[i] = vcpu->arch.gprs[i];
1174 regs->hi = vcpu->arch.hi;
1175 regs->lo = vcpu->arch.lo;
1176 regs->pc = vcpu->arch.pc;
1182 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1183 struct kvm_translation *tr)
1188 static void kvm_mips_set_c0_status(void)
1190 u32 status = read_c0_status();
1195 write_c0_status(status);
1200 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1202 int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1204 struct kvm_run *run = vcpu->run;
1205 u32 cause = vcpu->arch.host_cp0_cause;
1206 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1207 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1208 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1209 enum emulation_result er = EMULATE_DONE;
1211 int ret = RESUME_GUEST;
1213 vcpu->mode = OUTSIDE_GUEST_MODE;
1215 /* re-enable HTW before enabling interrupts */
1216 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1219 /* Set a default exit reason */
1220 run->exit_reason = KVM_EXIT_UNKNOWN;
1221 run->ready_for_interrupt_injection = 1;
1224 * Set the appropriate status bits based on host CPU features,
1225 * before we hit the scheduler
1227 kvm_mips_set_c0_status();
1231 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1232 cause, opc, run, vcpu);
1233 trace_kvm_exit(vcpu, exccode);
1235 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1237 * Do a privilege check, if in UM most of these exit conditions
1238 * end up causing an exception to be delivered to the Guest
1241 er = kvm_mips_check_privilege(cause, opc, vcpu);
1242 if (er == EMULATE_PRIV_FAIL) {
1244 } else if (er == EMULATE_FAIL) {
1245 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1253 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1255 ++vcpu->stat.int_exits;
1264 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1266 ++vcpu->stat.cop_unusable_exits;
1267 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1268 /* XXXKYMA: Might need to return to user space */
1269 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1274 ++vcpu->stat.tlbmod_exits;
1275 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1279 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1280 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1283 ++vcpu->stat.tlbmiss_st_exits;
1284 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1288 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1289 cause, opc, badvaddr);
1291 ++vcpu->stat.tlbmiss_ld_exits;
1292 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1296 ++vcpu->stat.addrerr_st_exits;
1297 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1301 ++vcpu->stat.addrerr_ld_exits;
1302 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1306 ++vcpu->stat.syscall_exits;
1307 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1311 ++vcpu->stat.resvd_inst_exits;
1312 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1316 ++vcpu->stat.break_inst_exits;
1317 ret = kvm_mips_callbacks->handle_break(vcpu);
1321 ++vcpu->stat.trap_inst_exits;
1322 ret = kvm_mips_callbacks->handle_trap(vcpu);
1325 case EXCCODE_MSAFPE:
1326 ++vcpu->stat.msa_fpe_exits;
1327 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1331 ++vcpu->stat.fpe_exits;
1332 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1335 case EXCCODE_MSADIS:
1336 ++vcpu->stat.msa_disabled_exits;
1337 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1341 /* defer exit accounting to handler */
1342 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1346 if (cause & CAUSEF_BD)
1349 kvm_get_badinstr(opc, vcpu, &inst);
1350 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1351 exccode, opc, inst, badvaddr,
1352 kvm_read_c0_guest_status(vcpu->arch.cop0));
1353 kvm_arch_vcpu_dump_regs(vcpu);
1354 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1361 local_irq_disable();
1363 if (ret == RESUME_GUEST)
1364 kvm_vz_acquire_htimer(vcpu);
1366 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1367 kvm_mips_deliver_interrupts(vcpu, cause);
1369 if (!(ret & RESUME_HOST)) {
1370 /* Only check for signals if not already exiting to userspace */
1371 if (signal_pending(current)) {
1372 run->exit_reason = KVM_EXIT_INTR;
1373 ret = (-EINTR << 2) | RESUME_HOST;
1374 ++vcpu->stat.signal_exits;
1375 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1379 if (ret == RESUME_GUEST) {
1380 trace_kvm_reenter(vcpu);
1383 * Make sure the read of VCPU requests in vcpu_reenter()
1384 * callback is not reordered ahead of the write to vcpu->mode,
1385 * or we could miss a TLB flush request while the requester sees
1386 * the VCPU as outside of guest mode and not needing an IPI.
1388 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1390 kvm_mips_callbacks->vcpu_reenter(vcpu);
1393 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1394 * is live), restore FCR31 / MSACSR.
1396 * This should be before returning to the guest exception
1397 * vector, as it may well cause an [MSA] FP exception if there
1398 * are pending exception bits unmasked. (see
1399 * kvm_mips_csr_die_notifier() for how that is handled).
1401 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1402 read_c0_status() & ST0_CU1)
1403 __kvm_restore_fcsr(&vcpu->arch);
1405 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1406 read_c0_config5() & MIPS_CONF5_MSAEN)
1407 __kvm_restore_msacsr(&vcpu->arch);
1410 /* Disable HTW before returning to guest or host */
1411 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1417 /* Enable FPU for guest and restore context */
1418 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1420 struct mips_coproc *cop0 = vcpu->arch.cop0;
1421 unsigned int sr, cfg5;
1425 sr = kvm_read_c0_guest_status(cop0);
1428 * If MSA state is already live, it is undefined how it interacts with
1429 * FR=0 FPU state, and we don't want to hit reserved instruction
1430 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1431 * play it safe and save it first.
1433 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1434 * get called when guest CU1 is set, however we can't trust the guest
1435 * not to clobber the status register directly via the commpage.
1437 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1438 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1442 * Enable FPU for guest
1443 * We set FR and FRE according to guest context
1445 change_c0_status(ST0_CU1 | ST0_FR, sr);
1447 cfg5 = kvm_read_c0_guest_config5(cop0);
1448 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1450 enable_fpu_hazard();
1452 /* If guest FPU state not active, restore it now */
1453 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1454 __kvm_restore_fpu(&vcpu->arch);
1455 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1456 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1458 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1464 #ifdef CONFIG_CPU_HAS_MSA
1465 /* Enable MSA for guest and restore context */
1466 void kvm_own_msa(struct kvm_vcpu *vcpu)
1468 struct mips_coproc *cop0 = vcpu->arch.cop0;
1469 unsigned int sr, cfg5;
1474 * Enable FPU if enabled in guest, since we're restoring FPU context
1475 * anyway. We set FR and FRE according to guest context.
1477 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1478 sr = kvm_read_c0_guest_status(cop0);
1481 * If FR=0 FPU state is already live, it is undefined how it
1482 * interacts with MSA state, so play it safe and save it first.
1484 if (!(sr & ST0_FR) &&
1485 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1486 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1489 change_c0_status(ST0_CU1 | ST0_FR, sr);
1490 if (sr & ST0_CU1 && cpu_has_fre) {
1491 cfg5 = kvm_read_c0_guest_config5(cop0);
1492 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1496 /* Enable MSA for guest */
1497 set_c0_config5(MIPS_CONF5_MSAEN);
1498 enable_fpu_hazard();
1500 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1501 case KVM_MIPS_AUX_FPU:
1503 * Guest FPU state already loaded, only restore upper MSA state
1505 __kvm_restore_msa_upper(&vcpu->arch);
1506 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1507 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1510 /* Neither FPU or MSA already active, restore full MSA state */
1511 __kvm_restore_msa(&vcpu->arch);
1512 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1513 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1514 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1515 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1516 KVM_TRACE_AUX_FPU_MSA);
1519 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1527 /* Drop FPU & MSA without saving it */
1528 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1531 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1533 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1534 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1536 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1537 clear_c0_status(ST0_CU1 | ST0_FR);
1538 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1539 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1544 /* Save and disable FPU & MSA */
1545 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1548 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1549 * is disabled in guest context (software), but the register state in
1550 * the hardware may still be in use.
1551 * This is why we explicitly re-enable the hardware before saving.
1555 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1556 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1557 set_c0_config5(MIPS_CONF5_MSAEN);
1558 enable_fpu_hazard();
1561 __kvm_save_msa(&vcpu->arch);
1562 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1564 /* Disable MSA & FPU */
1566 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1567 clear_c0_status(ST0_CU1 | ST0_FR);
1568 disable_fpu_hazard();
1570 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1571 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1572 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1573 set_c0_status(ST0_CU1);
1574 enable_fpu_hazard();
1577 __kvm_save_fpu(&vcpu->arch);
1578 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1579 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1582 clear_c0_status(ST0_CU1 | ST0_FR);
1583 disable_fpu_hazard();
1589 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1590 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1591 * exception if cause bits are set in the value being written.
1593 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1594 unsigned long cmd, void *ptr)
1596 struct die_args *args = (struct die_args *)ptr;
1597 struct pt_regs *regs = args->regs;
1600 /* Only interested in FPE and MSAFPE */
1601 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1604 /* Return immediately if guest context isn't active */
1605 if (!(current->flags & PF_VCPU))
1608 /* Should never get here from user mode */
1609 BUG_ON(user_mode(regs));
1611 pc = instruction_pointer(regs);
1614 /* match 2nd instruction in __kvm_restore_fcsr */
1615 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1619 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1621 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1622 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1627 /* Move PC forward a little and continue executing */
1628 instruction_pointer(regs) += 4;
1633 static struct notifier_block kvm_mips_csr_die_notifier = {
1634 .notifier_call = kvm_mips_csr_die_notify,
1637 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1638 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1639 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1640 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1641 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1644 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1645 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1646 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1647 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1648 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1651 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1653 u32 kvm_irq_to_priority(u32 irq)
1657 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1658 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1662 return MIPS_EXC_MAX;
1665 static int __init kvm_mips_init(void)
1670 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1674 ret = kvm_mips_entry_setup();
1678 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1683 if (boot_cpu_type() == CPU_LOONGSON64)
1684 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1686 register_die_notifier(&kvm_mips_csr_die_notifier);
1691 static void __exit kvm_mips_exit(void)
1695 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1698 module_init(kvm_mips_init);
1699 module_exit(kvm_mips_exit);
1701 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);