arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/memblock.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  43 struct kvm_stats_debugfs_item debugfs_entries[] = {
  44         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  45         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  46         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  47         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  48         { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  49         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  50         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  51         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  52         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  53         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  54         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  55         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  56         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  57         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  58         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  59         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  60         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  61         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  62 #ifdef CONFIG_KVM_MIPS_VZ
  63         { "vz_gpsi",      VCPU_STAT(vz_gpsi_exits),      KVM_STAT_VCPU },
  64         { "vz_gsfc",      VCPU_STAT(vz_gsfc_exits),      KVM_STAT_VCPU },
  65         { "vz_hc",        VCPU_STAT(vz_hc_exits),        KVM_STAT_VCPU },
  66         { "vz_grr",       VCPU_STAT(vz_grr_exits),       KVM_STAT_VCPU },
  67         { "vz_gva",       VCPU_STAT(vz_gva_exits),       KVM_STAT_VCPU },
  68         { "vz_ghfc",      VCPU_STAT(vz_ghfc_exits),      KVM_STAT_VCPU },
  69         { "vz_gpa",       VCPU_STAT(vz_gpa_exits),       KVM_STAT_VCPU },
  70         { "vz_resvd",     VCPU_STAT(vz_resvd_exits),     KVM_STAT_VCPU },
  71 #endif
  72         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  73         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  74         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  75         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  76         {NULL}
  77 };
  78
  79 bool kvm_trace_guest_mode_change;
  80
  81 int kvm_guest_mode_change_trace_reg(void)
  82 {
  83         kvm_trace_guest_mode_change = 1;
  84         return 0;
  85 }
  86
  87 void kvm_guest_mode_change_trace_unreg(void)
  88 {
  89         kvm_trace_guest_mode_change = 0;
  90 }
  91
  92 /*
  93  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  94  * Config7, so we are "runnable" if interrupts are pending
  95  */
  96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  97 {
  98         return !!(vcpu->arch.pending_exceptions);
  99 }
 100
 101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 102 {
 103         return false;
 104 }
 105
 106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 107 {
 108         return 1;
 109 }
 110
 111 int kvm_arch_hardware_enable(void)
 112 {
 113         return kvm_mips_callbacks->hardware_enable();
 114 }
 115
 116 void kvm_arch_hardware_disable(void)
 117 {
 118         kvm_mips_callbacks->hardware_disable();
 119 }
 120
 121 int kvm_arch_hardware_setup(void)
 122 {
 123         return 0;
 124 }
 125
 126 int kvm_arch_check_processor_compat(void)
 127 {
 128         return 0;
 129 }
 130
 131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 132 {
 133         switch (type) {
 134 #ifdef CONFIG_KVM_MIPS_VZ
 135         case KVM_VM_MIPS_VZ:
 136 #else
 137         case KVM_VM_MIPS_TE:
 138 #endif
 139                 break;
 140         default:
 141                 /* Unsupported KVM type */
 142                 return -EINVAL;
 143         };
 144
 145         /* Allocate page table to map GPA -> RPA */
 146         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 147         if (!kvm->arch.gpa_mm.pgd)
 148                 return -ENOMEM;
 149
 150         return 0;
 151 }
 152
 153 void kvm_mips_free_vcpus(struct kvm *kvm)
 154 {
 155         unsigned int i;
 156         struct kvm_vcpu *vcpu;
 157
 158         kvm_for_each_vcpu(i, vcpu, kvm) {
 159                 kvm_vcpu_destroy(vcpu);
 160         }
 161
 162         mutex_lock(&kvm->lock);
 163
 164         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 165                 kvm->vcpus[i] = NULL;
 166
 167         atomic_set(&kvm->online_vcpus, 0);
 168
 169         mutex_unlock(&kvm->lock);
 170 }
 171
 172 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 173 {
 174         /* It should always be safe to remove after flushing the whole range */
 175         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 176         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 177 }
 178
 179 void kvm_arch_destroy_vm(struct kvm *kvm)
 180 {
 181         kvm_mips_free_vcpus(kvm);
 182         kvm_mips_free_gpa_pt(kvm);
 183 }
 184
 185 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 186                         unsigned long arg)
 187 {
 188         return -ENOIOCTLCMD;
 189 }
 190
 191 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 192                             unsigned long npages)
 193 {
 194         return 0;
 195 }
 196
 197 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 198 {
 199         /* Flush whole GPA */
 200         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 201
 202         /* Let implementation do the rest */
 203         kvm_mips_callbacks->flush_shadow_all(kvm);
 204 }
 205
 206 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 207                                    struct kvm_memory_slot *slot)
 208 {
 209         /*
 210          * The slot has been made invalid (ready for moving or deletion), so we
 211          * need to ensure that it can no longer be accessed by any guest VCPUs.
 212          */
 213
 214         spin_lock(&kvm->mmu_lock);
 215         /* Flush slot from GPA */
 216         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 217                               slot->base_gfn + slot->npages - 1);
 218         /* Let implementation do the rest */
 219         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 220         spin_unlock(&kvm->mmu_lock);
 221 }
 222
 223 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 224                                    struct kvm_memory_slot *memslot,
 225                                    const struct kvm_userspace_memory_region *mem,
 226                                    enum kvm_mr_change change)
 227 {
 228         return 0;
 229 }
 230
 231 void kvm_arch_commit_memory_region(struct kvm *kvm,
 232                                    const struct kvm_userspace_memory_region *mem,
 233                                    const struct kvm_memory_slot *old,
 234                                    const struct kvm_memory_slot *new,
 235                                    enum kvm_mr_change change)
 236 {
 237         int needs_flush;
 238
 239         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 240                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 241                   mem->memory_size, mem->userspace_addr);
 242
 243         /*
 244          * If dirty page logging is enabled, write protect all pages in the slot
 245          * ready for dirty logging.
 246          *
 247          * There is no need to do this in any of the following cases:
 248          * CREATE:      No dirty mappings will already exist.
 249          * MOVE/DELETE: The old mappings will already have been cleaned up by
 250          *              kvm_arch_flush_shadow_memslot()
 251          */
 252         if (change == KVM_MR_FLAGS_ONLY &&
 253             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 254              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 255                 spin_lock(&kvm->mmu_lock);
 256                 /* Write protect GPA page table entries */
 257                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 258                                         new->base_gfn + new->npages - 1);
 259                 /* Let implementation do the rest */
 260                 if (needs_flush)
 261                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 262                 spin_unlock(&kvm->mmu_lock);
 263         }
 264 }
 265
 266 static inline void dump_handler(const char *symbol, void *start, void *end)
 267 {
 268         u32 *p;
 269
 270         pr_debug("LEAF(%s)\n", symbol);
 271
 272         pr_debug("\t.set push\n");
 273         pr_debug("\t.set noreorder\n");
 274
 275         for (p = start; p < (u32 *)end; ++p)
 276                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 277
 278         pr_debug("\t.set\tpop\n");
 279
 280         pr_debug("\tEND(%s)\n", symbol);
 281 }
 282
 283 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 284 {
 285         return 0;
 286 }
 287
 288 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 289 {
 290         int err, size;
 291         void *gebase, *p, *handler, *refill_start, *refill_end;
 292         int i;
 293
 294         kvm_debug("kvm @ %p: create cpu %d at %p\n",
 295                   vcpu->kvm, vcpu->vcpu_id, vcpu);
 296
 297         /*
 298          * Allocate space for host mode exception handlers that handle
 299          * guest mode exits
 300          */
 301         if (cpu_has_veic || cpu_has_vint)
 302                 size = 0x200 + VECTORSPACING * 64;
 303         else
 304                 size = 0x4000;
 305
 306         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 307
 308         if (!gebase) {
 309                 err = -ENOMEM;
 310                 goto out;
 311         }
 312         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 313                   ALIGN(size, PAGE_SIZE), gebase);
 314
 315         /*
 316          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 317          * limits us to the low 512MB of physical address space. If the memory
 318          * we allocate is out of range, just give up now.
 319          */
 320         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 321                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 322                         gebase);
 323                 err = -ENOMEM;
 324                 goto out_free_gebase;
 325         }
 326
 327         /* Save new ebase */
 328         vcpu->arch.guest_ebase = gebase;
 329
 330         /* Build guest exception vectors dynamically in unmapped memory */
 331         handler = gebase + 0x2000;
 332
 333         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 334         refill_start = gebase;
 335         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 336                 refill_start += 0x080;
 337         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 338
 339         /* General Exception Entry point */
 340         kvm_mips_build_exception(gebase + 0x180, handler);
 341
 342         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 343         for (i = 0; i < 8; i++) {
 344                 kvm_debug("L1 Vectored handler @ %p\n",
 345                           gebase + 0x200 + (i * VECTORSPACING));
 346                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 347                                          handler);
 348         }
 349
 350         /* General exit handler */
 351         p = handler;
 352         p = kvm_mips_build_exit(p);
 353
 354         /* Guest entry routine */
 355         vcpu->arch.vcpu_run = p;
 356         p = kvm_mips_build_vcpu_run(p);
 357
 358         /* Dump the generated code */
 359         pr_debug("#include <asm/asm.h>\n");
 360         pr_debug("#include <asm/regdef.h>\n");
 361         pr_debug("\n");
 362         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 363         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 364         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 365         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 366
 367         /* Invalidate the icache for these ranges */
 368         flush_icache_range((unsigned long)gebase,
 369                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 370
 371         /*
 372          * Allocate comm page for guest kernel, a TLB will be reserved for
 373          * mapping GVA @ 0xFFFF8000 to this page
 374          */
 375         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 376
 377         if (!vcpu->arch.kseg0_commpage) {
 378                 err = -ENOMEM;
 379                 goto out_free_gebase;
 380         }
 381
 382         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 383         kvm_mips_commpage_init(vcpu);
 384
 385         /* Init */
 386         vcpu->arch.last_sched_cpu = -1;
 387         vcpu->arch.last_exec_cpu = -1;
 388
 389         /* Initial guest state */
 390         err = kvm_mips_callbacks->vcpu_setup(vcpu);
 391         if (err)
 392                 goto out_free_commpage;
 393
 394         return 0;
 395
 396 out_free_commpage:
 397         kfree(vcpu->arch.kseg0_commpage);
 398 out_free_gebase:
 399         kfree(gebase);
 400 out:
 401         return err;
 402 }
 403
 404 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 405 {
 406         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 407
 408         kvm_mips_dump_stats(vcpu);
 409
 410         kvm_mmu_free_memory_caches(vcpu);
 411         kfree(vcpu->arch.guest_ebase);
 412         kfree(vcpu->arch.kseg0_commpage);
 413 }
 414
 415 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 416                                         struct kvm_guest_debug *dbg)
 417 {
 418         return -ENOIOCTLCMD;
 419 }
 420
 421 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 422 {
 423         int r = -EINTR;
 424
 425         vcpu_load(vcpu);
 426
 427         kvm_sigset_activate(vcpu);
 428
 429         if (vcpu->mmio_needed) {
 430                 if (!vcpu->mmio_is_write)
 431                         kvm_mips_complete_mmio_load(vcpu, run);
 432                 vcpu->mmio_needed = 0;
 433         }
 434
 435         if (run->immediate_exit)
 436                 goto out;
 437
 438         lose_fpu(1);
 439
 440         local_irq_disable();
 441         guest_enter_irqoff();
 442         trace_kvm_enter(vcpu);
 443
 444         /*
 445          * Make sure the read of VCPU requests in vcpu_run() callback is not
 446          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 447          * flush request while the requester sees the VCPU as outside of guest
 448          * mode and not needing an IPI.
 449          */
 450         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 451
 452         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 453
 454         trace_kvm_out(vcpu);
 455         guest_exit_irqoff();
 456         local_irq_enable();
 457
 458 out:
 459         kvm_sigset_deactivate(vcpu);
 460
 461         vcpu_put(vcpu);
 462         return r;
 463 }
 464
 465 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 466                              struct kvm_mips_interrupt *irq)
 467 {
 468         int intr = (int)irq->irq;
 469         struct kvm_vcpu *dvcpu = NULL;
 470
 471         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 472                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 473                           (int)intr);
 474
 475         if (irq->cpu == -1)
 476                 dvcpu = vcpu;
 477         else
 478                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 479
 480         if (intr == 2 || intr == 3 || intr == 4) {
 481                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 482
 483         } else if (intr == -2 || intr == -3 || intr == -4) {
 484                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 485         } else {
 486                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 487                         irq->cpu, irq->irq);
 488                 return -EINVAL;
 489         }
 490
 491         dvcpu->arch.wait = 0;
 492
 493         if (swq_has_sleeper(&dvcpu->wq))
 494                 swake_up_one(&dvcpu->wq);
 495
 496         return 0;
 497 }
 498
 499 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 500                                     struct kvm_mp_state *mp_state)
 501 {
 502         return -ENOIOCTLCMD;
 503 }
 504
 505 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 506                                     struct kvm_mp_state *mp_state)
 507 {
 508         return -ENOIOCTLCMD;
 509 }
 510
 511 static u64 kvm_mips_get_one_regs[] = {
 512         KVM_REG_MIPS_R0,
 513         KVM_REG_MIPS_R1,
 514         KVM_REG_MIPS_R2,
 515         KVM_REG_MIPS_R3,
 516         KVM_REG_MIPS_R4,
 517         KVM_REG_MIPS_R5,
 518         KVM_REG_MIPS_R6,
 519         KVM_REG_MIPS_R7,
 520         KVM_REG_MIPS_R8,
 521         KVM_REG_MIPS_R9,
 522         KVM_REG_MIPS_R10,
 523         KVM_REG_MIPS_R11,
 524         KVM_REG_MIPS_R12,
 525         KVM_REG_MIPS_R13,
 526         KVM_REG_MIPS_R14,
 527         KVM_REG_MIPS_R15,
 528         KVM_REG_MIPS_R16,
 529         KVM_REG_MIPS_R17,
 530         KVM_REG_MIPS_R18,
 531         KVM_REG_MIPS_R19,
 532         KVM_REG_MIPS_R20,
 533         KVM_REG_MIPS_R21,
 534         KVM_REG_MIPS_R22,
 535         KVM_REG_MIPS_R23,
 536         KVM_REG_MIPS_R24,
 537         KVM_REG_MIPS_R25,
 538         KVM_REG_MIPS_R26,
 539         KVM_REG_MIPS_R27,
 540         KVM_REG_MIPS_R28,
 541         KVM_REG_MIPS_R29,
 542         KVM_REG_MIPS_R30,
 543         KVM_REG_MIPS_R31,
 544
 545 #ifndef CONFIG_CPU_MIPSR6
 546         KVM_REG_MIPS_HI,
 547         KVM_REG_MIPS_LO,
 548 #endif
 549         KVM_REG_MIPS_PC,
 550 };
 551
 552 static u64 kvm_mips_get_one_regs_fpu[] = {
 553         KVM_REG_MIPS_FCR_IR,
 554         KVM_REG_MIPS_FCR_CSR,
 555 };
 556
 557 static u64 kvm_mips_get_one_regs_msa[] = {
 558         KVM_REG_MIPS_MSA_IR,
 559         KVM_REG_MIPS_MSA_CSR,
 560 };
 561
 562 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 563 {
 564         unsigned long ret;
 565
 566         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 567         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 568                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 569                 /* odd doubles */
 570                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 571                         ret += 16;
 572         }
 573         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 574                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 575         ret += kvm_mips_callbacks->num_regs(vcpu);
 576
 577         return ret;
 578 }
 579
 580 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 581 {
 582         u64 index;
 583         unsigned int i;
 584
 585         if (copy_to_user(indices, kvm_mips_get_one_regs,
 586                          sizeof(kvm_mips_get_one_regs)))
 587                 return -EFAULT;
 588         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 589
 590         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 591                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 592                                  sizeof(kvm_mips_get_one_regs_fpu)))
 593                         return -EFAULT;
 594                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 595
 596                 for (i = 0; i < 32; ++i) {
 597                         index = KVM_REG_MIPS_FPR_32(i);
 598                         if (copy_to_user(indices, &index, sizeof(index)))
 599                                 return -EFAULT;
 600                         ++indices;
 601
 602                         /* skip odd doubles if no F64 */
 603                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 604                                 continue;
 605
 606                         index = KVM_REG_MIPS_FPR_64(i);
 607                         if (copy_to_user(indices, &index, sizeof(index)))
 608                                 return -EFAULT;
 609                         ++indices;
 610                 }
 611         }
 612
 613         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 614                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 615                                  sizeof(kvm_mips_get_one_regs_msa)))
 616                         return -EFAULT;
 617                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 618
 619                 for (i = 0; i < 32; ++i) {
 620                         index = KVM_REG_MIPS_VEC_128(i);
 621                         if (copy_to_user(indices, &index, sizeof(index)))
 622                                 return -EFAULT;
 623                         ++indices;
 624                 }
 625         }
 626
 627         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 628 }
 629
 630 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 631                             const struct kvm_one_reg *reg)
 632 {
 633         struct mips_coproc *cop0 = vcpu->arch.cop0;
 634         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 635         int ret;
 636         s64 v;
 637         s64 vs[2];
 638         unsigned int idx;
 639
 640         switch (reg->id) {
 641         /* General purpose registers */
 642         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 643                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 644                 break;
 645 #ifndef CONFIG_CPU_MIPSR6
 646         case KVM_REG_MIPS_HI:
 647                 v = (long)vcpu->arch.hi;
 648                 break;
 649         case KVM_REG_MIPS_LO:
 650                 v = (long)vcpu->arch.lo;
 651                 break;
 652 #endif
 653         case KVM_REG_MIPS_PC:
 654                 v = (long)vcpu->arch.pc;
 655                 break;
 656
 657         /* Floating point registers */
 658         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 659                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 660                         return -EINVAL;
 661                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 662                 /* Odd singles in top of even double when FR=0 */
 663                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 664                         v = get_fpr32(&fpu->fpr[idx], 0);
 665                 else
 666                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 667                 break;
 668         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 669                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 670                         return -EINVAL;
 671                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 672                 /* Can't access odd doubles in FR=0 mode */
 673                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 674                         return -EINVAL;
 675                 v = get_fpr64(&fpu->fpr[idx], 0);
 676                 break;
 677         case KVM_REG_MIPS_FCR_IR:
 678                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 679                         return -EINVAL;
 680                 v = boot_cpu_data.fpu_id;
 681                 break;
 682         case KVM_REG_MIPS_FCR_CSR:
 683                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 684                         return -EINVAL;
 685                 v = fpu->fcr31;
 686                 break;
 687
 688         /* MIPS SIMD Architecture (MSA) registers */
 689         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 690                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 691                         return -EINVAL;
 692                 /* Can't access MSA registers in FR=0 mode */
 693                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 694                         return -EINVAL;
 695                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 696 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 697                 /* least significant byte first */
 698                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 699                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 700 #else
 701                 /* most significant byte first */
 702                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 703                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 704 #endif
 705                 break;
 706         case KVM_REG_MIPS_MSA_IR:
 707                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 708                         return -EINVAL;
 709                 v = boot_cpu_data.msa_id;
 710                 break;
 711         case KVM_REG_MIPS_MSA_CSR:
 712                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 713                         return -EINVAL;
 714                 v = fpu->msacsr;
 715                 break;
 716
 717         /* registers to be handled specially */
 718         default:
 719                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 720                 if (ret)
 721                         return ret;
 722                 break;
 723         }
 724         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 725                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 726
 727                 return put_user(v, uaddr64);
 728         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 729                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 730                 u32 v32 = (u32)v;
 731
 732                 return put_user(v32, uaddr32);
 733         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 734                 void __user *uaddr = (void __user *)(long)reg->addr;
 735
 736                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 737         } else {
 738                 return -EINVAL;
 739         }
 740 }
 741
 742 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 743                             const struct kvm_one_reg *reg)
 744 {
 745         struct mips_coproc *cop0 = vcpu->arch.cop0;
 746         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 747         s64 v;
 748         s64 vs[2];
 749         unsigned int idx;
 750
 751         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 752                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 753
 754                 if (get_user(v, uaddr64) != 0)
 755                         return -EFAULT;
 756         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 757                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 758                 s32 v32;
 759
 760                 if (get_user(v32, uaddr32) != 0)
 761                         return -EFAULT;
 762                 v = (s64)v32;
 763         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 764                 void __user *uaddr = (void __user *)(long)reg->addr;
 765
 766                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 767         } else {
 768                 return -EINVAL;
 769         }
 770
 771         switch (reg->id) {
 772         /* General purpose registers */
 773         case KVM_REG_MIPS_R0:
 774                 /* Silently ignore requests to set $0 */
 775                 break;
 776         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 777                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 778                 break;
 779 #ifndef CONFIG_CPU_MIPSR6
 780         case KVM_REG_MIPS_HI:
 781                 vcpu->arch.hi = v;
 782                 break;
 783         case KVM_REG_MIPS_LO:
 784                 vcpu->arch.lo = v;
 785                 break;
 786 #endif
 787         case KVM_REG_MIPS_PC:
 788                 vcpu->arch.pc = v;
 789                 break;
 790
 791         /* Floating point registers */
 792         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 793                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 794                         return -EINVAL;
 795                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 796                 /* Odd singles in top of even double when FR=0 */
 797                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 798                         set_fpr32(&fpu->fpr[idx], 0, v);
 799                 else
 800                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 801                 break;
 802         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 803                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 804                         return -EINVAL;
 805                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 806                 /* Can't access odd doubles in FR=0 mode */
 807                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 808                         return -EINVAL;
 809                 set_fpr64(&fpu->fpr[idx], 0, v);
 810                 break;
 811         case KVM_REG_MIPS_FCR_IR:
 812                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 813                         return -EINVAL;
 814                 /* Read-only */
 815                 break;
 816         case KVM_REG_MIPS_FCR_CSR:
 817                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 818                         return -EINVAL;
 819                 fpu->fcr31 = v;
 820                 break;
 821
 822         /* MIPS SIMD Architecture (MSA) registers */
 823         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 824                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 825                         return -EINVAL;
 826                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 827 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 828                 /* least significant byte first */
 829                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 830                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 831 #else
 832                 /* most significant byte first */
 833                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 834                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 835 #endif
 836                 break;
 837         case KVM_REG_MIPS_MSA_IR:
 838                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 839                         return -EINVAL;
 840                 /* Read-only */
 841                 break;
 842         case KVM_REG_MIPS_MSA_CSR:
 843                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 844                         return -EINVAL;
 845                 fpu->msacsr = v;
 846                 break;
 847
 848         /* registers to be handled specially */
 849         default:
 850                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 851         }
 852         return 0;
 853 }
 854
 855 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 856                                      struct kvm_enable_cap *cap)
 857 {
 858         int r = 0;
 859
 860         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 861                 return -EINVAL;
 862         if (cap->flags)
 863                 return -EINVAL;
 864         if (cap->args[0])
 865                 return -EINVAL;
 866
 867         switch (cap->cap) {
 868         case KVM_CAP_MIPS_FPU:
 869                 vcpu->arch.fpu_enabled = true;
 870                 break;
 871         case KVM_CAP_MIPS_MSA:
 872                 vcpu->arch.msa_enabled = true;
 873                 break;
 874         default:
 875                 r = -EINVAL;
 876                 break;
 877         }
 878
 879         return r;
 880 }
 881
 882 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 883                                unsigned long arg)
 884 {
 885         struct kvm_vcpu *vcpu = filp->private_data;
 886         void __user *argp = (void __user *)arg;
 887
 888         if (ioctl == KVM_INTERRUPT) {
 889                 struct kvm_mips_interrupt irq;
 890
 891                 if (copy_from_user(&irq, argp, sizeof(irq)))
 892                         return -EFAULT;
 893                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 894                           irq.irq);
 895
 896                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 897         }
 898
 899         return -ENOIOCTLCMD;
 900 }
 901
 902 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 903                          unsigned long arg)
 904 {
 905         struct kvm_vcpu *vcpu = filp->private_data;
 906         void __user *argp = (void __user *)arg;
 907         long r;
 908
 909         vcpu_load(vcpu);
 910
 911         switch (ioctl) {
 912         case KVM_SET_ONE_REG:
 913         case KVM_GET_ONE_REG: {
 914                 struct kvm_one_reg reg;
 915
 916                 r = -EFAULT;
 917                 if (copy_from_user(&reg, argp, sizeof(reg)))
 918                         break;
 919                 if (ioctl == KVM_SET_ONE_REG)
 920                         r = kvm_mips_set_reg(vcpu, &reg);
 921                 else
 922                         r = kvm_mips_get_reg(vcpu, &reg);
 923                 break;
 924         }
 925         case KVM_GET_REG_LIST: {
 926                 struct kvm_reg_list __user *user_list = argp;
 927                 struct kvm_reg_list reg_list;
 928                 unsigned n;
 929
 930                 r = -EFAULT;
 931                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 932                         break;
 933                 n = reg_list.n;
 934                 reg_list.n = kvm_mips_num_regs(vcpu);
 935                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 936                         break;
 937                 r = -E2BIG;
 938                 if (n < reg_list.n)
 939                         break;
 940                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 941                 break;
 942         }
 943         case KVM_ENABLE_CAP: {
 944                 struct kvm_enable_cap cap;
 945
 946                 r = -EFAULT;
 947                 if (copy_from_user(&cap, argp, sizeof(cap)))
 948                         break;
 949                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 950                 break;
 951         }
 952         default:
 953                 r = -ENOIOCTLCMD;
 954         }
 955
 956         vcpu_put(vcpu);
 957         return r;
 958 }
 959
 960 /**
 961  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
 962  * @kvm: kvm instance
 963  * @log: slot id and address to which we copy the log
 964  *
 965  * Steps 1-4 below provide general overview of dirty page logging. See
 966  * kvm_get_dirty_log_protect() function description for additional details.
 967  *
 968  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
 969  * always flush the TLB (step 4) even if previous step failed  and the dirty
 970  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
 971  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
 972  * writes will be marked dirty for next log read.
 973  *
 974  *   1. Take a snapshot of the bit and clear it if needed.
 975  *   2. Write protect the corresponding page.
 976  *   3. Copy the snapshot to the userspace.
 977  *   4. Flush TLB's if needed.
 978  */
 979 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
 980 {
 981         struct kvm_memslots *slots;
 982         struct kvm_memory_slot *memslot;
 983         bool flush = false;
 984         int r;
 985
 986         mutex_lock(&kvm->slots_lock);
 987
 988         r = kvm_get_dirty_log_protect(kvm, log, &flush);
 989
 990         if (flush) {
 991                 slots = kvm_memslots(kvm);
 992                 memslot = id_to_memslot(slots, log->slot);
 993
 994                 /* Let implementation handle TLB/GVA invalidation */
 995                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
 996         }
 997
 998         mutex_unlock(&kvm->slots_lock);
 999         return r;
1000 }
1001
1002 int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
1003 {
1004         struct kvm_memslots *slots;
1005         struct kvm_memory_slot *memslot;
1006         bool flush = false;
1007         int r;
1008
1009         mutex_lock(&kvm->slots_lock);
1010
1011         r = kvm_clear_dirty_log_protect(kvm, log, &flush);
1012
1013         if (flush) {
1014                 slots = kvm_memslots(kvm);
1015                 memslot = id_to_memslot(slots, log->slot);
1016
1017                 /* Let implementation handle TLB/GVA invalidation */
1018                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1019         }
1020
1021         mutex_unlock(&kvm->slots_lock);
1022         return r;
1023 }
1024
1025 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1026 {
1027         long r;
1028
1029         switch (ioctl) {
1030         default:
1031                 r = -ENOIOCTLCMD;
1032         }
1033
1034         return r;
1035 }
1036
1037 int kvm_arch_init(void *opaque)
1038 {
1039         if (kvm_mips_callbacks) {
1040                 kvm_err("kvm: module already exists\n");
1041                 return -EEXIST;
1042         }
1043
1044         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1045 }
1046
1047 void kvm_arch_exit(void)
1048 {
1049         kvm_mips_callbacks = NULL;
1050 }
1051
1052 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1053                                   struct kvm_sregs *sregs)
1054 {
1055         return -ENOIOCTLCMD;
1056 }
1057
1058 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1059                                   struct kvm_sregs *sregs)
1060 {
1061         return -ENOIOCTLCMD;
1062 }
1063
1064 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1065 {
1066 }
1067
1068 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1069 {
1070         return -ENOIOCTLCMD;
1071 }
1072
1073 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1074 {
1075         return -ENOIOCTLCMD;
1076 }
1077
1078 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1079 {
1080         return VM_FAULT_SIGBUS;
1081 }
1082
1083 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1084 {
1085         int r;
1086
1087         switch (ext) {
1088         case KVM_CAP_ONE_REG:
1089         case KVM_CAP_ENABLE_CAP:
1090         case KVM_CAP_READONLY_MEM:
1091         case KVM_CAP_SYNC_MMU:
1092         case KVM_CAP_IMMEDIATE_EXIT:
1093                 r = 1;
1094                 break;
1095         case KVM_CAP_NR_VCPUS:
1096                 r = num_online_cpus();
1097                 break;
1098         case KVM_CAP_MAX_VCPUS:
1099                 r = KVM_MAX_VCPUS;
1100                 break;
1101         case KVM_CAP_MAX_VCPU_ID:
1102                 r = KVM_MAX_VCPU_ID;
1103                 break;
1104         case KVM_CAP_MIPS_FPU:
1105                 /* We don't handle systems with inconsistent cpu_has_fpu */
1106                 r = !!raw_cpu_has_fpu;
1107                 break;
1108         case KVM_CAP_MIPS_MSA:
1109                 /*
1110                  * We don't support MSA vector partitioning yet:
1111                  * 1) It would require explicit support which can't be tested
1112                  *    yet due to lack of support in current hardware.
1113                  * 2) It extends the state that would need to be saved/restored
1114                  *    by e.g. QEMU for migration.
1115                  *
1116                  * When vector partitioning hardware becomes available, support
1117                  * could be added by requiring a flag when enabling
1118                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1119                  * to save/restore the appropriate extra state.
1120                  */
1121                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1122                 break;
1123         default:
1124                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1125                 break;
1126         }
1127         return r;
1128 }
1129
1130 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1131 {
1132         return kvm_mips_pending_timer(vcpu) ||
1133                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1134 }
1135
1136 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1137 {
1138         int i;
1139         struct mips_coproc *cop0;
1140
1141         if (!vcpu)
1142                 return -1;
1143
1144         kvm_debug("VCPU Register Dump:\n");
1145         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1146         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1147
1148         for (i = 0; i < 32; i += 4) {
1149                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1150                        vcpu->arch.gprs[i],
1151                        vcpu->arch.gprs[i + 1],
1152                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1153         }
1154         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1155         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1156
1157         cop0 = vcpu->arch.cop0;
1158         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1159                   kvm_read_c0_guest_status(cop0),
1160                   kvm_read_c0_guest_cause(cop0));
1161
1162         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1163
1164         return 0;
1165 }
1166
1167 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1168 {
1169         int i;
1170
1171         vcpu_load(vcpu);
1172
1173         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1174                 vcpu->arch.gprs[i] = regs->gpr[i];
1175         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1176         vcpu->arch.hi = regs->hi;
1177         vcpu->arch.lo = regs->lo;
1178         vcpu->arch.pc = regs->pc;
1179
1180         vcpu_put(vcpu);
1181         return 0;
1182 }
1183
1184 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1185 {
1186         int i;
1187
1188         vcpu_load(vcpu);
1189
1190         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1191                 regs->gpr[i] = vcpu->arch.gprs[i];
1192
1193         regs->hi = vcpu->arch.hi;
1194         regs->lo = vcpu->arch.lo;
1195         regs->pc = vcpu->arch.pc;
1196
1197         vcpu_put(vcpu);
1198         return 0;
1199 }
1200
1201 static void kvm_mips_comparecount_func(unsigned long data)
1202 {
1203         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1204
1205         kvm_mips_callbacks->queue_timer_int(vcpu);
1206
1207         vcpu->arch.wait = 0;
1208         if (swq_has_sleeper(&vcpu->wq))
1209                 swake_up_one(&vcpu->wq);
1210 }
1211
1212 /* low level hrtimer wake routine */
1213 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1214 {
1215         struct kvm_vcpu *vcpu;
1216
1217         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1218         kvm_mips_comparecount_func((unsigned long) vcpu);
1219         return kvm_mips_count_timeout(vcpu);
1220 }
1221
1222 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1223 {
1224         int err;
1225
1226         err = kvm_mips_callbacks->vcpu_init(vcpu);
1227         if (err)
1228                 return err;
1229
1230         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1231                      HRTIMER_MODE_REL);
1232         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1233         return 0;
1234 }
1235
1236 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1237 {
1238         kvm_mips_callbacks->vcpu_uninit(vcpu);
1239 }
1240
1241 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1242                                   struct kvm_translation *tr)
1243 {
1244         return 0;
1245 }
1246
1247 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1248 {
1249         return 0;
1250 }
1251
1252 static void kvm_mips_set_c0_status(void)
1253 {
1254         u32 status = read_c0_status();
1255
1256         if (cpu_has_dsp)
1257                 status |= (ST0_MX);
1258
1259         write_c0_status(status);
1260         ehb();
1261 }
1262
1263 /*
1264  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1265  */
1266 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1267 {
1268         u32 cause = vcpu->arch.host_cp0_cause;
1269         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1270         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1271         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1272         enum emulation_result er = EMULATE_DONE;
1273         u32 inst;
1274         int ret = RESUME_GUEST;
1275
1276         vcpu->mode = OUTSIDE_GUEST_MODE;
1277
1278         /* re-enable HTW before enabling interrupts */
1279         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1280                 htw_start();
1281
1282         /* Set a default exit reason */
1283         run->exit_reason = KVM_EXIT_UNKNOWN;
1284         run->ready_for_interrupt_injection = 1;
1285
1286         /*
1287          * Set the appropriate status bits based on host CPU features,
1288          * before we hit the scheduler
1289          */
1290         kvm_mips_set_c0_status();
1291
1292         local_irq_enable();
1293
1294         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1295                         cause, opc, run, vcpu);
1296         trace_kvm_exit(vcpu, exccode);
1297
1298         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1299                 /*
1300                  * Do a privilege check, if in UM most of these exit conditions
1301                  * end up causing an exception to be delivered to the Guest
1302                  * Kernel
1303                  */
1304                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1305                 if (er == EMULATE_PRIV_FAIL) {
1306                         goto skip_emul;
1307                 } else if (er == EMULATE_FAIL) {
1308                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1309                         ret = RESUME_HOST;
1310                         goto skip_emul;
1311                 }
1312         }
1313
1314         switch (exccode) {
1315         case EXCCODE_INT:
1316                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1317
1318                 ++vcpu->stat.int_exits;
1319
1320                 if (need_resched())
1321                         cond_resched();
1322
1323                 ret = RESUME_GUEST;
1324                 break;
1325
1326         case EXCCODE_CPU:
1327                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1328
1329                 ++vcpu->stat.cop_unusable_exits;
1330                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1331                 /* XXXKYMA: Might need to return to user space */
1332                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1333                         ret = RESUME_HOST;
1334                 break;
1335
1336         case EXCCODE_MOD:
1337                 ++vcpu->stat.tlbmod_exits;
1338                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1339                 break;
1340
1341         case EXCCODE_TLBS:
1342                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1343                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1344                           badvaddr);
1345
1346                 ++vcpu->stat.tlbmiss_st_exits;
1347                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1348                 break;
1349
1350         case EXCCODE_TLBL:
1351                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1352                           cause, opc, badvaddr);
1353
1354                 ++vcpu->stat.tlbmiss_ld_exits;
1355                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1356                 break;
1357
1358         case EXCCODE_ADES:
1359                 ++vcpu->stat.addrerr_st_exits;
1360                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1361                 break;
1362
1363         case EXCCODE_ADEL:
1364                 ++vcpu->stat.addrerr_ld_exits;
1365                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1366                 break;
1367
1368         case EXCCODE_SYS:
1369                 ++vcpu->stat.syscall_exits;
1370                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1371                 break;
1372
1373         case EXCCODE_RI:
1374                 ++vcpu->stat.resvd_inst_exits;
1375                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1376                 break;
1377
1378         case EXCCODE_BP:
1379                 ++vcpu->stat.break_inst_exits;
1380                 ret = kvm_mips_callbacks->handle_break(vcpu);
1381                 break;
1382
1383         case EXCCODE_TR:
1384                 ++vcpu->stat.trap_inst_exits;
1385                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1386                 break;
1387
1388         case EXCCODE_MSAFPE:
1389                 ++vcpu->stat.msa_fpe_exits;
1390                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1391                 break;
1392
1393         case EXCCODE_FPE:
1394                 ++vcpu->stat.fpe_exits;
1395                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1396                 break;
1397
1398         case EXCCODE_MSADIS:
1399                 ++vcpu->stat.msa_disabled_exits;
1400                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1401                 break;
1402
1403         case EXCCODE_GE:
1404                 /* defer exit accounting to handler */
1405                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1406                 break;
1407
1408         default:
1409                 if (cause & CAUSEF_BD)
1410                         opc += 1;
1411                 inst = 0;
1412                 kvm_get_badinstr(opc, vcpu, &inst);
1413                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1414                         exccode, opc, inst, badvaddr,
1415                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1416                 kvm_arch_vcpu_dump_regs(vcpu);
1417                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1418                 ret = RESUME_HOST;
1419                 break;
1420
1421         }
1422
1423 skip_emul:
1424         local_irq_disable();
1425
1426         if (ret == RESUME_GUEST)
1427                 kvm_vz_acquire_htimer(vcpu);
1428
1429         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1430                 kvm_mips_deliver_interrupts(vcpu, cause);
1431
1432         if (!(ret & RESUME_HOST)) {
1433                 /* Only check for signals if not already exiting to userspace */
1434                 if (signal_pending(current)) {
1435                         run->exit_reason = KVM_EXIT_INTR;
1436                         ret = (-EINTR << 2) | RESUME_HOST;
1437                         ++vcpu->stat.signal_exits;
1438                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1439                 }
1440         }
1441
1442         if (ret == RESUME_GUEST) {
1443                 trace_kvm_reenter(vcpu);
1444
1445                 /*
1446                  * Make sure the read of VCPU requests in vcpu_reenter()
1447                  * callback is not reordered ahead of the write to vcpu->mode,
1448                  * or we could miss a TLB flush request while the requester sees
1449                  * the VCPU as outside of guest mode and not needing an IPI.
1450                  */
1451                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1452
1453                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1454
1455                 /*
1456                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1457                  * is live), restore FCR31 / MSACSR.
1458                  *
1459                  * This should be before returning to the guest exception
1460                  * vector, as it may well cause an [MSA] FP exception if there
1461                  * are pending exception bits unmasked. (see
1462                  * kvm_mips_csr_die_notifier() for how that is handled).
1463                  */
1464                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1465                     read_c0_status() & ST0_CU1)
1466                         __kvm_restore_fcsr(&vcpu->arch);
1467
1468                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1469                     read_c0_config5() & MIPS_CONF5_MSAEN)
1470                         __kvm_restore_msacsr(&vcpu->arch);
1471         }
1472
1473         /* Disable HTW before returning to guest or host */
1474         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1475                 htw_stop();
1476
1477         return ret;
1478 }
1479
1480 /* Enable FPU for guest and restore context */
1481 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1482 {
1483         struct mips_coproc *cop0 = vcpu->arch.cop0;
1484         unsigned int sr, cfg5;
1485
1486         preempt_disable();
1487
1488         sr = kvm_read_c0_guest_status(cop0);
1489
1490         /*
1491          * If MSA state is already live, it is undefined how it interacts with
1492          * FR=0 FPU state, and we don't want to hit reserved instruction
1493          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1494          * play it safe and save it first.
1495          *
1496          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1497          * get called when guest CU1 is set, however we can't trust the guest
1498          * not to clobber the status register directly via the commpage.
1499          */
1500         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1501             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1502                 kvm_lose_fpu(vcpu);
1503
1504         /*
1505          * Enable FPU for guest
1506          * We set FR and FRE according to guest context
1507          */
1508         change_c0_status(ST0_CU1 | ST0_FR, sr);
1509         if (cpu_has_fre) {
1510                 cfg5 = kvm_read_c0_guest_config5(cop0);
1511                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1512         }
1513         enable_fpu_hazard();
1514
1515         /* If guest FPU state not active, restore it now */
1516         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1517                 __kvm_restore_fpu(&vcpu->arch);
1518                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1519                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1520         } else {
1521                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1522         }
1523
1524         preempt_enable();
1525 }
1526
1527 #ifdef CONFIG_CPU_HAS_MSA
1528 /* Enable MSA for guest and restore context */
1529 void kvm_own_msa(struct kvm_vcpu *vcpu)
1530 {
1531         struct mips_coproc *cop0 = vcpu->arch.cop0;
1532         unsigned int sr, cfg5;
1533
1534         preempt_disable();
1535
1536         /*
1537          * Enable FPU if enabled in guest, since we're restoring FPU context
1538          * anyway. We set FR and FRE according to guest context.
1539          */
1540         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1541                 sr = kvm_read_c0_guest_status(cop0);
1542
1543                 /*
1544                  * If FR=0 FPU state is already live, it is undefined how it
1545                  * interacts with MSA state, so play it safe and save it first.
1546                  */
1547                 if (!(sr & ST0_FR) &&
1548                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1549                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1550                         kvm_lose_fpu(vcpu);
1551
1552                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1553                 if (sr & ST0_CU1 && cpu_has_fre) {
1554                         cfg5 = kvm_read_c0_guest_config5(cop0);
1555                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1556                 }
1557         }
1558
1559         /* Enable MSA for guest */
1560         set_c0_config5(MIPS_CONF5_MSAEN);
1561         enable_fpu_hazard();
1562
1563         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1564         case KVM_MIPS_AUX_FPU:
1565                 /*
1566                  * Guest FPU state already loaded, only restore upper MSA state
1567                  */
1568                 __kvm_restore_msa_upper(&vcpu->arch);
1569                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1570                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1571                 break;
1572         case 0:
1573                 /* Neither FPU or MSA already active, restore full MSA state */
1574                 __kvm_restore_msa(&vcpu->arch);
1575                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1576                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1577                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1578                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1579                               KVM_TRACE_AUX_FPU_MSA);
1580                 break;
1581         default:
1582                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1583                 break;
1584         }
1585
1586         preempt_enable();
1587 }
1588 #endif
1589
1590 /* Drop FPU & MSA without saving it */
1591 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1592 {
1593         preempt_disable();
1594         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1595                 disable_msa();
1596                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1597                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1598         }
1599         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1600                 clear_c0_status(ST0_CU1 | ST0_FR);
1601                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1602                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1603         }
1604         preempt_enable();
1605 }
1606
1607 /* Save and disable FPU & MSA */
1608 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1609 {
1610         /*
1611          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1612          * is disabled in guest context (software), but the register state in
1613          * the hardware may still be in use.
1614          * This is why we explicitly re-enable the hardware before saving.
1615          */
1616
1617         preempt_disable();
1618         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1619                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1620                         set_c0_config5(MIPS_CONF5_MSAEN);
1621                         enable_fpu_hazard();
1622                 }
1623
1624                 __kvm_save_msa(&vcpu->arch);
1625                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1626
1627                 /* Disable MSA & FPU */
1628                 disable_msa();
1629                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1630                         clear_c0_status(ST0_CU1 | ST0_FR);
1631                         disable_fpu_hazard();
1632                 }
1633                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1634         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1635                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1636                         set_c0_status(ST0_CU1);
1637                         enable_fpu_hazard();
1638                 }
1639
1640                 __kvm_save_fpu(&vcpu->arch);
1641                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1642                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1643
1644                 /* Disable FPU */
1645                 clear_c0_status(ST0_CU1 | ST0_FR);
1646                 disable_fpu_hazard();
1647         }
1648         preempt_enable();
1649 }
1650
1651 /*
1652  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1653  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1654  * exception if cause bits are set in the value being written.
1655  */
1656 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1657                                    unsigned long cmd, void *ptr)
1658 {
1659         struct die_args *args = (struct die_args *)ptr;
1660         struct pt_regs *regs = args->regs;
1661         unsigned long pc;
1662
1663         /* Only interested in FPE and MSAFPE */
1664         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1665                 return NOTIFY_DONE;
1666
1667         /* Return immediately if guest context isn't active */
1668         if (!(current->flags & PF_VCPU))
1669                 return NOTIFY_DONE;
1670
1671         /* Should never get here from user mode */
1672         BUG_ON(user_mode(regs));
1673
1674         pc = instruction_pointer(regs);
1675         switch (cmd) {
1676         case DIE_FP:
1677                 /* match 2nd instruction in __kvm_restore_fcsr */
1678                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1679                         return NOTIFY_DONE;
1680                 break;
1681         case DIE_MSAFP:
1682                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1683                 if (!cpu_has_msa ||
1684                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1685                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1686                         return NOTIFY_DONE;
1687                 break;
1688         }
1689
1690         /* Move PC forward a little and continue executing */
1691         instruction_pointer(regs) += 4;
1692
1693         return NOTIFY_STOP;
1694 }
1695
1696 static struct notifier_block kvm_mips_csr_die_notifier = {
1697         .notifier_call = kvm_mips_csr_die_notify,
1698 };
1699
1700 static int __init kvm_mips_init(void)
1701 {
1702         int ret;
1703
1704         if (cpu_has_mmid) {
1705                 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1706                 return -EOPNOTSUPP;
1707         }
1708
1709         ret = kvm_mips_entry_setup();
1710         if (ret)
1711                 return ret;
1712
1713         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1714
1715         if (ret)
1716                 return ret;
1717
1718         register_die_notifier(&kvm_mips_csr_die_notifier);
1719
1720         return 0;
1721 }
1722
1723 static void __exit kvm_mips_exit(void)
1724 {
1725         kvm_exit();
1726
1727         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1728 }
1729
1730 module_init(kvm_mips_init);
1731 module_exit(kvm_mips_exit);
1732
1733 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);