arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/memblock.h>
  22 #include <linux/pgtable.h>
  23
  24 #include <asm/fpu.h>
  25 #include <asm/page.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/pgalloc.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33
  34 #define CREATE_TRACE_POINTS
  35 #include "trace.h"
  36
  37 #ifndef VECTORSPACING
  38 #define VECTORSPACING 0x100     /* for EI/VI mode */
  39 #endif
  40
  41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
  42         KVM_GENERIC_VM_STATS()
  43 };
  44
  45 const struct kvm_stats_header kvm_vm_stats_header = {
  46         .name_size = KVM_STATS_NAME_SIZE,
  47         .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
  48         .id_offset = sizeof(struct kvm_stats_header),
  49         .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
  50         .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
  51                        sizeof(kvm_vm_stats_desc),
  52 };
  53
  54 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
  55         KVM_GENERIC_VCPU_STATS(),
  56         STATS_DESC_COUNTER(VCPU, wait_exits),
  57         STATS_DESC_COUNTER(VCPU, cache_exits),
  58         STATS_DESC_COUNTER(VCPU, signal_exits),
  59         STATS_DESC_COUNTER(VCPU, int_exits),
  60         STATS_DESC_COUNTER(VCPU, cop_unusable_exits),
  61         STATS_DESC_COUNTER(VCPU, tlbmod_exits),
  62         STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits),
  63         STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits),
  64         STATS_DESC_COUNTER(VCPU, addrerr_st_exits),
  65         STATS_DESC_COUNTER(VCPU, addrerr_ld_exits),
  66         STATS_DESC_COUNTER(VCPU, syscall_exits),
  67         STATS_DESC_COUNTER(VCPU, resvd_inst_exits),
  68         STATS_DESC_COUNTER(VCPU, break_inst_exits),
  69         STATS_DESC_COUNTER(VCPU, trap_inst_exits),
  70         STATS_DESC_COUNTER(VCPU, msa_fpe_exits),
  71         STATS_DESC_COUNTER(VCPU, fpe_exits),
  72         STATS_DESC_COUNTER(VCPU, msa_disabled_exits),
  73         STATS_DESC_COUNTER(VCPU, flush_dcache_exits),
  74         STATS_DESC_COUNTER(VCPU, vz_gpsi_exits),
  75         STATS_DESC_COUNTER(VCPU, vz_gsfc_exits),
  76         STATS_DESC_COUNTER(VCPU, vz_hc_exits),
  77         STATS_DESC_COUNTER(VCPU, vz_grr_exits),
  78         STATS_DESC_COUNTER(VCPU, vz_gva_exits),
  79         STATS_DESC_COUNTER(VCPU, vz_ghfc_exits),
  80         STATS_DESC_COUNTER(VCPU, vz_gpa_exits),
  81         STATS_DESC_COUNTER(VCPU, vz_resvd_exits),
  82 #ifdef CONFIG_CPU_LOONGSON64
  83         STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits),
  84 #endif
  85 };
  86
  87 const struct kvm_stats_header kvm_vcpu_stats_header = {
  88         .name_size = KVM_STATS_NAME_SIZE,
  89         .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
  90         .id_offset = sizeof(struct kvm_stats_header),
  91         .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
  92         .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
  93                        sizeof(kvm_vcpu_stats_desc),
  94 };
  95
  96 bool kvm_trace_guest_mode_change;
  97
  98 int kvm_guest_mode_change_trace_reg(void)
  99 {
 100         kvm_trace_guest_mode_change = true;
 101         return 0;
 102 }
 103
 104 void kvm_guest_mode_change_trace_unreg(void)
 105 {
 106         kvm_trace_guest_mode_change = false;
 107 }
 108
 109 /*
 110  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
 111  * Config7, so we are "runnable" if interrupts are pending
 112  */
 113 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 114 {
 115         return !!(vcpu->arch.pending_exceptions);
 116 }
 117
 118 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 119 {
 120         return false;
 121 }
 122
 123 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 124 {
 125         return 1;
 126 }
 127
 128 int kvm_arch_hardware_enable(void)
 129 {
 130         return kvm_mips_callbacks->hardware_enable();
 131 }
 132
 133 void kvm_arch_hardware_disable(void)
 134 {
 135         kvm_mips_callbacks->hardware_disable();
 136 }
 137
 138 int kvm_arch_hardware_setup(void *opaque)
 139 {
 140         return 0;
 141 }
 142
 143 int kvm_arch_check_processor_compat(void *opaque)
 144 {
 145         return 0;
 146 }
 147
 148 extern void kvm_init_loongson_ipi(struct kvm *kvm);
 149
 150 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 151 {
 152         switch (type) {
 153         case KVM_VM_MIPS_AUTO:
 154                 break;
 155         case KVM_VM_MIPS_VZ:
 156                 break;
 157         default:
 158                 /* Unsupported KVM type */
 159                 return -EINVAL;
 160         }
 161
 162         /* Allocate page table to map GPA -> RPA */
 163         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 164         if (!kvm->arch.gpa_mm.pgd)
 165                 return -ENOMEM;
 166
 167 #ifdef CONFIG_CPU_LOONGSON64
 168         kvm_init_loongson_ipi(kvm);
 169 #endif
 170
 171         return 0;
 172 }
 173
 174 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 175 {
 176         /* It should always be safe to remove after flushing the whole range */
 177         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 178         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 179 }
 180
 181 void kvm_arch_destroy_vm(struct kvm *kvm)
 182 {
 183         kvm_destroy_vcpus(kvm);
 184         kvm_mips_free_gpa_pt(kvm);
 185 }
 186
 187 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 188                         unsigned long arg)
 189 {
 190         return -ENOIOCTLCMD;
 191 }
 192
 193 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 194 {
 195         /* Flush whole GPA */
 196         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 197         kvm_flush_remote_tlbs(kvm);
 198 }
 199
 200 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 201                                    struct kvm_memory_slot *slot)
 202 {
 203         /*
 204          * The slot has been made invalid (ready for moving or deletion), so we
 205          * need to ensure that it can no longer be accessed by any guest VCPUs.
 206          */
 207
 208         spin_lock(&kvm->mmu_lock);
 209         /* Flush slot from GPA */
 210         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 211                               slot->base_gfn + slot->npages - 1);
 212         kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
 213         spin_unlock(&kvm->mmu_lock);
 214 }
 215
 216 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 217                                    const struct kvm_userspace_memory_region *mem,
 218                                    const struct kvm_memory_slot *old,
 219                                    struct kvm_memory_slot *new,
 220                                    enum kvm_mr_change change)
 221 {
 222         return 0;
 223 }
 224
 225 void kvm_arch_commit_memory_region(struct kvm *kvm,
 226                                    const struct kvm_userspace_memory_region *mem,
 227                                    struct kvm_memory_slot *old,
 228                                    const struct kvm_memory_slot *new,
 229                                    enum kvm_mr_change change)
 230 {
 231         int needs_flush;
 232
 233         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 234                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 235                   mem->memory_size, mem->userspace_addr);
 236
 237         /*
 238          * If dirty page logging is enabled, write protect all pages in the slot
 239          * ready for dirty logging.
 240          *
 241          * There is no need to do this in any of the following cases:
 242          * CREATE:      No dirty mappings will already exist.
 243          * MOVE/DELETE: The old mappings will already have been cleaned up by
 244          *              kvm_arch_flush_shadow_memslot()
 245          */
 246         if (change == KVM_MR_FLAGS_ONLY &&
 247             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 248              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 249                 spin_lock(&kvm->mmu_lock);
 250                 /* Write protect GPA page table entries */
 251                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 252                                         new->base_gfn + new->npages - 1);
 253                 if (needs_flush)
 254                         kvm_arch_flush_remote_tlbs_memslot(kvm, new);
 255                 spin_unlock(&kvm->mmu_lock);
 256         }
 257 }
 258
 259 static inline void dump_handler(const char *symbol, void *start, void *end)
 260 {
 261         u32 *p;
 262
 263         pr_debug("LEAF(%s)\n", symbol);
 264
 265         pr_debug("\t.set push\n");
 266         pr_debug("\t.set noreorder\n");
 267
 268         for (p = start; p < (u32 *)end; ++p)
 269                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 270
 271         pr_debug("\t.set\tpop\n");
 272
 273         pr_debug("\tEND(%s)\n", symbol);
 274 }
 275
 276 /* low level hrtimer wake routine */
 277 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
 278 {
 279         struct kvm_vcpu *vcpu;
 280
 281         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
 282
 283         kvm_mips_callbacks->queue_timer_int(vcpu);
 284
 285         vcpu->arch.wait = 0;
 286         rcuwait_wake_up(&vcpu->wait);
 287
 288         return kvm_mips_count_timeout(vcpu);
 289 }
 290
 291 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 292 {
 293         return 0;
 294 }
 295
 296 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 297 {
 298         int err, size;
 299         void *gebase, *p, *handler, *refill_start, *refill_end;
 300         int i;
 301
 302         kvm_debug("kvm @ %p: create cpu %d at %p\n",
 303                   vcpu->kvm, vcpu->vcpu_id, vcpu);
 304
 305         err = kvm_mips_callbacks->vcpu_init(vcpu);
 306         if (err)
 307                 return err;
 308
 309         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
 310                      HRTIMER_MODE_REL);
 311         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
 312
 313         /*
 314          * Allocate space for host mode exception handlers that handle
 315          * guest mode exits
 316          */
 317         if (cpu_has_veic || cpu_has_vint)
 318                 size = 0x200 + VECTORSPACING * 64;
 319         else
 320                 size = 0x4000;
 321
 322         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 323
 324         if (!gebase) {
 325                 err = -ENOMEM;
 326                 goto out_uninit_vcpu;
 327         }
 328         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 329                   ALIGN(size, PAGE_SIZE), gebase);
 330
 331         /*
 332          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 333          * limits us to the low 512MB of physical address space. If the memory
 334          * we allocate is out of range, just give up now.
 335          */
 336         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 337                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 338                         gebase);
 339                 err = -ENOMEM;
 340                 goto out_free_gebase;
 341         }
 342
 343         /* Save new ebase */
 344         vcpu->arch.guest_ebase = gebase;
 345
 346         /* Build guest exception vectors dynamically in unmapped memory */
 347         handler = gebase + 0x2000;
 348
 349         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 350         refill_start = gebase;
 351         if (IS_ENABLED(CONFIG_64BIT))
 352                 refill_start += 0x080;
 353         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 354
 355         /* General Exception Entry point */
 356         kvm_mips_build_exception(gebase + 0x180, handler);
 357
 358         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 359         for (i = 0; i < 8; i++) {
 360                 kvm_debug("L1 Vectored handler @ %p\n",
 361                           gebase + 0x200 + (i * VECTORSPACING));
 362                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 363                                          handler);
 364         }
 365
 366         /* General exit handler */
 367         p = handler;
 368         p = kvm_mips_build_exit(p);
 369
 370         /* Guest entry routine */
 371         vcpu->arch.vcpu_run = p;
 372         p = kvm_mips_build_vcpu_run(p);
 373
 374         /* Dump the generated code */
 375         pr_debug("#include <asm/asm.h>\n");
 376         pr_debug("#include <asm/regdef.h>\n");
 377         pr_debug("\n");
 378         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 379         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 380         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 381         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 382
 383         /* Invalidate the icache for these ranges */
 384         flush_icache_range((unsigned long)gebase,
 385                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 386
 387         /* Init */
 388         vcpu->arch.last_sched_cpu = -1;
 389         vcpu->arch.last_exec_cpu = -1;
 390
 391         /* Initial guest state */
 392         err = kvm_mips_callbacks->vcpu_setup(vcpu);
 393         if (err)
 394                 goto out_free_gebase;
 395
 396         return 0;
 397
 398 out_free_gebase:
 399         kfree(gebase);
 400 out_uninit_vcpu:
 401         kvm_mips_callbacks->vcpu_uninit(vcpu);
 402         return err;
 403 }
 404
 405 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 406 {
 407         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 408
 409         kvm_mips_dump_stats(vcpu);
 410
 411         kvm_mmu_free_memory_caches(vcpu);
 412         kfree(vcpu->arch.guest_ebase);
 413
 414         kvm_mips_callbacks->vcpu_uninit(vcpu);
 415 }
 416
 417 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 418                                         struct kvm_guest_debug *dbg)
 419 {
 420         return -ENOIOCTLCMD;
 421 }
 422
 423 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
 424 {
 425         int r = -EINTR;
 426
 427         vcpu_load(vcpu);
 428
 429         kvm_sigset_activate(vcpu);
 430
 431         if (vcpu->mmio_needed) {
 432                 if (!vcpu->mmio_is_write)
 433                         kvm_mips_complete_mmio_load(vcpu);
 434                 vcpu->mmio_needed = 0;
 435         }
 436
 437         if (vcpu->run->immediate_exit)
 438                 goto out;
 439
 440         lose_fpu(1);
 441
 442         local_irq_disable();
 443         guest_enter_irqoff();
 444         trace_kvm_enter(vcpu);
 445
 446         /*
 447          * Make sure the read of VCPU requests in vcpu_run() callback is not
 448          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 449          * flush request while the requester sees the VCPU as outside of guest
 450          * mode and not needing an IPI.
 451          */
 452         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 453
 454         r = kvm_mips_callbacks->vcpu_run(vcpu);
 455
 456         trace_kvm_out(vcpu);
 457         guest_exit_irqoff();
 458         local_irq_enable();
 459
 460 out:
 461         kvm_sigset_deactivate(vcpu);
 462
 463         vcpu_put(vcpu);
 464         return r;
 465 }
 466
 467 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 468                              struct kvm_mips_interrupt *irq)
 469 {
 470         int intr = (int)irq->irq;
 471         struct kvm_vcpu *dvcpu = NULL;
 472
 473         if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
 474             intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
 475             intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
 476             intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
 477                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 478                           (int)intr);
 479
 480         if (irq->cpu == -1)
 481                 dvcpu = vcpu;
 482         else
 483                 dvcpu = kvm_get_vcpu(vcpu->kvm, irq->cpu);
 484
 485         if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
 486                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 487
 488         } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
 489                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 490         } else {
 491                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 492                         irq->cpu, irq->irq);
 493                 return -EINVAL;
 494         }
 495
 496         dvcpu->arch.wait = 0;
 497
 498         rcuwait_wake_up(&dvcpu->wait);
 499
 500         return 0;
 501 }
 502
 503 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 504                                     struct kvm_mp_state *mp_state)
 505 {
 506         return -ENOIOCTLCMD;
 507 }
 508
 509 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 510                                     struct kvm_mp_state *mp_state)
 511 {
 512         return -ENOIOCTLCMD;
 513 }
 514
 515 static u64 kvm_mips_get_one_regs[] = {
 516         KVM_REG_MIPS_R0,
 517         KVM_REG_MIPS_R1,
 518         KVM_REG_MIPS_R2,
 519         KVM_REG_MIPS_R3,
 520         KVM_REG_MIPS_R4,
 521         KVM_REG_MIPS_R5,
 522         KVM_REG_MIPS_R6,
 523         KVM_REG_MIPS_R7,
 524         KVM_REG_MIPS_R8,
 525         KVM_REG_MIPS_R9,
 526         KVM_REG_MIPS_R10,
 527         KVM_REG_MIPS_R11,
 528         KVM_REG_MIPS_R12,
 529         KVM_REG_MIPS_R13,
 530         KVM_REG_MIPS_R14,
 531         KVM_REG_MIPS_R15,
 532         KVM_REG_MIPS_R16,
 533         KVM_REG_MIPS_R17,
 534         KVM_REG_MIPS_R18,
 535         KVM_REG_MIPS_R19,
 536         KVM_REG_MIPS_R20,
 537         KVM_REG_MIPS_R21,
 538         KVM_REG_MIPS_R22,
 539         KVM_REG_MIPS_R23,
 540         KVM_REG_MIPS_R24,
 541         KVM_REG_MIPS_R25,
 542         KVM_REG_MIPS_R26,
 543         KVM_REG_MIPS_R27,
 544         KVM_REG_MIPS_R28,
 545         KVM_REG_MIPS_R29,
 546         KVM_REG_MIPS_R30,
 547         KVM_REG_MIPS_R31,
 548
 549 #ifndef CONFIG_CPU_MIPSR6
 550         KVM_REG_MIPS_HI,
 551         KVM_REG_MIPS_LO,
 552 #endif
 553         KVM_REG_MIPS_PC,
 554 };
 555
 556 static u64 kvm_mips_get_one_regs_fpu[] = {
 557         KVM_REG_MIPS_FCR_IR,
 558         KVM_REG_MIPS_FCR_CSR,
 559 };
 560
 561 static u64 kvm_mips_get_one_regs_msa[] = {
 562         KVM_REG_MIPS_MSA_IR,
 563         KVM_REG_MIPS_MSA_CSR,
 564 };
 565
 566 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 567 {
 568         unsigned long ret;
 569
 570         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 571         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 572                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 573                 /* odd doubles */
 574                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 575                         ret += 16;
 576         }
 577         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 578                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 579         ret += kvm_mips_callbacks->num_regs(vcpu);
 580
 581         return ret;
 582 }
 583
 584 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 585 {
 586         u64 index;
 587         unsigned int i;
 588
 589         if (copy_to_user(indices, kvm_mips_get_one_regs,
 590                          sizeof(kvm_mips_get_one_regs)))
 591                 return -EFAULT;
 592         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 593
 594         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 595                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 596                                  sizeof(kvm_mips_get_one_regs_fpu)))
 597                         return -EFAULT;
 598                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 599
 600                 for (i = 0; i < 32; ++i) {
 601                         index = KVM_REG_MIPS_FPR_32(i);
 602                         if (copy_to_user(indices, &index, sizeof(index)))
 603                                 return -EFAULT;
 604                         ++indices;
 605
 606                         /* skip odd doubles if no F64 */
 607                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 608                                 continue;
 609
 610                         index = KVM_REG_MIPS_FPR_64(i);
 611                         if (copy_to_user(indices, &index, sizeof(index)))
 612                                 return -EFAULT;
 613                         ++indices;
 614                 }
 615         }
 616
 617         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 618                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 619                                  sizeof(kvm_mips_get_one_regs_msa)))
 620                         return -EFAULT;
 621                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 622
 623                 for (i = 0; i < 32; ++i) {
 624                         index = KVM_REG_MIPS_VEC_128(i);
 625                         if (copy_to_user(indices, &index, sizeof(index)))
 626                                 return -EFAULT;
 627                         ++indices;
 628                 }
 629         }
 630
 631         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 632 }
 633
 634 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 635                             const struct kvm_one_reg *reg)
 636 {
 637         struct mips_coproc *cop0 = vcpu->arch.cop0;
 638         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 639         int ret;
 640         s64 v;
 641         s64 vs[2];
 642         unsigned int idx;
 643
 644         switch (reg->id) {
 645         /* General purpose registers */
 646         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 647                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 648                 break;
 649 #ifndef CONFIG_CPU_MIPSR6
 650         case KVM_REG_MIPS_HI:
 651                 v = (long)vcpu->arch.hi;
 652                 break;
 653         case KVM_REG_MIPS_LO:
 654                 v = (long)vcpu->arch.lo;
 655                 break;
 656 #endif
 657         case KVM_REG_MIPS_PC:
 658                 v = (long)vcpu->arch.pc;
 659                 break;
 660
 661         /* Floating point registers */
 662         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 663                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 664                         return -EINVAL;
 665                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 666                 /* Odd singles in top of even double when FR=0 */
 667                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 668                         v = get_fpr32(&fpu->fpr[idx], 0);
 669                 else
 670                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 671                 break;
 672         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 673                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 674                         return -EINVAL;
 675                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 676                 /* Can't access odd doubles in FR=0 mode */
 677                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 678                         return -EINVAL;
 679                 v = get_fpr64(&fpu->fpr[idx], 0);
 680                 break;
 681         case KVM_REG_MIPS_FCR_IR:
 682                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 683                         return -EINVAL;
 684                 v = boot_cpu_data.fpu_id;
 685                 break;
 686         case KVM_REG_MIPS_FCR_CSR:
 687                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 688                         return -EINVAL;
 689                 v = fpu->fcr31;
 690                 break;
 691
 692         /* MIPS SIMD Architecture (MSA) registers */
 693         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 694                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 695                         return -EINVAL;
 696                 /* Can't access MSA registers in FR=0 mode */
 697                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 698                         return -EINVAL;
 699                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 700 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 701                 /* least significant byte first */
 702                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 703                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 704 #else
 705                 /* most significant byte first */
 706                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 707                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 708 #endif
 709                 break;
 710         case KVM_REG_MIPS_MSA_IR:
 711                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 712                         return -EINVAL;
 713                 v = boot_cpu_data.msa_id;
 714                 break;
 715         case KVM_REG_MIPS_MSA_CSR:
 716                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 717                         return -EINVAL;
 718                 v = fpu->msacsr;
 719                 break;
 720
 721         /* registers to be handled specially */
 722         default:
 723                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 724                 if (ret)
 725                         return ret;
 726                 break;
 727         }
 728         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 729                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 730
 731                 return put_user(v, uaddr64);
 732         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 733                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 734                 u32 v32 = (u32)v;
 735
 736                 return put_user(v32, uaddr32);
 737         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 738                 void __user *uaddr = (void __user *)(long)reg->addr;
 739
 740                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 741         } else {
 742                 return -EINVAL;
 743         }
 744 }
 745
 746 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 747                             const struct kvm_one_reg *reg)
 748 {
 749         struct mips_coproc *cop0 = vcpu->arch.cop0;
 750         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 751         s64 v;
 752         s64 vs[2];
 753         unsigned int idx;
 754
 755         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 756                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 757
 758                 if (get_user(v, uaddr64) != 0)
 759                         return -EFAULT;
 760         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 761                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 762                 s32 v32;
 763
 764                 if (get_user(v32, uaddr32) != 0)
 765                         return -EFAULT;
 766                 v = (s64)v32;
 767         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 768                 void __user *uaddr = (void __user *)(long)reg->addr;
 769
 770                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 771         } else {
 772                 return -EINVAL;
 773         }
 774
 775         switch (reg->id) {
 776         /* General purpose registers */
 777         case KVM_REG_MIPS_R0:
 778                 /* Silently ignore requests to set $0 */
 779                 break;
 780         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 781                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 782                 break;
 783 #ifndef CONFIG_CPU_MIPSR6
 784         case KVM_REG_MIPS_HI:
 785                 vcpu->arch.hi = v;
 786                 break;
 787         case KVM_REG_MIPS_LO:
 788                 vcpu->arch.lo = v;
 789                 break;
 790 #endif
 791         case KVM_REG_MIPS_PC:
 792                 vcpu->arch.pc = v;
 793                 break;
 794
 795         /* Floating point registers */
 796         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 797                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 798                         return -EINVAL;
 799                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 800                 /* Odd singles in top of even double when FR=0 */
 801                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 802                         set_fpr32(&fpu->fpr[idx], 0, v);
 803                 else
 804                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 805                 break;
 806         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 807                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 808                         return -EINVAL;
 809                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 810                 /* Can't access odd doubles in FR=0 mode */
 811                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 812                         return -EINVAL;
 813                 set_fpr64(&fpu->fpr[idx], 0, v);
 814                 break;
 815         case KVM_REG_MIPS_FCR_IR:
 816                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 817                         return -EINVAL;
 818                 /* Read-only */
 819                 break;
 820         case KVM_REG_MIPS_FCR_CSR:
 821                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 822                         return -EINVAL;
 823                 fpu->fcr31 = v;
 824                 break;
 825
 826         /* MIPS SIMD Architecture (MSA) registers */
 827         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 828                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 829                         return -EINVAL;
 830                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 831 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 832                 /* least significant byte first */
 833                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 834                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 835 #else
 836                 /* most significant byte first */
 837                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 838                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 839 #endif
 840                 break;
 841         case KVM_REG_MIPS_MSA_IR:
 842                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 843                         return -EINVAL;
 844                 /* Read-only */
 845                 break;
 846         case KVM_REG_MIPS_MSA_CSR:
 847                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 848                         return -EINVAL;
 849                 fpu->msacsr = v;
 850                 break;
 851
 852         /* registers to be handled specially */
 853         default:
 854                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 855         }
 856         return 0;
 857 }
 858
 859 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 860                                      struct kvm_enable_cap *cap)
 861 {
 862         int r = 0;
 863
 864         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 865                 return -EINVAL;
 866         if (cap->flags)
 867                 return -EINVAL;
 868         if (cap->args[0])
 869                 return -EINVAL;
 870
 871         switch (cap->cap) {
 872         case KVM_CAP_MIPS_FPU:
 873                 vcpu->arch.fpu_enabled = true;
 874                 break;
 875         case KVM_CAP_MIPS_MSA:
 876                 vcpu->arch.msa_enabled = true;
 877                 break;
 878         default:
 879                 r = -EINVAL;
 880                 break;
 881         }
 882
 883         return r;
 884 }
 885
 886 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 887                                unsigned long arg)
 888 {
 889         struct kvm_vcpu *vcpu = filp->private_data;
 890         void __user *argp = (void __user *)arg;
 891
 892         if (ioctl == KVM_INTERRUPT) {
 893                 struct kvm_mips_interrupt irq;
 894
 895                 if (copy_from_user(&irq, argp, sizeof(irq)))
 896                         return -EFAULT;
 897                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 898                           irq.irq);
 899
 900                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 901         }
 902
 903         return -ENOIOCTLCMD;
 904 }
 905
 906 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 907                          unsigned long arg)
 908 {
 909         struct kvm_vcpu *vcpu = filp->private_data;
 910         void __user *argp = (void __user *)arg;
 911         long r;
 912
 913         vcpu_load(vcpu);
 914
 915         switch (ioctl) {
 916         case KVM_SET_ONE_REG:
 917         case KVM_GET_ONE_REG: {
 918                 struct kvm_one_reg reg;
 919
 920                 r = -EFAULT;
 921                 if (copy_from_user(&reg, argp, sizeof(reg)))
 922                         break;
 923                 if (ioctl == KVM_SET_ONE_REG)
 924                         r = kvm_mips_set_reg(vcpu, &reg);
 925                 else
 926                         r = kvm_mips_get_reg(vcpu, &reg);
 927                 break;
 928         }
 929         case KVM_GET_REG_LIST: {
 930                 struct kvm_reg_list __user *user_list = argp;
 931                 struct kvm_reg_list reg_list;
 932                 unsigned n;
 933
 934                 r = -EFAULT;
 935                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 936                         break;
 937                 n = reg_list.n;
 938                 reg_list.n = kvm_mips_num_regs(vcpu);
 939                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 940                         break;
 941                 r = -E2BIG;
 942                 if (n < reg_list.n)
 943                         break;
 944                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 945                 break;
 946         }
 947         case KVM_ENABLE_CAP: {
 948                 struct kvm_enable_cap cap;
 949
 950                 r = -EFAULT;
 951                 if (copy_from_user(&cap, argp, sizeof(cap)))
 952                         break;
 953                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 954                 break;
 955         }
 956         default:
 957                 r = -ENOIOCTLCMD;
 958         }
 959
 960         vcpu_put(vcpu);
 961         return r;
 962 }
 963
 964 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
 965 {
 966
 967 }
 968
 969 int kvm_arch_flush_remote_tlb(struct kvm *kvm)
 970 {
 971         kvm_mips_callbacks->prepare_flush_shadow(kvm);
 972         return 1;
 973 }
 974
 975 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
 976                                         const struct kvm_memory_slot *memslot)
 977 {
 978         kvm_flush_remote_tlbs(kvm);
 979 }
 980
 981 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
 982 {
 983         long r;
 984
 985         switch (ioctl) {
 986         default:
 987                 r = -ENOIOCTLCMD;
 988         }
 989
 990         return r;
 991 }
 992
 993 int kvm_arch_init(void *opaque)
 994 {
 995         if (kvm_mips_callbacks) {
 996                 kvm_err("kvm: module already exists\n");
 997                 return -EEXIST;
 998         }
 999
1000         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1001 }
1002
1003 void kvm_arch_exit(void)
1004 {
1005         kvm_mips_callbacks = NULL;
1006 }
1007
1008 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1009                                   struct kvm_sregs *sregs)
1010 {
1011         return -ENOIOCTLCMD;
1012 }
1013
1014 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1015                                   struct kvm_sregs *sregs)
1016 {
1017         return -ENOIOCTLCMD;
1018 }
1019
1020 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1021 {
1022 }
1023
1024 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1025 {
1026         return -ENOIOCTLCMD;
1027 }
1028
1029 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1030 {
1031         return -ENOIOCTLCMD;
1032 }
1033
1034 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1035 {
1036         return VM_FAULT_SIGBUS;
1037 }
1038
1039 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1040 {
1041         int r;
1042
1043         switch (ext) {
1044         case KVM_CAP_ONE_REG:
1045         case KVM_CAP_ENABLE_CAP:
1046         case KVM_CAP_READONLY_MEM:
1047         case KVM_CAP_SYNC_MMU:
1048         case KVM_CAP_IMMEDIATE_EXIT:
1049                 r = 1;
1050                 break;
1051         case KVM_CAP_NR_VCPUS:
1052                 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
1053                 break;
1054         case KVM_CAP_MAX_VCPUS:
1055                 r = KVM_MAX_VCPUS;
1056                 break;
1057         case KVM_CAP_MAX_VCPU_ID:
1058                 r = KVM_MAX_VCPU_IDS;
1059                 break;
1060         case KVM_CAP_MIPS_FPU:
1061                 /* We don't handle systems with inconsistent cpu_has_fpu */
1062                 r = !!raw_cpu_has_fpu;
1063                 break;
1064         case KVM_CAP_MIPS_MSA:
1065                 /*
1066                  * We don't support MSA vector partitioning yet:
1067                  * 1) It would require explicit support which can't be tested
1068                  *    yet due to lack of support in current hardware.
1069                  * 2) It extends the state that would need to be saved/restored
1070                  *    by e.g. QEMU for migration.
1071                  *
1072                  * When vector partitioning hardware becomes available, support
1073                  * could be added by requiring a flag when enabling
1074                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1075                  * to save/restore the appropriate extra state.
1076                  */
1077                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1078                 break;
1079         default:
1080                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1081                 break;
1082         }
1083         return r;
1084 }
1085
1086 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1087 {
1088         return kvm_mips_pending_timer(vcpu) ||
1089                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1090 }
1091
1092 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1093 {
1094         int i;
1095         struct mips_coproc *cop0;
1096
1097         if (!vcpu)
1098                 return -1;
1099
1100         kvm_debug("VCPU Register Dump:\n");
1101         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1102         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1103
1104         for (i = 0; i < 32; i += 4) {
1105                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1106                        vcpu->arch.gprs[i],
1107                        vcpu->arch.gprs[i + 1],
1108                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1109         }
1110         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1111         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1112
1113         cop0 = vcpu->arch.cop0;
1114         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1115                   kvm_read_c0_guest_status(cop0),
1116                   kvm_read_c0_guest_cause(cop0));
1117
1118         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1119
1120         return 0;
1121 }
1122
1123 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1124 {
1125         int i;
1126
1127         vcpu_load(vcpu);
1128
1129         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1130                 vcpu->arch.gprs[i] = regs->gpr[i];
1131         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1132         vcpu->arch.hi = regs->hi;
1133         vcpu->arch.lo = regs->lo;
1134         vcpu->arch.pc = regs->pc;
1135
1136         vcpu_put(vcpu);
1137         return 0;
1138 }
1139
1140 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1141 {
1142         int i;
1143
1144         vcpu_load(vcpu);
1145
1146         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1147                 regs->gpr[i] = vcpu->arch.gprs[i];
1148
1149         regs->hi = vcpu->arch.hi;
1150         regs->lo = vcpu->arch.lo;
1151         regs->pc = vcpu->arch.pc;
1152
1153         vcpu_put(vcpu);
1154         return 0;
1155 }
1156
1157 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1158                                   struct kvm_translation *tr)
1159 {
1160         return 0;
1161 }
1162
1163 static void kvm_mips_set_c0_status(void)
1164 {
1165         u32 status = read_c0_status();
1166
1167         if (cpu_has_dsp)
1168                 status |= (ST0_MX);
1169
1170         write_c0_status(status);
1171         ehb();
1172 }
1173
1174 /*
1175  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1176  */
1177 int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1178 {
1179         struct kvm_run *run = vcpu->run;
1180         u32 cause = vcpu->arch.host_cp0_cause;
1181         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1182         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1183         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1184         enum emulation_result er = EMULATE_DONE;
1185         u32 inst;
1186         int ret = RESUME_GUEST;
1187
1188         vcpu->mode = OUTSIDE_GUEST_MODE;
1189
1190         /* Set a default exit reason */
1191         run->exit_reason = KVM_EXIT_UNKNOWN;
1192         run->ready_for_interrupt_injection = 1;
1193
1194         /*
1195          * Set the appropriate status bits based on host CPU features,
1196          * before we hit the scheduler
1197          */
1198         kvm_mips_set_c0_status();
1199
1200         local_irq_enable();
1201
1202         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1203                         cause, opc, run, vcpu);
1204         trace_kvm_exit(vcpu, exccode);
1205
1206         switch (exccode) {
1207         case EXCCODE_INT:
1208                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1209
1210                 ++vcpu->stat.int_exits;
1211
1212                 if (need_resched())
1213                         cond_resched();
1214
1215                 ret = RESUME_GUEST;
1216                 break;
1217
1218         case EXCCODE_CPU:
1219                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1220
1221                 ++vcpu->stat.cop_unusable_exits;
1222                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1223                 /* XXXKYMA: Might need to return to user space */
1224                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1225                         ret = RESUME_HOST;
1226                 break;
1227
1228         case EXCCODE_MOD:
1229                 ++vcpu->stat.tlbmod_exits;
1230                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1231                 break;
1232
1233         case EXCCODE_TLBS:
1234                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1235                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1236                           badvaddr);
1237
1238                 ++vcpu->stat.tlbmiss_st_exits;
1239                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1240                 break;
1241
1242         case EXCCODE_TLBL:
1243                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1244                           cause, opc, badvaddr);
1245
1246                 ++vcpu->stat.tlbmiss_ld_exits;
1247                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1248                 break;
1249
1250         case EXCCODE_ADES:
1251                 ++vcpu->stat.addrerr_st_exits;
1252                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1253                 break;
1254
1255         case EXCCODE_ADEL:
1256                 ++vcpu->stat.addrerr_ld_exits;
1257                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1258                 break;
1259
1260         case EXCCODE_SYS:
1261                 ++vcpu->stat.syscall_exits;
1262                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1263                 break;
1264
1265         case EXCCODE_RI:
1266                 ++vcpu->stat.resvd_inst_exits;
1267                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1268                 break;
1269
1270         case EXCCODE_BP:
1271                 ++vcpu->stat.break_inst_exits;
1272                 ret = kvm_mips_callbacks->handle_break(vcpu);
1273                 break;
1274
1275         case EXCCODE_TR:
1276                 ++vcpu->stat.trap_inst_exits;
1277                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1278                 break;
1279
1280         case EXCCODE_MSAFPE:
1281                 ++vcpu->stat.msa_fpe_exits;
1282                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1283                 break;
1284
1285         case EXCCODE_FPE:
1286                 ++vcpu->stat.fpe_exits;
1287                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1288                 break;
1289
1290         case EXCCODE_MSADIS:
1291                 ++vcpu->stat.msa_disabled_exits;
1292                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1293                 break;
1294
1295         case EXCCODE_GE:
1296                 /* defer exit accounting to handler */
1297                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1298                 break;
1299
1300         default:
1301                 if (cause & CAUSEF_BD)
1302                         opc += 1;
1303                 inst = 0;
1304                 kvm_get_badinstr(opc, vcpu, &inst);
1305                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1306                         exccode, opc, inst, badvaddr,
1307                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1308                 kvm_arch_vcpu_dump_regs(vcpu);
1309                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1310                 ret = RESUME_HOST;
1311                 break;
1312
1313         }
1314
1315         local_irq_disable();
1316
1317         if (ret == RESUME_GUEST)
1318                 kvm_vz_acquire_htimer(vcpu);
1319
1320         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1321                 kvm_mips_deliver_interrupts(vcpu, cause);
1322
1323         if (!(ret & RESUME_HOST)) {
1324                 /* Only check for signals if not already exiting to userspace */
1325                 if (signal_pending(current)) {
1326                         run->exit_reason = KVM_EXIT_INTR;
1327                         ret = (-EINTR << 2) | RESUME_HOST;
1328                         ++vcpu->stat.signal_exits;
1329                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1330                 }
1331         }
1332
1333         if (ret == RESUME_GUEST) {
1334                 trace_kvm_reenter(vcpu);
1335
1336                 /*
1337                  * Make sure the read of VCPU requests in vcpu_reenter()
1338                  * callback is not reordered ahead of the write to vcpu->mode,
1339                  * or we could miss a TLB flush request while the requester sees
1340                  * the VCPU as outside of guest mode and not needing an IPI.
1341                  */
1342                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1343
1344                 kvm_mips_callbacks->vcpu_reenter(vcpu);
1345
1346                 /*
1347                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1348                  * is live), restore FCR31 / MSACSR.
1349                  *
1350                  * This should be before returning to the guest exception
1351                  * vector, as it may well cause an [MSA] FP exception if there
1352                  * are pending exception bits unmasked. (see
1353                  * kvm_mips_csr_die_notifier() for how that is handled).
1354                  */
1355                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1356                     read_c0_status() & ST0_CU1)
1357                         __kvm_restore_fcsr(&vcpu->arch);
1358
1359                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1360                     read_c0_config5() & MIPS_CONF5_MSAEN)
1361                         __kvm_restore_msacsr(&vcpu->arch);
1362         }
1363         return ret;
1364 }
1365
1366 /* Enable FPU for guest and restore context */
1367 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1368 {
1369         struct mips_coproc *cop0 = vcpu->arch.cop0;
1370         unsigned int sr, cfg5;
1371
1372         preempt_disable();
1373
1374         sr = kvm_read_c0_guest_status(cop0);
1375
1376         /*
1377          * If MSA state is already live, it is undefined how it interacts with
1378          * FR=0 FPU state, and we don't want to hit reserved instruction
1379          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1380          * play it safe and save it first.
1381          */
1382         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1383             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1384                 kvm_lose_fpu(vcpu);
1385
1386         /*
1387          * Enable FPU for guest
1388          * We set FR and FRE according to guest context
1389          */
1390         change_c0_status(ST0_CU1 | ST0_FR, sr);
1391         if (cpu_has_fre) {
1392                 cfg5 = kvm_read_c0_guest_config5(cop0);
1393                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1394         }
1395         enable_fpu_hazard();
1396
1397         /* If guest FPU state not active, restore it now */
1398         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1399                 __kvm_restore_fpu(&vcpu->arch);
1400                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1401                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1402         } else {
1403                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1404         }
1405
1406         preempt_enable();
1407 }
1408
1409 #ifdef CONFIG_CPU_HAS_MSA
1410 /* Enable MSA for guest and restore context */
1411 void kvm_own_msa(struct kvm_vcpu *vcpu)
1412 {
1413         struct mips_coproc *cop0 = vcpu->arch.cop0;
1414         unsigned int sr, cfg5;
1415
1416         preempt_disable();
1417
1418         /*
1419          * Enable FPU if enabled in guest, since we're restoring FPU context
1420          * anyway. We set FR and FRE according to guest context.
1421          */
1422         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1423                 sr = kvm_read_c0_guest_status(cop0);
1424
1425                 /*
1426                  * If FR=0 FPU state is already live, it is undefined how it
1427                  * interacts with MSA state, so play it safe and save it first.
1428                  */
1429                 if (!(sr & ST0_FR) &&
1430                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1431                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1432                         kvm_lose_fpu(vcpu);
1433
1434                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1435                 if (sr & ST0_CU1 && cpu_has_fre) {
1436                         cfg5 = kvm_read_c0_guest_config5(cop0);
1437                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1438                 }
1439         }
1440
1441         /* Enable MSA for guest */
1442         set_c0_config5(MIPS_CONF5_MSAEN);
1443         enable_fpu_hazard();
1444
1445         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1446         case KVM_MIPS_AUX_FPU:
1447                 /*
1448                  * Guest FPU state already loaded, only restore upper MSA state
1449                  */
1450                 __kvm_restore_msa_upper(&vcpu->arch);
1451                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1452                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1453                 break;
1454         case 0:
1455                 /* Neither FPU or MSA already active, restore full MSA state */
1456                 __kvm_restore_msa(&vcpu->arch);
1457                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1458                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1459                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1460                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1461                               KVM_TRACE_AUX_FPU_MSA);
1462                 break;
1463         default:
1464                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1465                 break;
1466         }
1467
1468         preempt_enable();
1469 }
1470 #endif
1471
1472 /* Drop FPU & MSA without saving it */
1473 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1474 {
1475         preempt_disable();
1476         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1477                 disable_msa();
1478                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1479                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1480         }
1481         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1482                 clear_c0_status(ST0_CU1 | ST0_FR);
1483                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1484                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1485         }
1486         preempt_enable();
1487 }
1488
1489 /* Save and disable FPU & MSA */
1490 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1491 {
1492         /*
1493          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1494          * is disabled in guest context (software), but the register state in
1495          * the hardware may still be in use.
1496          * This is why we explicitly re-enable the hardware before saving.
1497          */
1498
1499         preempt_disable();
1500         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1501                 __kvm_save_msa(&vcpu->arch);
1502                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1503
1504                 /* Disable MSA & FPU */
1505                 disable_msa();
1506                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1507                         clear_c0_status(ST0_CU1 | ST0_FR);
1508                         disable_fpu_hazard();
1509                 }
1510                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1511         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1512                 __kvm_save_fpu(&vcpu->arch);
1513                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1514                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1515
1516                 /* Disable FPU */
1517                 clear_c0_status(ST0_CU1 | ST0_FR);
1518                 disable_fpu_hazard();
1519         }
1520         preempt_enable();
1521 }
1522
1523 /*
1524  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1525  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1526  * exception if cause bits are set in the value being written.
1527  */
1528 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1529                                    unsigned long cmd, void *ptr)
1530 {
1531         struct die_args *args = (struct die_args *)ptr;
1532         struct pt_regs *regs = args->regs;
1533         unsigned long pc;
1534
1535         /* Only interested in FPE and MSAFPE */
1536         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1537                 return NOTIFY_DONE;
1538
1539         /* Return immediately if guest context isn't active */
1540         if (!(current->flags & PF_VCPU))
1541                 return NOTIFY_DONE;
1542
1543         /* Should never get here from user mode */
1544         BUG_ON(user_mode(regs));
1545
1546         pc = instruction_pointer(regs);
1547         switch (cmd) {
1548         case DIE_FP:
1549                 /* match 2nd instruction in __kvm_restore_fcsr */
1550                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1551                         return NOTIFY_DONE;
1552                 break;
1553         case DIE_MSAFP:
1554                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1555                 if (!cpu_has_msa ||
1556                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1557                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1558                         return NOTIFY_DONE;
1559                 break;
1560         }
1561
1562         /* Move PC forward a little and continue executing */
1563         instruction_pointer(regs) += 4;
1564
1565         return NOTIFY_STOP;
1566 }
1567
1568 static struct notifier_block kvm_mips_csr_die_notifier = {
1569         .notifier_call = kvm_mips_csr_die_notify,
1570 };
1571
1572 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1573         [MIPS_EXC_INT_TIMER] = C_IRQ5,
1574         [MIPS_EXC_INT_IO_1]  = C_IRQ0,
1575         [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1576         [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1577 };
1578
1579 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1580         [MIPS_EXC_INT_TIMER] = C_IRQ5,
1581         [MIPS_EXC_INT_IO_1]  = C_IRQ0,
1582         [MIPS_EXC_INT_IO_2]  = C_IRQ1,
1583         [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1584 };
1585
1586 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1587
1588 u32 kvm_irq_to_priority(u32 irq)
1589 {
1590         int i;
1591
1592         for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1593                 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1594                         return i;
1595         }
1596
1597         return MIPS_EXC_MAX;
1598 }
1599
1600 static int __init kvm_mips_init(void)
1601 {
1602         int ret;
1603
1604         if (cpu_has_mmid) {
1605                 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1606                 return -EOPNOTSUPP;
1607         }
1608
1609         ret = kvm_mips_entry_setup();
1610         if (ret)
1611                 return ret;
1612
1613         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1614
1615         if (ret)
1616                 return ret;
1617
1618         if (boot_cpu_type() == CPU_LOONGSON64)
1619                 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1620
1621         register_die_notifier(&kvm_mips_csr_die_notifier);
1622
1623         return 0;
1624 }
1625
1626 static void __exit kvm_mips_exit(void)
1627 {
1628         kvm_exit();
1629
1630         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1631 }
1632
1633 module_init(kvm_mips_init);
1634 module_exit(kvm_mips_exit);
1635
1636 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);