2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/memblock.h>
22 #include <linux/pgtable.h>
26 #include <asm/cacheflush.h>
27 #include <asm/mmu_context.h>
28 #include <asm/pgalloc.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
34 #define CREATE_TRACE_POINTS
38 #define VECTORSPACING 0x100 /* for EI/VI mode */
41 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
42 KVM_GENERIC_VM_STATS()
44 static_assert(ARRAY_SIZE(kvm_vm_stats_desc) ==
45 sizeof(struct kvm_vm_stat) / sizeof(u64));
47 const struct kvm_stats_header kvm_vm_stats_header = {
48 .name_size = KVM_STATS_NAME_SIZE,
49 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
50 .id_offset = sizeof(struct kvm_stats_header),
51 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
52 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
53 sizeof(kvm_vm_stats_desc),
56 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
57 KVM_GENERIC_VCPU_STATS(),
58 STATS_DESC_COUNTER(VCPU, wait_exits),
59 STATS_DESC_COUNTER(VCPU, cache_exits),
60 STATS_DESC_COUNTER(VCPU, signal_exits),
61 STATS_DESC_COUNTER(VCPU, int_exits),
62 STATS_DESC_COUNTER(VCPU, cop_unusable_exits),
63 STATS_DESC_COUNTER(VCPU, tlbmod_exits),
64 STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits),
65 STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits),
66 STATS_DESC_COUNTER(VCPU, addrerr_st_exits),
67 STATS_DESC_COUNTER(VCPU, addrerr_ld_exits),
68 STATS_DESC_COUNTER(VCPU, syscall_exits),
69 STATS_DESC_COUNTER(VCPU, resvd_inst_exits),
70 STATS_DESC_COUNTER(VCPU, break_inst_exits),
71 STATS_DESC_COUNTER(VCPU, trap_inst_exits),
72 STATS_DESC_COUNTER(VCPU, msa_fpe_exits),
73 STATS_DESC_COUNTER(VCPU, fpe_exits),
74 STATS_DESC_COUNTER(VCPU, msa_disabled_exits),
75 STATS_DESC_COUNTER(VCPU, flush_dcache_exits),
76 STATS_DESC_COUNTER(VCPU, vz_gpsi_exits),
77 STATS_DESC_COUNTER(VCPU, vz_gsfc_exits),
78 STATS_DESC_COUNTER(VCPU, vz_hc_exits),
79 STATS_DESC_COUNTER(VCPU, vz_grr_exits),
80 STATS_DESC_COUNTER(VCPU, vz_gva_exits),
81 STATS_DESC_COUNTER(VCPU, vz_ghfc_exits),
82 STATS_DESC_COUNTER(VCPU, vz_gpa_exits),
83 STATS_DESC_COUNTER(VCPU, vz_resvd_exits),
84 #ifdef CONFIG_CPU_LOONGSON64
85 STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits),
88 static_assert(ARRAY_SIZE(kvm_vcpu_stats_desc) ==
89 sizeof(struct kvm_vcpu_stat) / sizeof(u64));
91 const struct kvm_stats_header kvm_vcpu_stats_header = {
92 .name_size = KVM_STATS_NAME_SIZE,
93 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
94 .id_offset = sizeof(struct kvm_stats_header),
95 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
96 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
97 sizeof(kvm_vcpu_stats_desc),
100 bool kvm_trace_guest_mode_change;
102 int kvm_guest_mode_change_trace_reg(void)
104 kvm_trace_guest_mode_change = true;
108 void kvm_guest_mode_change_trace_unreg(void)
110 kvm_trace_guest_mode_change = false;
114 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
115 * Config7, so we are "runnable" if interrupts are pending
117 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
119 return !!(vcpu->arch.pending_exceptions);
122 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
127 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
132 int kvm_arch_hardware_enable(void)
134 return kvm_mips_callbacks->hardware_enable();
137 void kvm_arch_hardware_disable(void)
139 kvm_mips_callbacks->hardware_disable();
142 int kvm_arch_hardware_setup(void *opaque)
147 int kvm_arch_check_processor_compat(void *opaque)
152 extern void kvm_init_loongson_ipi(struct kvm *kvm);
154 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
157 case KVM_VM_MIPS_AUTO:
162 /* Unsupported KVM type */
166 /* Allocate page table to map GPA -> RPA */
167 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
168 if (!kvm->arch.gpa_mm.pgd)
171 #ifdef CONFIG_CPU_LOONGSON64
172 kvm_init_loongson_ipi(kvm);
178 void kvm_mips_free_vcpus(struct kvm *kvm)
181 struct kvm_vcpu *vcpu;
183 kvm_for_each_vcpu(i, vcpu, kvm) {
184 kvm_vcpu_destroy(vcpu);
187 mutex_lock(&kvm->lock);
189 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
190 kvm->vcpus[i] = NULL;
192 atomic_set(&kvm->online_vcpus, 0);
194 mutex_unlock(&kvm->lock);
197 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
199 /* It should always be safe to remove after flushing the whole range */
200 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
201 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
204 void kvm_arch_destroy_vm(struct kvm *kvm)
206 kvm_mips_free_vcpus(kvm);
207 kvm_mips_free_gpa_pt(kvm);
210 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
216 void kvm_arch_flush_shadow_all(struct kvm *kvm)
218 /* Flush whole GPA */
219 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
220 kvm_flush_remote_tlbs(kvm);
223 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
224 struct kvm_memory_slot *slot)
227 * The slot has been made invalid (ready for moving or deletion), so we
228 * need to ensure that it can no longer be accessed by any guest VCPUs.
231 spin_lock(&kvm->mmu_lock);
232 /* Flush slot from GPA */
233 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
234 slot->base_gfn + slot->npages - 1);
235 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
236 spin_unlock(&kvm->mmu_lock);
239 int kvm_arch_prepare_memory_region(struct kvm *kvm,
240 struct kvm_memory_slot *memslot,
241 const struct kvm_userspace_memory_region *mem,
242 enum kvm_mr_change change)
247 void kvm_arch_commit_memory_region(struct kvm *kvm,
248 const struct kvm_userspace_memory_region *mem,
249 struct kvm_memory_slot *old,
250 const struct kvm_memory_slot *new,
251 enum kvm_mr_change change)
255 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
256 __func__, kvm, mem->slot, mem->guest_phys_addr,
257 mem->memory_size, mem->userspace_addr);
260 * If dirty page logging is enabled, write protect all pages in the slot
261 * ready for dirty logging.
263 * There is no need to do this in any of the following cases:
264 * CREATE: No dirty mappings will already exist.
265 * MOVE/DELETE: The old mappings will already have been cleaned up by
266 * kvm_arch_flush_shadow_memslot()
268 if (change == KVM_MR_FLAGS_ONLY &&
269 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
270 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
271 spin_lock(&kvm->mmu_lock);
272 /* Write protect GPA page table entries */
273 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
274 new->base_gfn + new->npages - 1);
276 kvm_arch_flush_remote_tlbs_memslot(kvm, new);
277 spin_unlock(&kvm->mmu_lock);
281 static inline void dump_handler(const char *symbol, void *start, void *end)
285 pr_debug("LEAF(%s)\n", symbol);
287 pr_debug("\t.set push\n");
288 pr_debug("\t.set noreorder\n");
290 for (p = start; p < (u32 *)end; ++p)
291 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
293 pr_debug("\t.set\tpop\n");
295 pr_debug("\tEND(%s)\n", symbol);
298 /* low level hrtimer wake routine */
299 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
301 struct kvm_vcpu *vcpu;
303 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
305 kvm_mips_callbacks->queue_timer_int(vcpu);
308 rcuwait_wake_up(&vcpu->wait);
310 return kvm_mips_count_timeout(vcpu);
313 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
318 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
321 void *gebase, *p, *handler, *refill_start, *refill_end;
324 kvm_debug("kvm @ %p: create cpu %d at %p\n",
325 vcpu->kvm, vcpu->vcpu_id, vcpu);
327 err = kvm_mips_callbacks->vcpu_init(vcpu);
331 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
333 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
336 * Allocate space for host mode exception handlers that handle
339 if (cpu_has_veic || cpu_has_vint)
340 size = 0x200 + VECTORSPACING * 64;
344 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
348 goto out_uninit_vcpu;
350 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
351 ALIGN(size, PAGE_SIZE), gebase);
354 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
355 * limits us to the low 512MB of physical address space. If the memory
356 * we allocate is out of range, just give up now.
358 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
359 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
362 goto out_free_gebase;
366 vcpu->arch.guest_ebase = gebase;
368 /* Build guest exception vectors dynamically in unmapped memory */
369 handler = gebase + 0x2000;
371 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
372 refill_start = gebase;
373 if (IS_ENABLED(CONFIG_64BIT))
374 refill_start += 0x080;
375 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
377 /* General Exception Entry point */
378 kvm_mips_build_exception(gebase + 0x180, handler);
380 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
381 for (i = 0; i < 8; i++) {
382 kvm_debug("L1 Vectored handler @ %p\n",
383 gebase + 0x200 + (i * VECTORSPACING));
384 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
388 /* General exit handler */
390 p = kvm_mips_build_exit(p);
392 /* Guest entry routine */
393 vcpu->arch.vcpu_run = p;
394 p = kvm_mips_build_vcpu_run(p);
396 /* Dump the generated code */
397 pr_debug("#include <asm/asm.h>\n");
398 pr_debug("#include <asm/regdef.h>\n");
400 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
401 dump_handler("kvm_tlb_refill", refill_start, refill_end);
402 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
403 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
405 /* Invalidate the icache for these ranges */
406 flush_icache_range((unsigned long)gebase,
407 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
410 vcpu->arch.last_sched_cpu = -1;
411 vcpu->arch.last_exec_cpu = -1;
413 /* Initial guest state */
414 err = kvm_mips_callbacks->vcpu_setup(vcpu);
416 goto out_free_gebase;
423 kvm_mips_callbacks->vcpu_uninit(vcpu);
427 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
429 hrtimer_cancel(&vcpu->arch.comparecount_timer);
431 kvm_mips_dump_stats(vcpu);
433 kvm_mmu_free_memory_caches(vcpu);
434 kfree(vcpu->arch.guest_ebase);
436 kvm_mips_callbacks->vcpu_uninit(vcpu);
439 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
440 struct kvm_guest_debug *dbg)
445 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
451 kvm_sigset_activate(vcpu);
453 if (vcpu->mmio_needed) {
454 if (!vcpu->mmio_is_write)
455 kvm_mips_complete_mmio_load(vcpu);
456 vcpu->mmio_needed = 0;
459 if (vcpu->run->immediate_exit)
465 guest_enter_irqoff();
466 trace_kvm_enter(vcpu);
469 * Make sure the read of VCPU requests in vcpu_run() callback is not
470 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
471 * flush request while the requester sees the VCPU as outside of guest
472 * mode and not needing an IPI.
474 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
476 r = kvm_mips_callbacks->vcpu_run(vcpu);
483 kvm_sigset_deactivate(vcpu);
489 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
490 struct kvm_mips_interrupt *irq)
492 int intr = (int)irq->irq;
493 struct kvm_vcpu *dvcpu = NULL;
495 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
496 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
497 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
498 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
499 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
505 dvcpu = vcpu->kvm->vcpus[irq->cpu];
507 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
508 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
510 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
511 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
513 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
518 dvcpu->arch.wait = 0;
520 rcuwait_wake_up(&dvcpu->wait);
525 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
526 struct kvm_mp_state *mp_state)
531 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
532 struct kvm_mp_state *mp_state)
537 static u64 kvm_mips_get_one_regs[] = {
571 #ifndef CONFIG_CPU_MIPSR6
578 static u64 kvm_mips_get_one_regs_fpu[] = {
580 KVM_REG_MIPS_FCR_CSR,
583 static u64 kvm_mips_get_one_regs_msa[] = {
585 KVM_REG_MIPS_MSA_CSR,
588 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
592 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
593 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
594 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
596 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
599 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
600 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
601 ret += kvm_mips_callbacks->num_regs(vcpu);
606 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
611 if (copy_to_user(indices, kvm_mips_get_one_regs,
612 sizeof(kvm_mips_get_one_regs)))
614 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
616 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
617 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
618 sizeof(kvm_mips_get_one_regs_fpu)))
620 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
622 for (i = 0; i < 32; ++i) {
623 index = KVM_REG_MIPS_FPR_32(i);
624 if (copy_to_user(indices, &index, sizeof(index)))
628 /* skip odd doubles if no F64 */
629 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
632 index = KVM_REG_MIPS_FPR_64(i);
633 if (copy_to_user(indices, &index, sizeof(index)))
639 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
640 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
641 sizeof(kvm_mips_get_one_regs_msa)))
643 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
645 for (i = 0; i < 32; ++i) {
646 index = KVM_REG_MIPS_VEC_128(i);
647 if (copy_to_user(indices, &index, sizeof(index)))
653 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
656 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
657 const struct kvm_one_reg *reg)
659 struct mips_coproc *cop0 = vcpu->arch.cop0;
660 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
667 /* General purpose registers */
668 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
669 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
671 #ifndef CONFIG_CPU_MIPSR6
672 case KVM_REG_MIPS_HI:
673 v = (long)vcpu->arch.hi;
675 case KVM_REG_MIPS_LO:
676 v = (long)vcpu->arch.lo;
679 case KVM_REG_MIPS_PC:
680 v = (long)vcpu->arch.pc;
683 /* Floating point registers */
684 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
685 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
687 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
688 /* Odd singles in top of even double when FR=0 */
689 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
690 v = get_fpr32(&fpu->fpr[idx], 0);
692 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
694 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
695 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
697 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
698 /* Can't access odd doubles in FR=0 mode */
699 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
701 v = get_fpr64(&fpu->fpr[idx], 0);
703 case KVM_REG_MIPS_FCR_IR:
704 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
706 v = boot_cpu_data.fpu_id;
708 case KVM_REG_MIPS_FCR_CSR:
709 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
714 /* MIPS SIMD Architecture (MSA) registers */
715 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
716 if (!kvm_mips_guest_has_msa(&vcpu->arch))
718 /* Can't access MSA registers in FR=0 mode */
719 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
721 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
722 #ifdef CONFIG_CPU_LITTLE_ENDIAN
723 /* least significant byte first */
724 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
725 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
727 /* most significant byte first */
728 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
729 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
732 case KVM_REG_MIPS_MSA_IR:
733 if (!kvm_mips_guest_has_msa(&vcpu->arch))
735 v = boot_cpu_data.msa_id;
737 case KVM_REG_MIPS_MSA_CSR:
738 if (!kvm_mips_guest_has_msa(&vcpu->arch))
743 /* registers to be handled specially */
745 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
750 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
751 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
753 return put_user(v, uaddr64);
754 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
755 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
758 return put_user(v32, uaddr32);
759 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
760 void __user *uaddr = (void __user *)(long)reg->addr;
762 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
768 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
769 const struct kvm_one_reg *reg)
771 struct mips_coproc *cop0 = vcpu->arch.cop0;
772 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
777 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
778 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
780 if (get_user(v, uaddr64) != 0)
782 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
783 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
786 if (get_user(v32, uaddr32) != 0)
789 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
790 void __user *uaddr = (void __user *)(long)reg->addr;
792 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
798 /* General purpose registers */
799 case KVM_REG_MIPS_R0:
800 /* Silently ignore requests to set $0 */
802 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
803 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
805 #ifndef CONFIG_CPU_MIPSR6
806 case KVM_REG_MIPS_HI:
809 case KVM_REG_MIPS_LO:
813 case KVM_REG_MIPS_PC:
817 /* Floating point registers */
818 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
819 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
821 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
822 /* Odd singles in top of even double when FR=0 */
823 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
824 set_fpr32(&fpu->fpr[idx], 0, v);
826 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
828 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
829 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
831 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
832 /* Can't access odd doubles in FR=0 mode */
833 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
835 set_fpr64(&fpu->fpr[idx], 0, v);
837 case KVM_REG_MIPS_FCR_IR:
838 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
842 case KVM_REG_MIPS_FCR_CSR:
843 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
848 /* MIPS SIMD Architecture (MSA) registers */
849 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
850 if (!kvm_mips_guest_has_msa(&vcpu->arch))
852 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
853 #ifdef CONFIG_CPU_LITTLE_ENDIAN
854 /* least significant byte first */
855 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
856 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
858 /* most significant byte first */
859 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
860 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
863 case KVM_REG_MIPS_MSA_IR:
864 if (!kvm_mips_guest_has_msa(&vcpu->arch))
868 case KVM_REG_MIPS_MSA_CSR:
869 if (!kvm_mips_guest_has_msa(&vcpu->arch))
874 /* registers to be handled specially */
876 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
881 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
882 struct kvm_enable_cap *cap)
886 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
894 case KVM_CAP_MIPS_FPU:
895 vcpu->arch.fpu_enabled = true;
897 case KVM_CAP_MIPS_MSA:
898 vcpu->arch.msa_enabled = true;
908 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
911 struct kvm_vcpu *vcpu = filp->private_data;
912 void __user *argp = (void __user *)arg;
914 if (ioctl == KVM_INTERRUPT) {
915 struct kvm_mips_interrupt irq;
917 if (copy_from_user(&irq, argp, sizeof(irq)))
919 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
922 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
928 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
931 struct kvm_vcpu *vcpu = filp->private_data;
932 void __user *argp = (void __user *)arg;
938 case KVM_SET_ONE_REG:
939 case KVM_GET_ONE_REG: {
940 struct kvm_one_reg reg;
943 if (copy_from_user(®, argp, sizeof(reg)))
945 if (ioctl == KVM_SET_ONE_REG)
946 r = kvm_mips_set_reg(vcpu, ®);
948 r = kvm_mips_get_reg(vcpu, ®);
951 case KVM_GET_REG_LIST: {
952 struct kvm_reg_list __user *user_list = argp;
953 struct kvm_reg_list reg_list;
957 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
960 reg_list.n = kvm_mips_num_regs(vcpu);
961 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
966 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
969 case KVM_ENABLE_CAP: {
970 struct kvm_enable_cap cap;
973 if (copy_from_user(&cap, argp, sizeof(cap)))
975 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
986 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
991 int kvm_arch_flush_remote_tlb(struct kvm *kvm)
993 kvm_mips_callbacks->prepare_flush_shadow(kvm);
997 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
998 const struct kvm_memory_slot *memslot)
1000 kvm_flush_remote_tlbs(kvm);
1003 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1015 int kvm_arch_init(void *opaque)
1017 if (kvm_mips_callbacks) {
1018 kvm_err("kvm: module already exists\n");
1022 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1025 void kvm_arch_exit(void)
1027 kvm_mips_callbacks = NULL;
1030 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1031 struct kvm_sregs *sregs)
1033 return -ENOIOCTLCMD;
1036 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1037 struct kvm_sregs *sregs)
1039 return -ENOIOCTLCMD;
1042 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1046 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1048 return -ENOIOCTLCMD;
1051 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1053 return -ENOIOCTLCMD;
1056 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1058 return VM_FAULT_SIGBUS;
1061 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1066 case KVM_CAP_ONE_REG:
1067 case KVM_CAP_ENABLE_CAP:
1068 case KVM_CAP_READONLY_MEM:
1069 case KVM_CAP_SYNC_MMU:
1070 case KVM_CAP_IMMEDIATE_EXIT:
1073 case KVM_CAP_NR_VCPUS:
1074 r = num_online_cpus();
1076 case KVM_CAP_MAX_VCPUS:
1079 case KVM_CAP_MAX_VCPU_ID:
1080 r = KVM_MAX_VCPU_ID;
1082 case KVM_CAP_MIPS_FPU:
1083 /* We don't handle systems with inconsistent cpu_has_fpu */
1084 r = !!raw_cpu_has_fpu;
1086 case KVM_CAP_MIPS_MSA:
1088 * We don't support MSA vector partitioning yet:
1089 * 1) It would require explicit support which can't be tested
1090 * yet due to lack of support in current hardware.
1091 * 2) It extends the state that would need to be saved/restored
1092 * by e.g. QEMU for migration.
1094 * When vector partitioning hardware becomes available, support
1095 * could be added by requiring a flag when enabling
1096 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1097 * to save/restore the appropriate extra state.
1099 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1102 r = kvm_mips_callbacks->check_extension(kvm, ext);
1108 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1110 return kvm_mips_pending_timer(vcpu) ||
1111 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1114 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1117 struct mips_coproc *cop0;
1122 kvm_debug("VCPU Register Dump:\n");
1123 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1124 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1126 for (i = 0; i < 32; i += 4) {
1127 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1129 vcpu->arch.gprs[i + 1],
1130 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1132 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1133 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1135 cop0 = vcpu->arch.cop0;
1136 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1137 kvm_read_c0_guest_status(cop0),
1138 kvm_read_c0_guest_cause(cop0));
1140 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1145 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1151 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1152 vcpu->arch.gprs[i] = regs->gpr[i];
1153 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1154 vcpu->arch.hi = regs->hi;
1155 vcpu->arch.lo = regs->lo;
1156 vcpu->arch.pc = regs->pc;
1162 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1168 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1169 regs->gpr[i] = vcpu->arch.gprs[i];
1171 regs->hi = vcpu->arch.hi;
1172 regs->lo = vcpu->arch.lo;
1173 regs->pc = vcpu->arch.pc;
1179 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1180 struct kvm_translation *tr)
1185 static void kvm_mips_set_c0_status(void)
1187 u32 status = read_c0_status();
1192 write_c0_status(status);
1197 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1199 int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1201 struct kvm_run *run = vcpu->run;
1202 u32 cause = vcpu->arch.host_cp0_cause;
1203 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1204 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1205 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1206 enum emulation_result er = EMULATE_DONE;
1208 int ret = RESUME_GUEST;
1210 vcpu->mode = OUTSIDE_GUEST_MODE;
1212 /* Set a default exit reason */
1213 run->exit_reason = KVM_EXIT_UNKNOWN;
1214 run->ready_for_interrupt_injection = 1;
1217 * Set the appropriate status bits based on host CPU features,
1218 * before we hit the scheduler
1220 kvm_mips_set_c0_status();
1224 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1225 cause, opc, run, vcpu);
1226 trace_kvm_exit(vcpu, exccode);
1230 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1232 ++vcpu->stat.int_exits;
1241 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1243 ++vcpu->stat.cop_unusable_exits;
1244 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1245 /* XXXKYMA: Might need to return to user space */
1246 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1251 ++vcpu->stat.tlbmod_exits;
1252 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1256 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1257 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1260 ++vcpu->stat.tlbmiss_st_exits;
1261 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1265 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1266 cause, opc, badvaddr);
1268 ++vcpu->stat.tlbmiss_ld_exits;
1269 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1273 ++vcpu->stat.addrerr_st_exits;
1274 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1278 ++vcpu->stat.addrerr_ld_exits;
1279 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1283 ++vcpu->stat.syscall_exits;
1284 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1288 ++vcpu->stat.resvd_inst_exits;
1289 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1293 ++vcpu->stat.break_inst_exits;
1294 ret = kvm_mips_callbacks->handle_break(vcpu);
1298 ++vcpu->stat.trap_inst_exits;
1299 ret = kvm_mips_callbacks->handle_trap(vcpu);
1302 case EXCCODE_MSAFPE:
1303 ++vcpu->stat.msa_fpe_exits;
1304 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1308 ++vcpu->stat.fpe_exits;
1309 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1312 case EXCCODE_MSADIS:
1313 ++vcpu->stat.msa_disabled_exits;
1314 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1318 /* defer exit accounting to handler */
1319 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1323 if (cause & CAUSEF_BD)
1326 kvm_get_badinstr(opc, vcpu, &inst);
1327 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1328 exccode, opc, inst, badvaddr,
1329 kvm_read_c0_guest_status(vcpu->arch.cop0));
1330 kvm_arch_vcpu_dump_regs(vcpu);
1331 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1337 local_irq_disable();
1339 if (ret == RESUME_GUEST)
1340 kvm_vz_acquire_htimer(vcpu);
1342 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1343 kvm_mips_deliver_interrupts(vcpu, cause);
1345 if (!(ret & RESUME_HOST)) {
1346 /* Only check for signals if not already exiting to userspace */
1347 if (signal_pending(current)) {
1348 run->exit_reason = KVM_EXIT_INTR;
1349 ret = (-EINTR << 2) | RESUME_HOST;
1350 ++vcpu->stat.signal_exits;
1351 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1355 if (ret == RESUME_GUEST) {
1356 trace_kvm_reenter(vcpu);
1359 * Make sure the read of VCPU requests in vcpu_reenter()
1360 * callback is not reordered ahead of the write to vcpu->mode,
1361 * or we could miss a TLB flush request while the requester sees
1362 * the VCPU as outside of guest mode and not needing an IPI.
1364 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1366 kvm_mips_callbacks->vcpu_reenter(vcpu);
1369 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1370 * is live), restore FCR31 / MSACSR.
1372 * This should be before returning to the guest exception
1373 * vector, as it may well cause an [MSA] FP exception if there
1374 * are pending exception bits unmasked. (see
1375 * kvm_mips_csr_die_notifier() for how that is handled).
1377 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1378 read_c0_status() & ST0_CU1)
1379 __kvm_restore_fcsr(&vcpu->arch);
1381 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1382 read_c0_config5() & MIPS_CONF5_MSAEN)
1383 __kvm_restore_msacsr(&vcpu->arch);
1388 /* Enable FPU for guest and restore context */
1389 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1391 struct mips_coproc *cop0 = vcpu->arch.cop0;
1392 unsigned int sr, cfg5;
1396 sr = kvm_read_c0_guest_status(cop0);
1399 * If MSA state is already live, it is undefined how it interacts with
1400 * FR=0 FPU state, and we don't want to hit reserved instruction
1401 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1402 * play it safe and save it first.
1404 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1405 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1409 * Enable FPU for guest
1410 * We set FR and FRE according to guest context
1412 change_c0_status(ST0_CU1 | ST0_FR, sr);
1414 cfg5 = kvm_read_c0_guest_config5(cop0);
1415 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1417 enable_fpu_hazard();
1419 /* If guest FPU state not active, restore it now */
1420 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1421 __kvm_restore_fpu(&vcpu->arch);
1422 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1423 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1425 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1431 #ifdef CONFIG_CPU_HAS_MSA
1432 /* Enable MSA for guest and restore context */
1433 void kvm_own_msa(struct kvm_vcpu *vcpu)
1435 struct mips_coproc *cop0 = vcpu->arch.cop0;
1436 unsigned int sr, cfg5;
1441 * Enable FPU if enabled in guest, since we're restoring FPU context
1442 * anyway. We set FR and FRE according to guest context.
1444 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1445 sr = kvm_read_c0_guest_status(cop0);
1448 * If FR=0 FPU state is already live, it is undefined how it
1449 * interacts with MSA state, so play it safe and save it first.
1451 if (!(sr & ST0_FR) &&
1452 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1453 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1456 change_c0_status(ST0_CU1 | ST0_FR, sr);
1457 if (sr & ST0_CU1 && cpu_has_fre) {
1458 cfg5 = kvm_read_c0_guest_config5(cop0);
1459 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1463 /* Enable MSA for guest */
1464 set_c0_config5(MIPS_CONF5_MSAEN);
1465 enable_fpu_hazard();
1467 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1468 case KVM_MIPS_AUX_FPU:
1470 * Guest FPU state already loaded, only restore upper MSA state
1472 __kvm_restore_msa_upper(&vcpu->arch);
1473 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1474 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1477 /* Neither FPU or MSA already active, restore full MSA state */
1478 __kvm_restore_msa(&vcpu->arch);
1479 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1480 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1481 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1482 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1483 KVM_TRACE_AUX_FPU_MSA);
1486 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1494 /* Drop FPU & MSA without saving it */
1495 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1498 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1500 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1501 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1503 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1504 clear_c0_status(ST0_CU1 | ST0_FR);
1505 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1506 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1511 /* Save and disable FPU & MSA */
1512 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1515 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1516 * is disabled in guest context (software), but the register state in
1517 * the hardware may still be in use.
1518 * This is why we explicitly re-enable the hardware before saving.
1522 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1523 __kvm_save_msa(&vcpu->arch);
1524 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1526 /* Disable MSA & FPU */
1528 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1529 clear_c0_status(ST0_CU1 | ST0_FR);
1530 disable_fpu_hazard();
1532 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1533 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1534 __kvm_save_fpu(&vcpu->arch);
1535 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1536 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1539 clear_c0_status(ST0_CU1 | ST0_FR);
1540 disable_fpu_hazard();
1546 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1547 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1548 * exception if cause bits are set in the value being written.
1550 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1551 unsigned long cmd, void *ptr)
1553 struct die_args *args = (struct die_args *)ptr;
1554 struct pt_regs *regs = args->regs;
1557 /* Only interested in FPE and MSAFPE */
1558 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1561 /* Return immediately if guest context isn't active */
1562 if (!(current->flags & PF_VCPU))
1565 /* Should never get here from user mode */
1566 BUG_ON(user_mode(regs));
1568 pc = instruction_pointer(regs);
1571 /* match 2nd instruction in __kvm_restore_fcsr */
1572 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1576 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1578 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1579 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1584 /* Move PC forward a little and continue executing */
1585 instruction_pointer(regs) += 4;
1590 static struct notifier_block kvm_mips_csr_die_notifier = {
1591 .notifier_call = kvm_mips_csr_die_notify,
1594 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1595 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1596 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1597 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1598 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1601 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1602 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1603 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1604 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1605 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1608 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1610 u32 kvm_irq_to_priority(u32 irq)
1614 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1615 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1619 return MIPS_EXC_MAX;
1622 static int __init kvm_mips_init(void)
1627 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1631 ret = kvm_mips_entry_setup();
1635 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1640 if (boot_cpu_type() == CPU_LOONGSON64)
1641 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1643 register_die_notifier(&kvm_mips_csr_die_notifier);
1648 static void __exit kvm_mips_exit(void)
1652 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1655 module_init(kvm_mips_init);
1656 module_exit(kvm_mips_exit);
1658 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);