arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sched/signal.h>
  20 #include <linux/fs.h>
  21 #include <linux/memblock.h>
  22
  23 #include <asm/fpu.h>
  24 #include <asm/page.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28 #include <asm/pgtable.h>
  29
  30 #include <linux/kvm_host.h>
  31
  32 #include "interrupt.h"
  33 #include "commpage.h"
  34
  35 #define CREATE_TRACE_POINTS
  36 #include "trace.h"
  37
  38 #ifndef VECTORSPACING
  39 #define VECTORSPACING 0x100     /* for EI/VI mode */
  40 #endif
  41
  42 struct kvm_stats_debugfs_item debugfs_entries[] = {
  43         VCPU_STAT("wait", wait_exits),
  44         VCPU_STAT("cache", cache_exits),
  45         VCPU_STAT("signal", signal_exits),
  46         VCPU_STAT("interrupt", int_exits),
  47         VCPU_STAT("cop_unusable", cop_unusable_exits),
  48         VCPU_STAT("tlbmod", tlbmod_exits),
  49         VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits),
  50         VCPU_STAT("tlbmiss_st", tlbmiss_st_exits),
  51         VCPU_STAT("addrerr_st", addrerr_st_exits),
  52         VCPU_STAT("addrerr_ld", addrerr_ld_exits),
  53         VCPU_STAT("syscall", syscall_exits),
  54         VCPU_STAT("resvd_inst", resvd_inst_exits),
  55         VCPU_STAT("break_inst", break_inst_exits),
  56         VCPU_STAT("trap_inst", trap_inst_exits),
  57         VCPU_STAT("msa_fpe", msa_fpe_exits),
  58         VCPU_STAT("fpe", fpe_exits),
  59         VCPU_STAT("msa_disabled", msa_disabled_exits),
  60         VCPU_STAT("flush_dcache", flush_dcache_exits),
  61 #ifdef CONFIG_KVM_MIPS_VZ
  62         VCPU_STAT("vz_gpsi", vz_gpsi_exits),
  63         VCPU_STAT("vz_gsfc", vz_gsfc_exits),
  64         VCPU_STAT("vz_hc", vz_hc_exits),
  65         VCPU_STAT("vz_grr", vz_grr_exits),
  66         VCPU_STAT("vz_gva", vz_gva_exits),
  67         VCPU_STAT("vz_ghfc", vz_ghfc_exits),
  68         VCPU_STAT("vz_gpa", vz_gpa_exits),
  69         VCPU_STAT("vz_resvd", vz_resvd_exits),
  70 #endif
  71         VCPU_STAT("halt_successful_poll", halt_successful_poll),
  72         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
  73         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
  74         VCPU_STAT("halt_wakeup", halt_wakeup),
  75         {NULL}
  76 };
  77
  78 bool kvm_trace_guest_mode_change;
  79
  80 int kvm_guest_mode_change_trace_reg(void)
  81 {
  82         kvm_trace_guest_mode_change = 1;
  83         return 0;
  84 }
  85
  86 void kvm_guest_mode_change_trace_unreg(void)
  87 {
  88         kvm_trace_guest_mode_change = 0;
  89 }
  90
  91 /*
  92  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  93  * Config7, so we are "runnable" if interrupts are pending
  94  */
  95 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  96 {
  97         return !!(vcpu->arch.pending_exceptions);
  98 }
  99
 100 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 101 {
 102         return false;
 103 }
 104
 105 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 106 {
 107         return 1;
 108 }
 109
 110 int kvm_arch_hardware_enable(void)
 111 {
 112         return kvm_mips_callbacks->hardware_enable();
 113 }
 114
 115 void kvm_arch_hardware_disable(void)
 116 {
 117         kvm_mips_callbacks->hardware_disable();
 118 }
 119
 120 int kvm_arch_hardware_setup(void *opaque)
 121 {
 122         return 0;
 123 }
 124
 125 int kvm_arch_check_processor_compat(void *opaque)
 126 {
 127         return 0;
 128 }
 129
 130 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 131 {
 132         switch (type) {
 133 #ifdef CONFIG_KVM_MIPS_VZ
 134         case KVM_VM_MIPS_VZ:
 135 #else
 136         case KVM_VM_MIPS_TE:
 137 #endif
 138                 break;
 139         default:
 140                 /* Unsupported KVM type */
 141                 return -EINVAL;
 142         };
 143
 144         /* Allocate page table to map GPA -> RPA */
 145         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 146         if (!kvm->arch.gpa_mm.pgd)
 147                 return -ENOMEM;
 148
 149         return 0;
 150 }
 151
 152 void kvm_mips_free_vcpus(struct kvm *kvm)
 153 {
 154         unsigned int i;
 155         struct kvm_vcpu *vcpu;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 kvm_vcpu_destroy(vcpu);
 159         }
 160
 161         mutex_lock(&kvm->lock);
 162
 163         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 164                 kvm->vcpus[i] = NULL;
 165
 166         atomic_set(&kvm->online_vcpus, 0);
 167
 168         mutex_unlock(&kvm->lock);
 169 }
 170
 171 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 172 {
 173         /* It should always be safe to remove after flushing the whole range */
 174         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 175         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 176 }
 177
 178 void kvm_arch_destroy_vm(struct kvm *kvm)
 179 {
 180         kvm_mips_free_vcpus(kvm);
 181         kvm_mips_free_gpa_pt(kvm);
 182 }
 183
 184 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 185                         unsigned long arg)
 186 {
 187         return -ENOIOCTLCMD;
 188 }
 189
 190 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 191 {
 192         /* Flush whole GPA */
 193         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 194
 195         /* Let implementation do the rest */
 196         kvm_mips_callbacks->flush_shadow_all(kvm);
 197 }
 198
 199 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 200                                    struct kvm_memory_slot *slot)
 201 {
 202         /*
 203          * The slot has been made invalid (ready for moving or deletion), so we
 204          * need to ensure that it can no longer be accessed by any guest VCPUs.
 205          */
 206
 207         spin_lock(&kvm->mmu_lock);
 208         /* Flush slot from GPA */
 209         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 210                               slot->base_gfn + slot->npages - 1);
 211         /* Let implementation do the rest */
 212         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 213         spin_unlock(&kvm->mmu_lock);
 214 }
 215
 216 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 217                                    struct kvm_memory_slot *memslot,
 218                                    const struct kvm_userspace_memory_region *mem,
 219                                    enum kvm_mr_change change)
 220 {
 221         return 0;
 222 }
 223
 224 void kvm_arch_commit_memory_region(struct kvm *kvm,
 225                                    const struct kvm_userspace_memory_region *mem,
 226                                    struct kvm_memory_slot *old,
 227                                    const struct kvm_memory_slot *new,
 228                                    enum kvm_mr_change change)
 229 {
 230         int needs_flush;
 231
 232         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 233                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 234                   mem->memory_size, mem->userspace_addr);
 235
 236         /*
 237          * If dirty page logging is enabled, write protect all pages in the slot
 238          * ready for dirty logging.
 239          *
 240          * There is no need to do this in any of the following cases:
 241          * CREATE:      No dirty mappings will already exist.
 242          * MOVE/DELETE: The old mappings will already have been cleaned up by
 243          *              kvm_arch_flush_shadow_memslot()
 244          */
 245         if (change == KVM_MR_FLAGS_ONLY &&
 246             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 247              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 248                 spin_lock(&kvm->mmu_lock);
 249                 /* Write protect GPA page table entries */
 250                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 251                                         new->base_gfn + new->npages - 1);
 252                 /* Let implementation do the rest */
 253                 if (needs_flush)
 254                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 255                 spin_unlock(&kvm->mmu_lock);
 256         }
 257 }
 258
 259 static inline void dump_handler(const char *symbol, void *start, void *end)
 260 {
 261         u32 *p;
 262
 263         pr_debug("LEAF(%s)\n", symbol);
 264
 265         pr_debug("\t.set push\n");
 266         pr_debug("\t.set noreorder\n");
 267
 268         for (p = start; p < (u32 *)end; ++p)
 269                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 270
 271         pr_debug("\t.set\tpop\n");
 272
 273         pr_debug("\tEND(%s)\n", symbol);
 274 }
 275
 276 /* low level hrtimer wake routine */
 277 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
 278 {
 279         struct kvm_vcpu *vcpu;
 280
 281         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
 282
 283         kvm_mips_callbacks->queue_timer_int(vcpu);
 284
 285         vcpu->arch.wait = 0;
 286         rcuwait_wake_up(&vcpu->wait);
 287
 288         return kvm_mips_count_timeout(vcpu);
 289 }
 290
 291 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 292 {
 293         return 0;
 294 }
 295
 296 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 297 {
 298         int err, size;
 299         void *gebase, *p, *handler, *refill_start, *refill_end;
 300         int i;
 301
 302         kvm_debug("kvm @ %p: create cpu %d at %p\n",
 303                   vcpu->kvm, vcpu->vcpu_id, vcpu);
 304
 305         err = kvm_mips_callbacks->vcpu_init(vcpu);
 306         if (err)
 307                 return err;
 308
 309         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
 310                      HRTIMER_MODE_REL);
 311         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
 312
 313         /*
 314          * Allocate space for host mode exception handlers that handle
 315          * guest mode exits
 316          */
 317         if (cpu_has_veic || cpu_has_vint)
 318                 size = 0x200 + VECTORSPACING * 64;
 319         else
 320                 size = 0x4000;
 321
 322         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 323
 324         if (!gebase) {
 325                 err = -ENOMEM;
 326                 goto out_uninit_vcpu;
 327         }
 328         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 329                   ALIGN(size, PAGE_SIZE), gebase);
 330
 331         /*
 332          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 333          * limits us to the low 512MB of physical address space. If the memory
 334          * we allocate is out of range, just give up now.
 335          */
 336         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 337                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 338                         gebase);
 339                 err = -ENOMEM;
 340                 goto out_free_gebase;
 341         }
 342
 343         /* Save new ebase */
 344         vcpu->arch.guest_ebase = gebase;
 345
 346         /* Build guest exception vectors dynamically in unmapped memory */
 347         handler = gebase + 0x2000;
 348
 349         /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
 350         refill_start = gebase;
 351         if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
 352                 refill_start += 0x080;
 353         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 354
 355         /* General Exception Entry point */
 356         kvm_mips_build_exception(gebase + 0x180, handler);
 357
 358         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 359         for (i = 0; i < 8; i++) {
 360                 kvm_debug("L1 Vectored handler @ %p\n",
 361                           gebase + 0x200 + (i * VECTORSPACING));
 362                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 363                                          handler);
 364         }
 365
 366         /* General exit handler */
 367         p = handler;
 368         p = kvm_mips_build_exit(p);
 369
 370         /* Guest entry routine */
 371         vcpu->arch.vcpu_run = p;
 372         p = kvm_mips_build_vcpu_run(p);
 373
 374         /* Dump the generated code */
 375         pr_debug("#include <asm/asm.h>\n");
 376         pr_debug("#include <asm/regdef.h>\n");
 377         pr_debug("\n");
 378         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 379         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 380         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 381         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 382
 383         /* Invalidate the icache for these ranges */
 384         flush_icache_range((unsigned long)gebase,
 385                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 386
 387         /*
 388          * Allocate comm page for guest kernel, a TLB will be reserved for
 389          * mapping GVA @ 0xFFFF8000 to this page
 390          */
 391         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 392
 393         if (!vcpu->arch.kseg0_commpage) {
 394                 err = -ENOMEM;
 395                 goto out_free_gebase;
 396         }
 397
 398         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 399         kvm_mips_commpage_init(vcpu);
 400
 401         /* Init */
 402         vcpu->arch.last_sched_cpu = -1;
 403         vcpu->arch.last_exec_cpu = -1;
 404
 405         /* Initial guest state */
 406         err = kvm_mips_callbacks->vcpu_setup(vcpu);
 407         if (err)
 408                 goto out_free_commpage;
 409
 410         return 0;
 411
 412 out_free_commpage:
 413         kfree(vcpu->arch.kseg0_commpage);
 414 out_free_gebase:
 415         kfree(gebase);
 416 out_uninit_vcpu:
 417         kvm_mips_callbacks->vcpu_uninit(vcpu);
 418         return err;
 419 }
 420
 421 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 422 {
 423         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 424
 425         kvm_mips_dump_stats(vcpu);
 426
 427         kvm_mmu_free_memory_caches(vcpu);
 428         kfree(vcpu->arch.guest_ebase);
 429         kfree(vcpu->arch.kseg0_commpage);
 430
 431         kvm_mips_callbacks->vcpu_uninit(vcpu);
 432 }
 433
 434 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 435                                         struct kvm_guest_debug *dbg)
 436 {
 437         return -ENOIOCTLCMD;
 438 }
 439
 440 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
 441 {
 442         struct kvm_run *run = vcpu->run;
 443         int r = -EINTR;
 444
 445         vcpu_load(vcpu);
 446
 447         kvm_sigset_activate(vcpu);
 448
 449         if (vcpu->mmio_needed) {
 450                 if (!vcpu->mmio_is_write)
 451                         kvm_mips_complete_mmio_load(vcpu, run);
 452                 vcpu->mmio_needed = 0;
 453         }
 454
 455         if (run->immediate_exit)
 456                 goto out;
 457
 458         lose_fpu(1);
 459
 460         local_irq_disable();
 461         guest_enter_irqoff();
 462         trace_kvm_enter(vcpu);
 463
 464         /*
 465          * Make sure the read of VCPU requests in vcpu_run() callback is not
 466          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 467          * flush request while the requester sees the VCPU as outside of guest
 468          * mode and not needing an IPI.
 469          */
 470         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 471
 472         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 473
 474         trace_kvm_out(vcpu);
 475         guest_exit_irqoff();
 476         local_irq_enable();
 477
 478 out:
 479         kvm_sigset_deactivate(vcpu);
 480
 481         vcpu_put(vcpu);
 482         return r;
 483 }
 484
 485 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 486                              struct kvm_mips_interrupt *irq)
 487 {
 488         int intr = (int)irq->irq;
 489         struct kvm_vcpu *dvcpu = NULL;
 490
 491         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 492                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 493                           (int)intr);
 494
 495         if (irq->cpu == -1)
 496                 dvcpu = vcpu;
 497         else
 498                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 499
 500         if (intr == 2 || intr == 3 || intr == 4) {
 501                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 502
 503         } else if (intr == -2 || intr == -3 || intr == -4) {
 504                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 505         } else {
 506                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 507                         irq->cpu, irq->irq);
 508                 return -EINVAL;
 509         }
 510
 511         dvcpu->arch.wait = 0;
 512
 513         rcuwait_wake_up(&dvcpu->wait);
 514
 515         return 0;
 516 }
 517
 518 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 519                                     struct kvm_mp_state *mp_state)
 520 {
 521         return -ENOIOCTLCMD;
 522 }
 523
 524 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 525                                     struct kvm_mp_state *mp_state)
 526 {
 527         return -ENOIOCTLCMD;
 528 }
 529
 530 static u64 kvm_mips_get_one_regs[] = {
 531         KVM_REG_MIPS_R0,
 532         KVM_REG_MIPS_R1,
 533         KVM_REG_MIPS_R2,
 534         KVM_REG_MIPS_R3,
 535         KVM_REG_MIPS_R4,
 536         KVM_REG_MIPS_R5,
 537         KVM_REG_MIPS_R6,
 538         KVM_REG_MIPS_R7,
 539         KVM_REG_MIPS_R8,
 540         KVM_REG_MIPS_R9,
 541         KVM_REG_MIPS_R10,
 542         KVM_REG_MIPS_R11,
 543         KVM_REG_MIPS_R12,
 544         KVM_REG_MIPS_R13,
 545         KVM_REG_MIPS_R14,
 546         KVM_REG_MIPS_R15,
 547         KVM_REG_MIPS_R16,
 548         KVM_REG_MIPS_R17,
 549         KVM_REG_MIPS_R18,
 550         KVM_REG_MIPS_R19,
 551         KVM_REG_MIPS_R20,
 552         KVM_REG_MIPS_R21,
 553         KVM_REG_MIPS_R22,
 554         KVM_REG_MIPS_R23,
 555         KVM_REG_MIPS_R24,
 556         KVM_REG_MIPS_R25,
 557         KVM_REG_MIPS_R26,
 558         KVM_REG_MIPS_R27,
 559         KVM_REG_MIPS_R28,
 560         KVM_REG_MIPS_R29,
 561         KVM_REG_MIPS_R30,
 562         KVM_REG_MIPS_R31,
 563
 564 #ifndef CONFIG_CPU_MIPSR6
 565         KVM_REG_MIPS_HI,
 566         KVM_REG_MIPS_LO,
 567 #endif
 568         KVM_REG_MIPS_PC,
 569 };
 570
 571 static u64 kvm_mips_get_one_regs_fpu[] = {
 572         KVM_REG_MIPS_FCR_IR,
 573         KVM_REG_MIPS_FCR_CSR,
 574 };
 575
 576 static u64 kvm_mips_get_one_regs_msa[] = {
 577         KVM_REG_MIPS_MSA_IR,
 578         KVM_REG_MIPS_MSA_CSR,
 579 };
 580
 581 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 582 {
 583         unsigned long ret;
 584
 585         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 586         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 587                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 588                 /* odd doubles */
 589                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 590                         ret += 16;
 591         }
 592         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 593                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 594         ret += kvm_mips_callbacks->num_regs(vcpu);
 595
 596         return ret;
 597 }
 598
 599 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 600 {
 601         u64 index;
 602         unsigned int i;
 603
 604         if (copy_to_user(indices, kvm_mips_get_one_regs,
 605                          sizeof(kvm_mips_get_one_regs)))
 606                 return -EFAULT;
 607         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 608
 609         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 610                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 611                                  sizeof(kvm_mips_get_one_regs_fpu)))
 612                         return -EFAULT;
 613                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 614
 615                 for (i = 0; i < 32; ++i) {
 616                         index = KVM_REG_MIPS_FPR_32(i);
 617                         if (copy_to_user(indices, &index, sizeof(index)))
 618                                 return -EFAULT;
 619                         ++indices;
 620
 621                         /* skip odd doubles if no F64 */
 622                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 623                                 continue;
 624
 625                         index = KVM_REG_MIPS_FPR_64(i);
 626                         if (copy_to_user(indices, &index, sizeof(index)))
 627                                 return -EFAULT;
 628                         ++indices;
 629                 }
 630         }
 631
 632         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 633                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 634                                  sizeof(kvm_mips_get_one_regs_msa)))
 635                         return -EFAULT;
 636                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 637
 638                 for (i = 0; i < 32; ++i) {
 639                         index = KVM_REG_MIPS_VEC_128(i);
 640                         if (copy_to_user(indices, &index, sizeof(index)))
 641                                 return -EFAULT;
 642                         ++indices;
 643                 }
 644         }
 645
 646         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 647 }
 648
 649 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 650                             const struct kvm_one_reg *reg)
 651 {
 652         struct mips_coproc *cop0 = vcpu->arch.cop0;
 653         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 654         int ret;
 655         s64 v;
 656         s64 vs[2];
 657         unsigned int idx;
 658
 659         switch (reg->id) {
 660         /* General purpose registers */
 661         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 662                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 663                 break;
 664 #ifndef CONFIG_CPU_MIPSR6
 665         case KVM_REG_MIPS_HI:
 666                 v = (long)vcpu->arch.hi;
 667                 break;
 668         case KVM_REG_MIPS_LO:
 669                 v = (long)vcpu->arch.lo;
 670                 break;
 671 #endif
 672         case KVM_REG_MIPS_PC:
 673                 v = (long)vcpu->arch.pc;
 674                 break;
 675
 676         /* Floating point registers */
 677         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 678                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 679                         return -EINVAL;
 680                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 681                 /* Odd singles in top of even double when FR=0 */
 682                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 683                         v = get_fpr32(&fpu->fpr[idx], 0);
 684                 else
 685                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 686                 break;
 687         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 688                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 689                         return -EINVAL;
 690                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 691                 /* Can't access odd doubles in FR=0 mode */
 692                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 693                         return -EINVAL;
 694                 v = get_fpr64(&fpu->fpr[idx], 0);
 695                 break;
 696         case KVM_REG_MIPS_FCR_IR:
 697                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 698                         return -EINVAL;
 699                 v = boot_cpu_data.fpu_id;
 700                 break;
 701         case KVM_REG_MIPS_FCR_CSR:
 702                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 703                         return -EINVAL;
 704                 v = fpu->fcr31;
 705                 break;
 706
 707         /* MIPS SIMD Architecture (MSA) registers */
 708         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 709                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 710                         return -EINVAL;
 711                 /* Can't access MSA registers in FR=0 mode */
 712                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 713                         return -EINVAL;
 714                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 715 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 716                 /* least significant byte first */
 717                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 718                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 719 #else
 720                 /* most significant byte first */
 721                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 722                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 723 #endif
 724                 break;
 725         case KVM_REG_MIPS_MSA_IR:
 726                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 727                         return -EINVAL;
 728                 v = boot_cpu_data.msa_id;
 729                 break;
 730         case KVM_REG_MIPS_MSA_CSR:
 731                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 732                         return -EINVAL;
 733                 v = fpu->msacsr;
 734                 break;
 735
 736         /* registers to be handled specially */
 737         default:
 738                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 739                 if (ret)
 740                         return ret;
 741                 break;
 742         }
 743         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 744                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 745
 746                 return put_user(v, uaddr64);
 747         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 748                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 749                 u32 v32 = (u32)v;
 750
 751                 return put_user(v32, uaddr32);
 752         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 753                 void __user *uaddr = (void __user *)(long)reg->addr;
 754
 755                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 756         } else {
 757                 return -EINVAL;
 758         }
 759 }
 760
 761 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 762                             const struct kvm_one_reg *reg)
 763 {
 764         struct mips_coproc *cop0 = vcpu->arch.cop0;
 765         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 766         s64 v;
 767         s64 vs[2];
 768         unsigned int idx;
 769
 770         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 771                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 772
 773                 if (get_user(v, uaddr64) != 0)
 774                         return -EFAULT;
 775         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 776                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 777                 s32 v32;
 778
 779                 if (get_user(v32, uaddr32) != 0)
 780                         return -EFAULT;
 781                 v = (s64)v32;
 782         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 783                 void __user *uaddr = (void __user *)(long)reg->addr;
 784
 785                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 786         } else {
 787                 return -EINVAL;
 788         }
 789
 790         switch (reg->id) {
 791         /* General purpose registers */
 792         case KVM_REG_MIPS_R0:
 793                 /* Silently ignore requests to set $0 */
 794                 break;
 795         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 796                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 797                 break;
 798 #ifndef CONFIG_CPU_MIPSR6
 799         case KVM_REG_MIPS_HI:
 800                 vcpu->arch.hi = v;
 801                 break;
 802         case KVM_REG_MIPS_LO:
 803                 vcpu->arch.lo = v;
 804                 break;
 805 #endif
 806         case KVM_REG_MIPS_PC:
 807                 vcpu->arch.pc = v;
 808                 break;
 809
 810         /* Floating point registers */
 811         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 812                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 813                         return -EINVAL;
 814                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 815                 /* Odd singles in top of even double when FR=0 */
 816                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 817                         set_fpr32(&fpu->fpr[idx], 0, v);
 818                 else
 819                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 820                 break;
 821         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 822                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 823                         return -EINVAL;
 824                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 825                 /* Can't access odd doubles in FR=0 mode */
 826                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 827                         return -EINVAL;
 828                 set_fpr64(&fpu->fpr[idx], 0, v);
 829                 break;
 830         case KVM_REG_MIPS_FCR_IR:
 831                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 832                         return -EINVAL;
 833                 /* Read-only */
 834                 break;
 835         case KVM_REG_MIPS_FCR_CSR:
 836                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 837                         return -EINVAL;
 838                 fpu->fcr31 = v;
 839                 break;
 840
 841         /* MIPS SIMD Architecture (MSA) registers */
 842         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 843                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 844                         return -EINVAL;
 845                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 846 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 847                 /* least significant byte first */
 848                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 849                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 850 #else
 851                 /* most significant byte first */
 852                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 853                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 854 #endif
 855                 break;
 856         case KVM_REG_MIPS_MSA_IR:
 857                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 858                         return -EINVAL;
 859                 /* Read-only */
 860                 break;
 861         case KVM_REG_MIPS_MSA_CSR:
 862                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 863                         return -EINVAL;
 864                 fpu->msacsr = v;
 865                 break;
 866
 867         /* registers to be handled specially */
 868         default:
 869                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
 870         }
 871         return 0;
 872 }
 873
 874 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
 875                                      struct kvm_enable_cap *cap)
 876 {
 877         int r = 0;
 878
 879         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
 880                 return -EINVAL;
 881         if (cap->flags)
 882                 return -EINVAL;
 883         if (cap->args[0])
 884                 return -EINVAL;
 885
 886         switch (cap->cap) {
 887         case KVM_CAP_MIPS_FPU:
 888                 vcpu->arch.fpu_enabled = true;
 889                 break;
 890         case KVM_CAP_MIPS_MSA:
 891                 vcpu->arch.msa_enabled = true;
 892                 break;
 893         default:
 894                 r = -EINVAL;
 895                 break;
 896         }
 897
 898         return r;
 899 }
 900
 901 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
 902                                unsigned long arg)
 903 {
 904         struct kvm_vcpu *vcpu = filp->private_data;
 905         void __user *argp = (void __user *)arg;
 906
 907         if (ioctl == KVM_INTERRUPT) {
 908                 struct kvm_mips_interrupt irq;
 909
 910                 if (copy_from_user(&irq, argp, sizeof(irq)))
 911                         return -EFAULT;
 912                 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
 913                           irq.irq);
 914
 915                 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
 916         }
 917
 918         return -ENOIOCTLCMD;
 919 }
 920
 921 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
 922                          unsigned long arg)
 923 {
 924         struct kvm_vcpu *vcpu = filp->private_data;
 925         void __user *argp = (void __user *)arg;
 926         long r;
 927
 928         vcpu_load(vcpu);
 929
 930         switch (ioctl) {
 931         case KVM_SET_ONE_REG:
 932         case KVM_GET_ONE_REG: {
 933                 struct kvm_one_reg reg;
 934
 935                 r = -EFAULT;
 936                 if (copy_from_user(&reg, argp, sizeof(reg)))
 937                         break;
 938                 if (ioctl == KVM_SET_ONE_REG)
 939                         r = kvm_mips_set_reg(vcpu, &reg);
 940                 else
 941                         r = kvm_mips_get_reg(vcpu, &reg);
 942                 break;
 943         }
 944         case KVM_GET_REG_LIST: {
 945                 struct kvm_reg_list __user *user_list = argp;
 946                 struct kvm_reg_list reg_list;
 947                 unsigned n;
 948
 949                 r = -EFAULT;
 950                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
 951                         break;
 952                 n = reg_list.n;
 953                 reg_list.n = kvm_mips_num_regs(vcpu);
 954                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
 955                         break;
 956                 r = -E2BIG;
 957                 if (n < reg_list.n)
 958                         break;
 959                 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
 960                 break;
 961         }
 962         case KVM_ENABLE_CAP: {
 963                 struct kvm_enable_cap cap;
 964
 965                 r = -EFAULT;
 966                 if (copy_from_user(&cap, argp, sizeof(cap)))
 967                         break;
 968                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
 969                 break;
 970         }
 971         default:
 972                 r = -ENOIOCTLCMD;
 973         }
 974
 975         vcpu_put(vcpu);
 976         return r;
 977 }
 978
 979 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
 980 {
 981
 982 }
 983
 984 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
 985                                         struct kvm_memory_slot *memslot)
 986 {
 987         /* Let implementation handle TLB/GVA invalidation */
 988         kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
 989 }
 990
 991 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
 992 {
 993         long r;
 994
 995         switch (ioctl) {
 996         default:
 997                 r = -ENOIOCTLCMD;
 998         }
 999
1000         return r;
1001 }
1002
1003 int kvm_arch_init(void *opaque)
1004 {
1005         if (kvm_mips_callbacks) {
1006                 kvm_err("kvm: module already exists\n");
1007                 return -EEXIST;
1008         }
1009
1010         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1011 }
1012
1013 void kvm_arch_exit(void)
1014 {
1015         kvm_mips_callbacks = NULL;
1016 }
1017
1018 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1019                                   struct kvm_sregs *sregs)
1020 {
1021         return -ENOIOCTLCMD;
1022 }
1023
1024 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1025                                   struct kvm_sregs *sregs)
1026 {
1027         return -ENOIOCTLCMD;
1028 }
1029
1030 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1031 {
1032 }
1033
1034 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1035 {
1036         return -ENOIOCTLCMD;
1037 }
1038
1039 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1040 {
1041         return -ENOIOCTLCMD;
1042 }
1043
1044 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1045 {
1046         return VM_FAULT_SIGBUS;
1047 }
1048
1049 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1050 {
1051         int r;
1052
1053         switch (ext) {
1054         case KVM_CAP_ONE_REG:
1055         case KVM_CAP_ENABLE_CAP:
1056         case KVM_CAP_READONLY_MEM:
1057         case KVM_CAP_SYNC_MMU:
1058         case KVM_CAP_IMMEDIATE_EXIT:
1059                 r = 1;
1060                 break;
1061         case KVM_CAP_NR_VCPUS:
1062                 r = num_online_cpus();
1063                 break;
1064         case KVM_CAP_MAX_VCPUS:
1065                 r = KVM_MAX_VCPUS;
1066                 break;
1067         case KVM_CAP_MAX_VCPU_ID:
1068                 r = KVM_MAX_VCPU_ID;
1069                 break;
1070         case KVM_CAP_MIPS_FPU:
1071                 /* We don't handle systems with inconsistent cpu_has_fpu */
1072                 r = !!raw_cpu_has_fpu;
1073                 break;
1074         case KVM_CAP_MIPS_MSA:
1075                 /*
1076                  * We don't support MSA vector partitioning yet:
1077                  * 1) It would require explicit support which can't be tested
1078                  *    yet due to lack of support in current hardware.
1079                  * 2) It extends the state that would need to be saved/restored
1080                  *    by e.g. QEMU for migration.
1081                  *
1082                  * When vector partitioning hardware becomes available, support
1083                  * could be added by requiring a flag when enabling
1084                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1085                  * to save/restore the appropriate extra state.
1086                  */
1087                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1088                 break;
1089         default:
1090                 r = kvm_mips_callbacks->check_extension(kvm, ext);
1091                 break;
1092         }
1093         return r;
1094 }
1095
1096 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1097 {
1098         return kvm_mips_pending_timer(vcpu) ||
1099                 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1100 }
1101
1102 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1103 {
1104         int i;
1105         struct mips_coproc *cop0;
1106
1107         if (!vcpu)
1108                 return -1;
1109
1110         kvm_debug("VCPU Register Dump:\n");
1111         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1112         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1113
1114         for (i = 0; i < 32; i += 4) {
1115                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1116                        vcpu->arch.gprs[i],
1117                        vcpu->arch.gprs[i + 1],
1118                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1119         }
1120         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1121         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1122
1123         cop0 = vcpu->arch.cop0;
1124         kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1125                   kvm_read_c0_guest_status(cop0),
1126                   kvm_read_c0_guest_cause(cop0));
1127
1128         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1129
1130         return 0;
1131 }
1132
1133 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1134 {
1135         int i;
1136
1137         vcpu_load(vcpu);
1138
1139         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1140                 vcpu->arch.gprs[i] = regs->gpr[i];
1141         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1142         vcpu->arch.hi = regs->hi;
1143         vcpu->arch.lo = regs->lo;
1144         vcpu->arch.pc = regs->pc;
1145
1146         vcpu_put(vcpu);
1147         return 0;
1148 }
1149
1150 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1151 {
1152         int i;
1153
1154         vcpu_load(vcpu);
1155
1156         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1157                 regs->gpr[i] = vcpu->arch.gprs[i];
1158
1159         regs->hi = vcpu->arch.hi;
1160         regs->lo = vcpu->arch.lo;
1161         regs->pc = vcpu->arch.pc;
1162
1163         vcpu_put(vcpu);
1164         return 0;
1165 }
1166
1167 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1168                                   struct kvm_translation *tr)
1169 {
1170         return 0;
1171 }
1172
1173 static void kvm_mips_set_c0_status(void)
1174 {
1175         u32 status = read_c0_status();
1176
1177         if (cpu_has_dsp)
1178                 status |= (ST0_MX);
1179
1180         write_c0_status(status);
1181         ehb();
1182 }
1183
1184 /*
1185  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1186  */
1187 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1188 {
1189         u32 cause = vcpu->arch.host_cp0_cause;
1190         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1191         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1192         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1193         enum emulation_result er = EMULATE_DONE;
1194         u32 inst;
1195         int ret = RESUME_GUEST;
1196
1197         vcpu->mode = OUTSIDE_GUEST_MODE;
1198
1199         /* re-enable HTW before enabling interrupts */
1200         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1201                 htw_start();
1202
1203         /* Set a default exit reason */
1204         run->exit_reason = KVM_EXIT_UNKNOWN;
1205         run->ready_for_interrupt_injection = 1;
1206
1207         /*
1208          * Set the appropriate status bits based on host CPU features,
1209          * before we hit the scheduler
1210          */
1211         kvm_mips_set_c0_status();
1212
1213         local_irq_enable();
1214
1215         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1216                         cause, opc, run, vcpu);
1217         trace_kvm_exit(vcpu, exccode);
1218
1219         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1220                 /*
1221                  * Do a privilege check, if in UM most of these exit conditions
1222                  * end up causing an exception to be delivered to the Guest
1223                  * Kernel
1224                  */
1225                 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1226                 if (er == EMULATE_PRIV_FAIL) {
1227                         goto skip_emul;
1228                 } else if (er == EMULATE_FAIL) {
1229                         run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1230                         ret = RESUME_HOST;
1231                         goto skip_emul;
1232                 }
1233         }
1234
1235         switch (exccode) {
1236         case EXCCODE_INT:
1237                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1238
1239                 ++vcpu->stat.int_exits;
1240
1241                 if (need_resched())
1242                         cond_resched();
1243
1244                 ret = RESUME_GUEST;
1245                 break;
1246
1247         case EXCCODE_CPU:
1248                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1249
1250                 ++vcpu->stat.cop_unusable_exits;
1251                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1252                 /* XXXKYMA: Might need to return to user space */
1253                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1254                         ret = RESUME_HOST;
1255                 break;
1256
1257         case EXCCODE_MOD:
1258                 ++vcpu->stat.tlbmod_exits;
1259                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1260                 break;
1261
1262         case EXCCODE_TLBS:
1263                 kvm_debug("TLB ST fault:  cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1264                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1265                           badvaddr);
1266
1267                 ++vcpu->stat.tlbmiss_st_exits;
1268                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1269                 break;
1270
1271         case EXCCODE_TLBL:
1272                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1273                           cause, opc, badvaddr);
1274
1275                 ++vcpu->stat.tlbmiss_ld_exits;
1276                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1277                 break;
1278
1279         case EXCCODE_ADES:
1280                 ++vcpu->stat.addrerr_st_exits;
1281                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1282                 break;
1283
1284         case EXCCODE_ADEL:
1285                 ++vcpu->stat.addrerr_ld_exits;
1286                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1287                 break;
1288
1289         case EXCCODE_SYS:
1290                 ++vcpu->stat.syscall_exits;
1291                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1292                 break;
1293
1294         case EXCCODE_RI:
1295                 ++vcpu->stat.resvd_inst_exits;
1296                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1297                 break;
1298
1299         case EXCCODE_BP:
1300                 ++vcpu->stat.break_inst_exits;
1301                 ret = kvm_mips_callbacks->handle_break(vcpu);
1302                 break;
1303
1304         case EXCCODE_TR:
1305                 ++vcpu->stat.trap_inst_exits;
1306                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1307                 break;
1308
1309         case EXCCODE_MSAFPE:
1310                 ++vcpu->stat.msa_fpe_exits;
1311                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1312                 break;
1313
1314         case EXCCODE_FPE:
1315                 ++vcpu->stat.fpe_exits;
1316                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1317                 break;
1318
1319         case EXCCODE_MSADIS:
1320                 ++vcpu->stat.msa_disabled_exits;
1321                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1322                 break;
1323
1324         case EXCCODE_GE:
1325                 /* defer exit accounting to handler */
1326                 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1327                 break;
1328
1329         default:
1330                 if (cause & CAUSEF_BD)
1331                         opc += 1;
1332                 inst = 0;
1333                 kvm_get_badinstr(opc, vcpu, &inst);
1334                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#x\n",
1335                         exccode, opc, inst, badvaddr,
1336                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1337                 kvm_arch_vcpu_dump_regs(vcpu);
1338                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1339                 ret = RESUME_HOST;
1340                 break;
1341
1342         }
1343
1344 skip_emul:
1345         local_irq_disable();
1346
1347         if (ret == RESUME_GUEST)
1348                 kvm_vz_acquire_htimer(vcpu);
1349
1350         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1351                 kvm_mips_deliver_interrupts(vcpu, cause);
1352
1353         if (!(ret & RESUME_HOST)) {
1354                 /* Only check for signals if not already exiting to userspace */
1355                 if (signal_pending(current)) {
1356                         run->exit_reason = KVM_EXIT_INTR;
1357                         ret = (-EINTR << 2) | RESUME_HOST;
1358                         ++vcpu->stat.signal_exits;
1359                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1360                 }
1361         }
1362
1363         if (ret == RESUME_GUEST) {
1364                 trace_kvm_reenter(vcpu);
1365
1366                 /*
1367                  * Make sure the read of VCPU requests in vcpu_reenter()
1368                  * callback is not reordered ahead of the write to vcpu->mode,
1369                  * or we could miss a TLB flush request while the requester sees
1370                  * the VCPU as outside of guest mode and not needing an IPI.
1371                  */
1372                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1373
1374                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1375
1376                 /*
1377                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1378                  * is live), restore FCR31 / MSACSR.
1379                  *
1380                  * This should be before returning to the guest exception
1381                  * vector, as it may well cause an [MSA] FP exception if there
1382                  * are pending exception bits unmasked. (see
1383                  * kvm_mips_csr_die_notifier() for how that is handled).
1384                  */
1385                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1386                     read_c0_status() & ST0_CU1)
1387                         __kvm_restore_fcsr(&vcpu->arch);
1388
1389                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1390                     read_c0_config5() & MIPS_CONF5_MSAEN)
1391                         __kvm_restore_msacsr(&vcpu->arch);
1392         }
1393
1394         /* Disable HTW before returning to guest or host */
1395         if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1396                 htw_stop();
1397
1398         return ret;
1399 }
1400
1401 /* Enable FPU for guest and restore context */
1402 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1403 {
1404         struct mips_coproc *cop0 = vcpu->arch.cop0;
1405         unsigned int sr, cfg5;
1406
1407         preempt_disable();
1408
1409         sr = kvm_read_c0_guest_status(cop0);
1410
1411         /*
1412          * If MSA state is already live, it is undefined how it interacts with
1413          * FR=0 FPU state, and we don't want to hit reserved instruction
1414          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1415          * play it safe and save it first.
1416          *
1417          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1418          * get called when guest CU1 is set, however we can't trust the guest
1419          * not to clobber the status register directly via the commpage.
1420          */
1421         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1422             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1423                 kvm_lose_fpu(vcpu);
1424
1425         /*
1426          * Enable FPU for guest
1427          * We set FR and FRE according to guest context
1428          */
1429         change_c0_status(ST0_CU1 | ST0_FR, sr);
1430         if (cpu_has_fre) {
1431                 cfg5 = kvm_read_c0_guest_config5(cop0);
1432                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1433         }
1434         enable_fpu_hazard();
1435
1436         /* If guest FPU state not active, restore it now */
1437         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1438                 __kvm_restore_fpu(&vcpu->arch);
1439                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1440                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1441         } else {
1442                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1443         }
1444
1445         preempt_enable();
1446 }
1447
1448 #ifdef CONFIG_CPU_HAS_MSA
1449 /* Enable MSA for guest and restore context */
1450 void kvm_own_msa(struct kvm_vcpu *vcpu)
1451 {
1452         struct mips_coproc *cop0 = vcpu->arch.cop0;
1453         unsigned int sr, cfg5;
1454
1455         preempt_disable();
1456
1457         /*
1458          * Enable FPU if enabled in guest, since we're restoring FPU context
1459          * anyway. We set FR and FRE according to guest context.
1460          */
1461         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1462                 sr = kvm_read_c0_guest_status(cop0);
1463
1464                 /*
1465                  * If FR=0 FPU state is already live, it is undefined how it
1466                  * interacts with MSA state, so play it safe and save it first.
1467                  */
1468                 if (!(sr & ST0_FR) &&
1469                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1470                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1471                         kvm_lose_fpu(vcpu);
1472
1473                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1474                 if (sr & ST0_CU1 && cpu_has_fre) {
1475                         cfg5 = kvm_read_c0_guest_config5(cop0);
1476                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1477                 }
1478         }
1479
1480         /* Enable MSA for guest */
1481         set_c0_config5(MIPS_CONF5_MSAEN);
1482         enable_fpu_hazard();
1483
1484         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1485         case KVM_MIPS_AUX_FPU:
1486                 /*
1487                  * Guest FPU state already loaded, only restore upper MSA state
1488                  */
1489                 __kvm_restore_msa_upper(&vcpu->arch);
1490                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1491                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1492                 break;
1493         case 0:
1494                 /* Neither FPU or MSA already active, restore full MSA state */
1495                 __kvm_restore_msa(&vcpu->arch);
1496                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1497                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1498                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1499                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1500                               KVM_TRACE_AUX_FPU_MSA);
1501                 break;
1502         default:
1503                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1504                 break;
1505         }
1506
1507         preempt_enable();
1508 }
1509 #endif
1510
1511 /* Drop FPU & MSA without saving it */
1512 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1513 {
1514         preempt_disable();
1515         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1516                 disable_msa();
1517                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1518                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1519         }
1520         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1521                 clear_c0_status(ST0_CU1 | ST0_FR);
1522                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1523                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1524         }
1525         preempt_enable();
1526 }
1527
1528 /* Save and disable FPU & MSA */
1529 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1530 {
1531         /*
1532          * With T&E, FPU & MSA get disabled in root context (hardware) when it
1533          * is disabled in guest context (software), but the register state in
1534          * the hardware may still be in use.
1535          * This is why we explicitly re-enable the hardware before saving.
1536          */
1537
1538         preempt_disable();
1539         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1540                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1541                         set_c0_config5(MIPS_CONF5_MSAEN);
1542                         enable_fpu_hazard();
1543                 }
1544
1545                 __kvm_save_msa(&vcpu->arch);
1546                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1547
1548                 /* Disable MSA & FPU */
1549                 disable_msa();
1550                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1551                         clear_c0_status(ST0_CU1 | ST0_FR);
1552                         disable_fpu_hazard();
1553                 }
1554                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1555         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1556                 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1557                         set_c0_status(ST0_CU1);
1558                         enable_fpu_hazard();
1559                 }
1560
1561                 __kvm_save_fpu(&vcpu->arch);
1562                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1563                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1564
1565                 /* Disable FPU */
1566                 clear_c0_status(ST0_CU1 | ST0_FR);
1567                 disable_fpu_hazard();
1568         }
1569         preempt_enable();
1570 }
1571
1572 /*
1573  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1574  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1575  * exception if cause bits are set in the value being written.
1576  */
1577 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1578                                    unsigned long cmd, void *ptr)
1579 {
1580         struct die_args *args = (struct die_args *)ptr;
1581         struct pt_regs *regs = args->regs;
1582         unsigned long pc;
1583
1584         /* Only interested in FPE and MSAFPE */
1585         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1586                 return NOTIFY_DONE;
1587
1588         /* Return immediately if guest context isn't active */
1589         if (!(current->flags & PF_VCPU))
1590                 return NOTIFY_DONE;
1591
1592         /* Should never get here from user mode */
1593         BUG_ON(user_mode(regs));
1594
1595         pc = instruction_pointer(regs);
1596         switch (cmd) {
1597         case DIE_FP:
1598                 /* match 2nd instruction in __kvm_restore_fcsr */
1599                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1600                         return NOTIFY_DONE;
1601                 break;
1602         case DIE_MSAFP:
1603                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1604                 if (!cpu_has_msa ||
1605                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1606                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1607                         return NOTIFY_DONE;
1608                 break;
1609         }
1610
1611         /* Move PC forward a little and continue executing */
1612         instruction_pointer(regs) += 4;
1613
1614         return NOTIFY_STOP;
1615 }
1616
1617 static struct notifier_block kvm_mips_csr_die_notifier = {
1618         .notifier_call = kvm_mips_csr_die_notify,
1619 };
1620
1621 static int __init kvm_mips_init(void)
1622 {
1623         int ret;
1624
1625         if (cpu_has_mmid) {
1626                 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1627                 return -EOPNOTSUPP;
1628         }
1629
1630         ret = kvm_mips_entry_setup();
1631         if (ret)
1632                 return ret;
1633
1634         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1635
1636         if (ret)
1637                 return ret;
1638
1639         register_die_notifier(&kvm_mips_csr_die_notifier);
1640
1641         return 0;
1642 }
1643
1644 static void __exit kvm_mips_exit(void)
1645 {
1646         kvm_exit();
1647
1648         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1649 }
1650
1651 module_init(kvm_mips_init);
1652 module_exit(kvm_mips_exit);
1653
1654 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);