2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/memblock.h>
22 #include <linux/pgtable.h>
26 #include <asm/cacheflush.h>
27 #include <asm/mmu_context.h>
28 #include <asm/pgalloc.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 struct kvm_stats_debugfs_item debugfs_entries[] = {
43 VCPU_STAT("wait", wait_exits),
44 VCPU_STAT("cache", cache_exits),
45 VCPU_STAT("signal", signal_exits),
46 VCPU_STAT("interrupt", int_exits),
47 VCPU_STAT("cop_unusable", cop_unusable_exits),
48 VCPU_STAT("tlbmod", tlbmod_exits),
49 VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits),
50 VCPU_STAT("tlbmiss_st", tlbmiss_st_exits),
51 VCPU_STAT("addrerr_st", addrerr_st_exits),
52 VCPU_STAT("addrerr_ld", addrerr_ld_exits),
53 VCPU_STAT("syscall", syscall_exits),
54 VCPU_STAT("resvd_inst", resvd_inst_exits),
55 VCPU_STAT("break_inst", break_inst_exits),
56 VCPU_STAT("trap_inst", trap_inst_exits),
57 VCPU_STAT("msa_fpe", msa_fpe_exits),
58 VCPU_STAT("fpe", fpe_exits),
59 VCPU_STAT("msa_disabled", msa_disabled_exits),
60 VCPU_STAT("flush_dcache", flush_dcache_exits),
61 #ifdef CONFIG_KVM_MIPS_VZ
62 VCPU_STAT("vz_gpsi", vz_gpsi_exits),
63 VCPU_STAT("vz_gsfc", vz_gsfc_exits),
64 VCPU_STAT("vz_hc", vz_hc_exits),
65 VCPU_STAT("vz_grr", vz_grr_exits),
66 VCPU_STAT("vz_gva", vz_gva_exits),
67 VCPU_STAT("vz_ghfc", vz_ghfc_exits),
68 VCPU_STAT("vz_gpa", vz_gpa_exits),
69 VCPU_STAT("vz_resvd", vz_resvd_exits),
70 #ifdef CONFIG_CPU_LOONGSON64
71 VCPU_STAT("vz_cpucfg", vz_cpucfg_exits),
74 VCPU_STAT("halt_successful_poll", halt_successful_poll),
75 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
76 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
77 VCPU_STAT("halt_wakeup", halt_wakeup),
78 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
79 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
83 bool kvm_trace_guest_mode_change;
85 int kvm_guest_mode_change_trace_reg(void)
87 kvm_trace_guest_mode_change = true;
91 void kvm_guest_mode_change_trace_unreg(void)
93 kvm_trace_guest_mode_change = false;
97 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
98 * Config7, so we are "runnable" if interrupts are pending
100 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
102 return !!(vcpu->arch.pending_exceptions);
105 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
110 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
115 int kvm_arch_hardware_enable(void)
117 return kvm_mips_callbacks->hardware_enable();
120 void kvm_arch_hardware_disable(void)
122 kvm_mips_callbacks->hardware_disable();
125 int kvm_arch_hardware_setup(void *opaque)
130 int kvm_arch_check_processor_compat(void *opaque)
135 extern void kvm_init_loongson_ipi(struct kvm *kvm);
137 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
140 #ifdef CONFIG_KVM_MIPS_VZ
147 /* Unsupported KVM type */
151 /* Allocate page table to map GPA -> RPA */
152 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
153 if (!kvm->arch.gpa_mm.pgd)
156 #ifdef CONFIG_CPU_LOONGSON64
157 kvm_init_loongson_ipi(kvm);
163 void kvm_mips_free_vcpus(struct kvm *kvm)
166 struct kvm_vcpu *vcpu;
168 kvm_for_each_vcpu(i, vcpu, kvm) {
169 kvm_vcpu_destroy(vcpu);
172 mutex_lock(&kvm->lock);
174 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
175 kvm->vcpus[i] = NULL;
177 atomic_set(&kvm->online_vcpus, 0);
179 mutex_unlock(&kvm->lock);
182 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
184 /* It should always be safe to remove after flushing the whole range */
185 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
186 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
189 void kvm_arch_destroy_vm(struct kvm *kvm)
191 kvm_mips_free_vcpus(kvm);
192 kvm_mips_free_gpa_pt(kvm);
195 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
201 void kvm_arch_flush_shadow_all(struct kvm *kvm)
203 /* Flush whole GPA */
204 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
206 /* Let implementation do the rest */
207 kvm_mips_callbacks->flush_shadow_all(kvm);
210 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
211 struct kvm_memory_slot *slot)
214 * The slot has been made invalid (ready for moving or deletion), so we
215 * need to ensure that it can no longer be accessed by any guest VCPUs.
218 spin_lock(&kvm->mmu_lock);
219 /* Flush slot from GPA */
220 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
221 slot->base_gfn + slot->npages - 1);
222 /* Let implementation do the rest */
223 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
224 spin_unlock(&kvm->mmu_lock);
227 int kvm_arch_prepare_memory_region(struct kvm *kvm,
228 struct kvm_memory_slot *memslot,
229 const struct kvm_userspace_memory_region *mem,
230 enum kvm_mr_change change)
235 void kvm_arch_commit_memory_region(struct kvm *kvm,
236 const struct kvm_userspace_memory_region *mem,
237 struct kvm_memory_slot *old,
238 const struct kvm_memory_slot *new,
239 enum kvm_mr_change change)
243 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
244 __func__, kvm, mem->slot, mem->guest_phys_addr,
245 mem->memory_size, mem->userspace_addr);
248 * If dirty page logging is enabled, write protect all pages in the slot
249 * ready for dirty logging.
251 * There is no need to do this in any of the following cases:
252 * CREATE: No dirty mappings will already exist.
253 * MOVE/DELETE: The old mappings will already have been cleaned up by
254 * kvm_arch_flush_shadow_memslot()
256 if (change == KVM_MR_FLAGS_ONLY &&
257 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
258 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
259 spin_lock(&kvm->mmu_lock);
260 /* Write protect GPA page table entries */
261 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
262 new->base_gfn + new->npages - 1);
263 /* Let implementation do the rest */
265 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
266 spin_unlock(&kvm->mmu_lock);
270 static inline void dump_handler(const char *symbol, void *start, void *end)
274 pr_debug("LEAF(%s)\n", symbol);
276 pr_debug("\t.set push\n");
277 pr_debug("\t.set noreorder\n");
279 for (p = start; p < (u32 *)end; ++p)
280 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
282 pr_debug("\t.set\tpop\n");
284 pr_debug("\tEND(%s)\n", symbol);
287 /* low level hrtimer wake routine */
288 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
290 struct kvm_vcpu *vcpu;
292 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
294 kvm_mips_callbacks->queue_timer_int(vcpu);
297 rcuwait_wake_up(&vcpu->wait);
299 return kvm_mips_count_timeout(vcpu);
302 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
307 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
310 void *gebase, *p, *handler, *refill_start, *refill_end;
313 kvm_debug("kvm @ %p: create cpu %d at %p\n",
314 vcpu->kvm, vcpu->vcpu_id, vcpu);
316 err = kvm_mips_callbacks->vcpu_init(vcpu);
320 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
322 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
325 * Allocate space for host mode exception handlers that handle
328 if (cpu_has_veic || cpu_has_vint)
329 size = 0x200 + VECTORSPACING * 64;
333 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
337 goto out_uninit_vcpu;
339 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
340 ALIGN(size, PAGE_SIZE), gebase);
343 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
344 * limits us to the low 512MB of physical address space. If the memory
345 * we allocate is out of range, just give up now.
347 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
348 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
351 goto out_free_gebase;
355 vcpu->arch.guest_ebase = gebase;
357 /* Build guest exception vectors dynamically in unmapped memory */
358 handler = gebase + 0x2000;
360 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
361 refill_start = gebase;
362 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
363 refill_start += 0x080;
364 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
366 /* General Exception Entry point */
367 kvm_mips_build_exception(gebase + 0x180, handler);
369 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
370 for (i = 0; i < 8; i++) {
371 kvm_debug("L1 Vectored handler @ %p\n",
372 gebase + 0x200 + (i * VECTORSPACING));
373 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
377 /* General exit handler */
379 p = kvm_mips_build_exit(p);
381 /* Guest entry routine */
382 vcpu->arch.vcpu_run = p;
383 p = kvm_mips_build_vcpu_run(p);
385 /* Dump the generated code */
386 pr_debug("#include <asm/asm.h>\n");
387 pr_debug("#include <asm/regdef.h>\n");
389 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
390 dump_handler("kvm_tlb_refill", refill_start, refill_end);
391 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
392 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
394 /* Invalidate the icache for these ranges */
395 flush_icache_range((unsigned long)gebase,
396 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
399 * Allocate comm page for guest kernel, a TLB will be reserved for
400 * mapping GVA @ 0xFFFF8000 to this page
402 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
404 if (!vcpu->arch.kseg0_commpage) {
406 goto out_free_gebase;
409 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
410 kvm_mips_commpage_init(vcpu);
413 vcpu->arch.last_sched_cpu = -1;
414 vcpu->arch.last_exec_cpu = -1;
416 /* Initial guest state */
417 err = kvm_mips_callbacks->vcpu_setup(vcpu);
419 goto out_free_commpage;
424 kfree(vcpu->arch.kseg0_commpage);
428 kvm_mips_callbacks->vcpu_uninit(vcpu);
432 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
434 hrtimer_cancel(&vcpu->arch.comparecount_timer);
436 kvm_mips_dump_stats(vcpu);
438 kvm_mmu_free_memory_caches(vcpu);
439 kfree(vcpu->arch.guest_ebase);
440 kfree(vcpu->arch.kseg0_commpage);
442 kvm_mips_callbacks->vcpu_uninit(vcpu);
445 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
446 struct kvm_guest_debug *dbg)
451 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
453 struct kvm_run *run = vcpu->run;
458 kvm_sigset_activate(vcpu);
460 if (vcpu->mmio_needed) {
461 if (!vcpu->mmio_is_write)
462 kvm_mips_complete_mmio_load(vcpu, run);
463 vcpu->mmio_needed = 0;
466 if (run->immediate_exit)
472 guest_enter_irqoff();
473 trace_kvm_enter(vcpu);
476 * Make sure the read of VCPU requests in vcpu_run() callback is not
477 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
478 * flush request while the requester sees the VCPU as outside of guest
479 * mode and not needing an IPI.
481 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
483 r = kvm_mips_callbacks->vcpu_run(run, vcpu);
490 kvm_sigset_deactivate(vcpu);
496 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
497 struct kvm_mips_interrupt *irq)
499 int intr = (int)irq->irq;
500 struct kvm_vcpu *dvcpu = NULL;
502 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
503 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
504 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
505 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
506 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
512 dvcpu = vcpu->kvm->vcpus[irq->cpu];
514 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
515 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
517 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
518 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
520 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
525 dvcpu->arch.wait = 0;
527 rcuwait_wake_up(&dvcpu->wait);
532 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
533 struct kvm_mp_state *mp_state)
538 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
539 struct kvm_mp_state *mp_state)
544 static u64 kvm_mips_get_one_regs[] = {
578 #ifndef CONFIG_CPU_MIPSR6
585 static u64 kvm_mips_get_one_regs_fpu[] = {
587 KVM_REG_MIPS_FCR_CSR,
590 static u64 kvm_mips_get_one_regs_msa[] = {
592 KVM_REG_MIPS_MSA_CSR,
595 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
599 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
600 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
601 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
603 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
606 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
607 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
608 ret += kvm_mips_callbacks->num_regs(vcpu);
613 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
618 if (copy_to_user(indices, kvm_mips_get_one_regs,
619 sizeof(kvm_mips_get_one_regs)))
621 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
623 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
624 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
625 sizeof(kvm_mips_get_one_regs_fpu)))
627 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
629 for (i = 0; i < 32; ++i) {
630 index = KVM_REG_MIPS_FPR_32(i);
631 if (copy_to_user(indices, &index, sizeof(index)))
635 /* skip odd doubles if no F64 */
636 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
639 index = KVM_REG_MIPS_FPR_64(i);
640 if (copy_to_user(indices, &index, sizeof(index)))
646 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
647 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
648 sizeof(kvm_mips_get_one_regs_msa)))
650 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
652 for (i = 0; i < 32; ++i) {
653 index = KVM_REG_MIPS_VEC_128(i);
654 if (copy_to_user(indices, &index, sizeof(index)))
660 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
663 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
664 const struct kvm_one_reg *reg)
666 struct mips_coproc *cop0 = vcpu->arch.cop0;
667 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
674 /* General purpose registers */
675 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
676 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
678 #ifndef CONFIG_CPU_MIPSR6
679 case KVM_REG_MIPS_HI:
680 v = (long)vcpu->arch.hi;
682 case KVM_REG_MIPS_LO:
683 v = (long)vcpu->arch.lo;
686 case KVM_REG_MIPS_PC:
687 v = (long)vcpu->arch.pc;
690 /* Floating point registers */
691 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
692 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
694 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
695 /* Odd singles in top of even double when FR=0 */
696 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
697 v = get_fpr32(&fpu->fpr[idx], 0);
699 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
701 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
702 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
704 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
705 /* Can't access odd doubles in FR=0 mode */
706 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
708 v = get_fpr64(&fpu->fpr[idx], 0);
710 case KVM_REG_MIPS_FCR_IR:
711 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
713 v = boot_cpu_data.fpu_id;
715 case KVM_REG_MIPS_FCR_CSR:
716 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
721 /* MIPS SIMD Architecture (MSA) registers */
722 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
723 if (!kvm_mips_guest_has_msa(&vcpu->arch))
725 /* Can't access MSA registers in FR=0 mode */
726 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
728 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
729 #ifdef CONFIG_CPU_LITTLE_ENDIAN
730 /* least significant byte first */
731 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
732 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
734 /* most significant byte first */
735 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
736 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
739 case KVM_REG_MIPS_MSA_IR:
740 if (!kvm_mips_guest_has_msa(&vcpu->arch))
742 v = boot_cpu_data.msa_id;
744 case KVM_REG_MIPS_MSA_CSR:
745 if (!kvm_mips_guest_has_msa(&vcpu->arch))
750 /* registers to be handled specially */
752 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
757 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
758 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
760 return put_user(v, uaddr64);
761 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
762 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
765 return put_user(v32, uaddr32);
766 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
767 void __user *uaddr = (void __user *)(long)reg->addr;
769 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
775 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
776 const struct kvm_one_reg *reg)
778 struct mips_coproc *cop0 = vcpu->arch.cop0;
779 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
784 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
785 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
787 if (get_user(v, uaddr64) != 0)
789 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
790 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
793 if (get_user(v32, uaddr32) != 0)
796 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
797 void __user *uaddr = (void __user *)(long)reg->addr;
799 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
805 /* General purpose registers */
806 case KVM_REG_MIPS_R0:
807 /* Silently ignore requests to set $0 */
809 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
810 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
812 #ifndef CONFIG_CPU_MIPSR6
813 case KVM_REG_MIPS_HI:
816 case KVM_REG_MIPS_LO:
820 case KVM_REG_MIPS_PC:
824 /* Floating point registers */
825 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
826 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
828 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
829 /* Odd singles in top of even double when FR=0 */
830 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
831 set_fpr32(&fpu->fpr[idx], 0, v);
833 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
835 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
836 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
838 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
839 /* Can't access odd doubles in FR=0 mode */
840 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
842 set_fpr64(&fpu->fpr[idx], 0, v);
844 case KVM_REG_MIPS_FCR_IR:
845 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
849 case KVM_REG_MIPS_FCR_CSR:
850 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
855 /* MIPS SIMD Architecture (MSA) registers */
856 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
857 if (!kvm_mips_guest_has_msa(&vcpu->arch))
859 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
860 #ifdef CONFIG_CPU_LITTLE_ENDIAN
861 /* least significant byte first */
862 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
863 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
865 /* most significant byte first */
866 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
867 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
870 case KVM_REG_MIPS_MSA_IR:
871 if (!kvm_mips_guest_has_msa(&vcpu->arch))
875 case KVM_REG_MIPS_MSA_CSR:
876 if (!kvm_mips_guest_has_msa(&vcpu->arch))
881 /* registers to be handled specially */
883 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
888 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
889 struct kvm_enable_cap *cap)
893 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
901 case KVM_CAP_MIPS_FPU:
902 vcpu->arch.fpu_enabled = true;
904 case KVM_CAP_MIPS_MSA:
905 vcpu->arch.msa_enabled = true;
915 long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
918 struct kvm_vcpu *vcpu = filp->private_data;
919 void __user *argp = (void __user *)arg;
921 if (ioctl == KVM_INTERRUPT) {
922 struct kvm_mips_interrupt irq;
924 if (copy_from_user(&irq, argp, sizeof(irq)))
926 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
929 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
935 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
938 struct kvm_vcpu *vcpu = filp->private_data;
939 void __user *argp = (void __user *)arg;
945 case KVM_SET_ONE_REG:
946 case KVM_GET_ONE_REG: {
947 struct kvm_one_reg reg;
950 if (copy_from_user(®, argp, sizeof(reg)))
952 if (ioctl == KVM_SET_ONE_REG)
953 r = kvm_mips_set_reg(vcpu, ®);
955 r = kvm_mips_get_reg(vcpu, ®);
958 case KVM_GET_REG_LIST: {
959 struct kvm_reg_list __user *user_list = argp;
960 struct kvm_reg_list reg_list;
964 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
967 reg_list.n = kvm_mips_num_regs(vcpu);
968 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
973 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
976 case KVM_ENABLE_CAP: {
977 struct kvm_enable_cap cap;
980 if (copy_from_user(&cap, argp, sizeof(cap)))
982 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
993 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
998 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
999 struct kvm_memory_slot *memslot)
1001 /* Let implementation handle TLB/GVA invalidation */
1002 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1005 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1017 int kvm_arch_init(void *opaque)
1019 if (kvm_mips_callbacks) {
1020 kvm_err("kvm: module already exists\n");
1024 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1027 void kvm_arch_exit(void)
1029 kvm_mips_callbacks = NULL;
1032 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1033 struct kvm_sregs *sregs)
1035 return -ENOIOCTLCMD;
1038 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1039 struct kvm_sregs *sregs)
1041 return -ENOIOCTLCMD;
1044 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1048 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1050 return -ENOIOCTLCMD;
1053 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055 return -ENOIOCTLCMD;
1058 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1060 return VM_FAULT_SIGBUS;
1063 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1068 case KVM_CAP_ONE_REG:
1069 case KVM_CAP_ENABLE_CAP:
1070 case KVM_CAP_READONLY_MEM:
1071 case KVM_CAP_SYNC_MMU:
1072 case KVM_CAP_IMMEDIATE_EXIT:
1075 case KVM_CAP_NR_VCPUS:
1076 r = num_online_cpus();
1078 case KVM_CAP_MAX_VCPUS:
1081 case KVM_CAP_MAX_VCPU_ID:
1082 r = KVM_MAX_VCPU_ID;
1084 case KVM_CAP_MIPS_FPU:
1085 /* We don't handle systems with inconsistent cpu_has_fpu */
1086 r = !!raw_cpu_has_fpu;
1088 case KVM_CAP_MIPS_MSA:
1090 * We don't support MSA vector partitioning yet:
1091 * 1) It would require explicit support which can't be tested
1092 * yet due to lack of support in current hardware.
1093 * 2) It extends the state that would need to be saved/restored
1094 * by e.g. QEMU for migration.
1096 * When vector partitioning hardware becomes available, support
1097 * could be added by requiring a flag when enabling
1098 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1099 * to save/restore the appropriate extra state.
1101 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1104 r = kvm_mips_callbacks->check_extension(kvm, ext);
1110 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1112 return kvm_mips_pending_timer(vcpu) ||
1113 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1116 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1119 struct mips_coproc *cop0;
1124 kvm_debug("VCPU Register Dump:\n");
1125 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1126 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1128 for (i = 0; i < 32; i += 4) {
1129 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1131 vcpu->arch.gprs[i + 1],
1132 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1134 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1135 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1137 cop0 = vcpu->arch.cop0;
1138 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1139 kvm_read_c0_guest_status(cop0),
1140 kvm_read_c0_guest_cause(cop0));
1142 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1147 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1153 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1154 vcpu->arch.gprs[i] = regs->gpr[i];
1155 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1156 vcpu->arch.hi = regs->hi;
1157 vcpu->arch.lo = regs->lo;
1158 vcpu->arch.pc = regs->pc;
1164 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1170 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1171 regs->gpr[i] = vcpu->arch.gprs[i];
1173 regs->hi = vcpu->arch.hi;
1174 regs->lo = vcpu->arch.lo;
1175 regs->pc = vcpu->arch.pc;
1181 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1182 struct kvm_translation *tr)
1187 static void kvm_mips_set_c0_status(void)
1189 u32 status = read_c0_status();
1194 write_c0_status(status);
1199 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1201 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1203 u32 cause = vcpu->arch.host_cp0_cause;
1204 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1205 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1206 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1207 enum emulation_result er = EMULATE_DONE;
1209 int ret = RESUME_GUEST;
1211 vcpu->mode = OUTSIDE_GUEST_MODE;
1213 /* re-enable HTW before enabling interrupts */
1214 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1217 /* Set a default exit reason */
1218 run->exit_reason = KVM_EXIT_UNKNOWN;
1219 run->ready_for_interrupt_injection = 1;
1222 * Set the appropriate status bits based on host CPU features,
1223 * before we hit the scheduler
1225 kvm_mips_set_c0_status();
1229 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1230 cause, opc, run, vcpu);
1231 trace_kvm_exit(vcpu, exccode);
1233 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1235 * Do a privilege check, if in UM most of these exit conditions
1236 * end up causing an exception to be delivered to the Guest
1239 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1240 if (er == EMULATE_PRIV_FAIL) {
1242 } else if (er == EMULATE_FAIL) {
1243 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1251 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1253 ++vcpu->stat.int_exits;
1262 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1264 ++vcpu->stat.cop_unusable_exits;
1265 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1266 /* XXXKYMA: Might need to return to user space */
1267 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1272 ++vcpu->stat.tlbmod_exits;
1273 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1277 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1278 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1281 ++vcpu->stat.tlbmiss_st_exits;
1282 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1286 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1287 cause, opc, badvaddr);
1289 ++vcpu->stat.tlbmiss_ld_exits;
1290 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1294 ++vcpu->stat.addrerr_st_exits;
1295 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1299 ++vcpu->stat.addrerr_ld_exits;
1300 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1304 ++vcpu->stat.syscall_exits;
1305 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1309 ++vcpu->stat.resvd_inst_exits;
1310 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1314 ++vcpu->stat.break_inst_exits;
1315 ret = kvm_mips_callbacks->handle_break(vcpu);
1319 ++vcpu->stat.trap_inst_exits;
1320 ret = kvm_mips_callbacks->handle_trap(vcpu);
1323 case EXCCODE_MSAFPE:
1324 ++vcpu->stat.msa_fpe_exits;
1325 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1329 ++vcpu->stat.fpe_exits;
1330 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1333 case EXCCODE_MSADIS:
1334 ++vcpu->stat.msa_disabled_exits;
1335 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1339 /* defer exit accounting to handler */
1340 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1344 if (cause & CAUSEF_BD)
1347 kvm_get_badinstr(opc, vcpu, &inst);
1348 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1349 exccode, opc, inst, badvaddr,
1350 kvm_read_c0_guest_status(vcpu->arch.cop0));
1351 kvm_arch_vcpu_dump_regs(vcpu);
1352 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1359 local_irq_disable();
1361 if (ret == RESUME_GUEST)
1362 kvm_vz_acquire_htimer(vcpu);
1364 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1365 kvm_mips_deliver_interrupts(vcpu, cause);
1367 if (!(ret & RESUME_HOST)) {
1368 /* Only check for signals if not already exiting to userspace */
1369 if (signal_pending(current)) {
1370 run->exit_reason = KVM_EXIT_INTR;
1371 ret = (-EINTR << 2) | RESUME_HOST;
1372 ++vcpu->stat.signal_exits;
1373 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1377 if (ret == RESUME_GUEST) {
1378 trace_kvm_reenter(vcpu);
1381 * Make sure the read of VCPU requests in vcpu_reenter()
1382 * callback is not reordered ahead of the write to vcpu->mode,
1383 * or we could miss a TLB flush request while the requester sees
1384 * the VCPU as outside of guest mode and not needing an IPI.
1386 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1388 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1391 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1392 * is live), restore FCR31 / MSACSR.
1394 * This should be before returning to the guest exception
1395 * vector, as it may well cause an [MSA] FP exception if there
1396 * are pending exception bits unmasked. (see
1397 * kvm_mips_csr_die_notifier() for how that is handled).
1399 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1400 read_c0_status() & ST0_CU1)
1401 __kvm_restore_fcsr(&vcpu->arch);
1403 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1404 read_c0_config5() & MIPS_CONF5_MSAEN)
1405 __kvm_restore_msacsr(&vcpu->arch);
1408 /* Disable HTW before returning to guest or host */
1409 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1415 /* Enable FPU for guest and restore context */
1416 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1418 struct mips_coproc *cop0 = vcpu->arch.cop0;
1419 unsigned int sr, cfg5;
1423 sr = kvm_read_c0_guest_status(cop0);
1426 * If MSA state is already live, it is undefined how it interacts with
1427 * FR=0 FPU state, and we don't want to hit reserved instruction
1428 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1429 * play it safe and save it first.
1431 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1432 * get called when guest CU1 is set, however we can't trust the guest
1433 * not to clobber the status register directly via the commpage.
1435 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1436 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1440 * Enable FPU for guest
1441 * We set FR and FRE according to guest context
1443 change_c0_status(ST0_CU1 | ST0_FR, sr);
1445 cfg5 = kvm_read_c0_guest_config5(cop0);
1446 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1448 enable_fpu_hazard();
1450 /* If guest FPU state not active, restore it now */
1451 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1452 __kvm_restore_fpu(&vcpu->arch);
1453 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1454 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1456 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1462 #ifdef CONFIG_CPU_HAS_MSA
1463 /* Enable MSA for guest and restore context */
1464 void kvm_own_msa(struct kvm_vcpu *vcpu)
1466 struct mips_coproc *cop0 = vcpu->arch.cop0;
1467 unsigned int sr, cfg5;
1472 * Enable FPU if enabled in guest, since we're restoring FPU context
1473 * anyway. We set FR and FRE according to guest context.
1475 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1476 sr = kvm_read_c0_guest_status(cop0);
1479 * If FR=0 FPU state is already live, it is undefined how it
1480 * interacts with MSA state, so play it safe and save it first.
1482 if (!(sr & ST0_FR) &&
1483 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1484 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1487 change_c0_status(ST0_CU1 | ST0_FR, sr);
1488 if (sr & ST0_CU1 && cpu_has_fre) {
1489 cfg5 = kvm_read_c0_guest_config5(cop0);
1490 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1494 /* Enable MSA for guest */
1495 set_c0_config5(MIPS_CONF5_MSAEN);
1496 enable_fpu_hazard();
1498 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1499 case KVM_MIPS_AUX_FPU:
1501 * Guest FPU state already loaded, only restore upper MSA state
1503 __kvm_restore_msa_upper(&vcpu->arch);
1504 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1505 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1508 /* Neither FPU or MSA already active, restore full MSA state */
1509 __kvm_restore_msa(&vcpu->arch);
1510 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1511 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1512 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1513 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1514 KVM_TRACE_AUX_FPU_MSA);
1517 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1525 /* Drop FPU & MSA without saving it */
1526 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1529 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1531 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1532 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1534 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1535 clear_c0_status(ST0_CU1 | ST0_FR);
1536 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1537 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1542 /* Save and disable FPU & MSA */
1543 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1546 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1547 * is disabled in guest context (software), but the register state in
1548 * the hardware may still be in use.
1549 * This is why we explicitly re-enable the hardware before saving.
1553 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1554 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1555 set_c0_config5(MIPS_CONF5_MSAEN);
1556 enable_fpu_hazard();
1559 __kvm_save_msa(&vcpu->arch);
1560 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1562 /* Disable MSA & FPU */
1564 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1565 clear_c0_status(ST0_CU1 | ST0_FR);
1566 disable_fpu_hazard();
1568 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1569 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1570 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1571 set_c0_status(ST0_CU1);
1572 enable_fpu_hazard();
1575 __kvm_save_fpu(&vcpu->arch);
1576 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1577 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1580 clear_c0_status(ST0_CU1 | ST0_FR);
1581 disable_fpu_hazard();
1587 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1588 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1589 * exception if cause bits are set in the value being written.
1591 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1592 unsigned long cmd, void *ptr)
1594 struct die_args *args = (struct die_args *)ptr;
1595 struct pt_regs *regs = args->regs;
1598 /* Only interested in FPE and MSAFPE */
1599 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1602 /* Return immediately if guest context isn't active */
1603 if (!(current->flags & PF_VCPU))
1606 /* Should never get here from user mode */
1607 BUG_ON(user_mode(regs));
1609 pc = instruction_pointer(regs);
1612 /* match 2nd instruction in __kvm_restore_fcsr */
1613 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1617 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1619 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1620 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1625 /* Move PC forward a little and continue executing */
1626 instruction_pointer(regs) += 4;
1631 static struct notifier_block kvm_mips_csr_die_notifier = {
1632 .notifier_call = kvm_mips_csr_die_notify,
1635 static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1636 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1637 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1638 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1639 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1642 static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1643 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1644 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1645 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1646 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1649 u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1651 u32 kvm_irq_to_priority(u32 irq)
1655 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1656 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1660 return MIPS_EXC_MAX;
1663 static int __init kvm_mips_init(void)
1668 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1672 ret = kvm_mips_entry_setup();
1676 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1681 if (boot_cpu_type() == CPU_LOONGSON64)
1682 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1684 register_die_notifier(&kvm_mips_csr_die_notifier);
1689 static void __exit kvm_mips_exit(void)
1693 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1696 module_init(kvm_mips_init);
1697 module_exit(kvm_mips_exit);
1699 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);