arch/mips/kvm/emulate.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: Instruction/Exception emulation
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/errno.h>
  13 #include <linux/err.h>
  14 #include <linux/ktime.h>
  15 #include <linux/kvm_host.h>
  16 #include <linux/module.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/fs.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/random.h>
  21 #include <asm/page.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/cacheops.h>
  24 #include <asm/cpu-info.h>
  25 #include <asm/mmu_context.h>
  26 #include <asm/tlbflush.h>
  27 #include <asm/inst.h>
  28
  29 #undef CONFIG_MIPS_MT
  30 #include <asm/r4kcache.h>
  31 #define CONFIG_MIPS_MT
  32
  33 #include "interrupt.h"
  34 #include "commpage.h"
  35
  36 #include "trace.h"
  37
  38 /*
  39  * Compute the return address and do emulate branch simulation, if required.
  40  * This function should be called only in branch delay slot active.
  41  */
  42 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
  43         unsigned long instpc)
  44 {
  45         unsigned int dspcontrol;
  46         union mips_instruction insn;
  47         struct kvm_vcpu_arch *arch = &vcpu->arch;
  48         long epc = instpc;
  49         long nextpc = KVM_INVALID_INST;
  50
  51         if (epc & 3)
  52                 goto unaligned;
  53
  54         /* Read the instruction */
  55         insn.word = kvm_get_inst((u32 *) epc, vcpu);
  56
  57         if (insn.word == KVM_INVALID_INST)
  58                 return KVM_INVALID_INST;
  59
  60         switch (insn.i_format.opcode) {
  61                 /* jr and jalr are in r_format format. */
  62         case spec_op:
  63                 switch (insn.r_format.func) {
  64                 case jalr_op:
  65                         arch->gprs[insn.r_format.rd] = epc + 8;
  66                         /* Fall through */
  67                 case jr_op:
  68                         nextpc = arch->gprs[insn.r_format.rs];
  69                         break;
  70                 }
  71                 break;
  72
  73                 /*
  74                  * This group contains:
  75                  * bltz_op, bgez_op, bltzl_op, bgezl_op,
  76                  * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
  77                  */
  78         case bcond_op:
  79                 switch (insn.i_format.rt) {
  80                 case bltz_op:
  81                 case bltzl_op:
  82                         if ((long)arch->gprs[insn.i_format.rs] < 0)
  83                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  84                         else
  85                                 epc += 8;
  86                         nextpc = epc;
  87                         break;
  88
  89                 case bgez_op:
  90                 case bgezl_op:
  91                         if ((long)arch->gprs[insn.i_format.rs] >= 0)
  92                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  93                         else
  94                                 epc += 8;
  95                         nextpc = epc;
  96                         break;
  97
  98                 case bltzal_op:
  99                 case bltzall_op:
 100                         arch->gprs[31] = epc + 8;
 101                         if ((long)arch->gprs[insn.i_format.rs] < 0)
 102                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 103                         else
 104                                 epc += 8;
 105                         nextpc = epc;
 106                         break;
 107
 108                 case bgezal_op:
 109                 case bgezall_op:
 110                         arch->gprs[31] = epc + 8;
 111                         if ((long)arch->gprs[insn.i_format.rs] >= 0)
 112                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 113                         else
 114                                 epc += 8;
 115                         nextpc = epc;
 116                         break;
 117                 case bposge32_op:
 118                         if (!cpu_has_dsp)
 119                                 goto sigill;
 120
 121                         dspcontrol = rddsp(0x01);
 122
 123                         if (dspcontrol >= 32)
 124                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 125                         else
 126                                 epc += 8;
 127                         nextpc = epc;
 128                         break;
 129                 }
 130                 break;
 131
 132                 /* These are unconditional and in j_format. */
 133         case jal_op:
 134                 arch->gprs[31] = instpc + 8;
 135         case j_op:
 136                 epc += 4;
 137                 epc >>= 28;
 138                 epc <<= 28;
 139                 epc |= (insn.j_format.target << 2);
 140                 nextpc = epc;
 141                 break;
 142
 143                 /* These are conditional and in i_format. */
 144         case beq_op:
 145         case beql_op:
 146                 if (arch->gprs[insn.i_format.rs] ==
 147                     arch->gprs[insn.i_format.rt])
 148                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 149                 else
 150                         epc += 8;
 151                 nextpc = epc;
 152                 break;
 153
 154         case bne_op:
 155         case bnel_op:
 156                 if (arch->gprs[insn.i_format.rs] !=
 157                     arch->gprs[insn.i_format.rt])
 158                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 159                 else
 160                         epc += 8;
 161                 nextpc = epc;
 162                 break;
 163
 164         case blez_op:           /* not really i_format */
 165         case blezl_op:
 166                 /* rt field assumed to be zero */
 167                 if ((long)arch->gprs[insn.i_format.rs] <= 0)
 168                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 169                 else
 170                         epc += 8;
 171                 nextpc = epc;
 172                 break;
 173
 174         case bgtz_op:
 175         case bgtzl_op:
 176                 /* rt field assumed to be zero */
 177                 if ((long)arch->gprs[insn.i_format.rs] > 0)
 178                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 179                 else
 180                         epc += 8;
 181                 nextpc = epc;
 182                 break;
 183
 184                 /* And now the FPA/cp1 branch instructions. */
 185         case cop1_op:
 186                 kvm_err("%s: unsupported cop1_op\n", __func__);
 187                 break;
 188         }
 189
 190         return nextpc;
 191
 192 unaligned:
 193         kvm_err("%s: unaligned epc\n", __func__);
 194         return nextpc;
 195
 196 sigill:
 197         kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
 198         return nextpc;
 199 }
 200
 201 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause)
 202 {
 203         unsigned long branch_pc;
 204         enum emulation_result er = EMULATE_DONE;
 205
 206         if (cause & CAUSEF_BD) {
 207                 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
 208                 if (branch_pc == KVM_INVALID_INST) {
 209                         er = EMULATE_FAIL;
 210                 } else {
 211                         vcpu->arch.pc = branch_pc;
 212                         kvm_debug("BD update_pc(): New PC: %#lx\n",
 213                                   vcpu->arch.pc);
 214                 }
 215         } else
 216                 vcpu->arch.pc += 4;
 217
 218         kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
 219
 220         return er;
 221 }
 222
 223 /**
 224  * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
 225  * @vcpu:       Virtual CPU.
 226  *
 227  * Returns:     1 if the CP0_Count timer is disabled by either the guest
 228  *              CP0_Cause.DC bit or the count_ctl.DC bit.
 229  *              0 otherwise (in which case CP0_Count timer is running).
 230  */
 231 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
 232 {
 233         struct mips_coproc *cop0 = vcpu->arch.cop0;
 234
 235         return  (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
 236                 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
 237 }
 238
 239 /**
 240  * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
 241  *
 242  * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
 243  *
 244  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
 245  */
 246 static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
 247 {
 248         s64 now_ns, periods;
 249         u64 delta;
 250
 251         now_ns = ktime_to_ns(now);
 252         delta = now_ns + vcpu->arch.count_dyn_bias;
 253
 254         if (delta >= vcpu->arch.count_period) {
 255                 /* If delta is out of safe range the bias needs adjusting */
 256                 periods = div64_s64(now_ns, vcpu->arch.count_period);
 257                 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
 258                 /* Recalculate delta with new bias */
 259                 delta = now_ns + vcpu->arch.count_dyn_bias;
 260         }
 261
 262         /*
 263          * We've ensured that:
 264          *   delta < count_period
 265          *
 266          * Therefore the intermediate delta*count_hz will never overflow since
 267          * at the boundary condition:
 268          *   delta = count_period
 269          *   delta = NSEC_PER_SEC * 2^32 / count_hz
 270          *   delta * count_hz = NSEC_PER_SEC * 2^32
 271          */
 272         return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
 273 }
 274
 275 /**
 276  * kvm_mips_count_time() - Get effective current time.
 277  * @vcpu:       Virtual CPU.
 278  *
 279  * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
 280  * except when the master disable bit is set in count_ctl, in which case it is
 281  * count_resume, i.e. the time that the count was disabled.
 282  *
 283  * Returns:     Effective monotonic ktime for CP0_Count.
 284  */
 285 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
 286 {
 287         if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
 288                 return vcpu->arch.count_resume;
 289
 290         return ktime_get();
 291 }
 292
 293 /**
 294  * kvm_mips_read_count_running() - Read the current count value as if running.
 295  * @vcpu:       Virtual CPU.
 296  * @now:        Kernel time to read CP0_Count at.
 297  *
 298  * Returns the current guest CP0_Count register at time @now and handles if the
 299  * timer interrupt is pending and hasn't been handled yet.
 300  *
 301  * Returns:     The current value of the guest CP0_Count register.
 302  */
 303 static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
 304 {
 305         struct mips_coproc *cop0 = vcpu->arch.cop0;
 306         ktime_t expires, threshold;
 307         u32 count, compare;
 308         int running;
 309
 310         /* Calculate the biased and scaled guest CP0_Count */
 311         count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
 312         compare = kvm_read_c0_guest_compare(cop0);
 313
 314         /*
 315          * Find whether CP0_Count has reached the closest timer interrupt. If
 316          * not, we shouldn't inject it.
 317          */
 318         if ((s32)(count - compare) < 0)
 319                 return count;
 320
 321         /*
 322          * The CP0_Count we're going to return has already reached the closest
 323          * timer interrupt. Quickly check if it really is a new interrupt by
 324          * looking at whether the interval until the hrtimer expiry time is
 325          * less than 1/4 of the timer period.
 326          */
 327         expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
 328         threshold = ktime_add_ns(now, vcpu->arch.count_period / 4);
 329         if (ktime_before(expires, threshold)) {
 330                 /*
 331                  * Cancel it while we handle it so there's no chance of
 332                  * interference with the timeout handler.
 333                  */
 334                 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
 335
 336                 /* Nothing should be waiting on the timeout */
 337                 kvm_mips_callbacks->queue_timer_int(vcpu);
 338
 339                 /*
 340                  * Restart the timer if it was running based on the expiry time
 341                  * we read, so that we don't push it back 2 periods.
 342                  */
 343                 if (running) {
 344                         expires = ktime_add_ns(expires,
 345                                                vcpu->arch.count_period);
 346                         hrtimer_start(&vcpu->arch.comparecount_timer, expires,
 347                                       HRTIMER_MODE_ABS);
 348                 }
 349         }
 350
 351         return count;
 352 }
 353
 354 /**
 355  * kvm_mips_read_count() - Read the current count value.
 356  * @vcpu:       Virtual CPU.
 357  *
 358  * Read the current guest CP0_Count value, taking into account whether the timer
 359  * is stopped.
 360  *
 361  * Returns:     The current guest CP0_Count value.
 362  */
 363 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu)
 364 {
 365         struct mips_coproc *cop0 = vcpu->arch.cop0;
 366
 367         /* If count disabled just read static copy of count */
 368         if (kvm_mips_count_disabled(vcpu))
 369                 return kvm_read_c0_guest_count(cop0);
 370
 371         return kvm_mips_read_count_running(vcpu, ktime_get());
 372 }
 373
 374 /**
 375  * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
 376  * @vcpu:       Virtual CPU.
 377  * @count:      Output pointer for CP0_Count value at point of freeze.
 378  *
 379  * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
 380  * at the point it was frozen. It is guaranteed that any pending interrupts at
 381  * the point it was frozen are handled, and none after that point.
 382  *
 383  * This is useful where the time/CP0_Count is needed in the calculation of the
 384  * new parameters.
 385  *
 386  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
 387  *
 388  * Returns:     The ktime at the point of freeze.
 389  */
 390 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count)
 391 {
 392         ktime_t now;
 393
 394         /* stop hrtimer before finding time */
 395         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 396         now = ktime_get();
 397
 398         /* find count at this point and handle pending hrtimer */
 399         *count = kvm_mips_read_count_running(vcpu, now);
 400
 401         return now;
 402 }
 403
 404 /**
 405  * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
 406  * @vcpu:       Virtual CPU.
 407  * @now:        ktime at point of resume.
 408  * @count:      CP0_Count at point of resume.
 409  *
 410  * Resumes the timer and updates the timer expiry based on @now and @count.
 411  * This can be used in conjunction with kvm_mips_freeze_timer() when timer
 412  * parameters need to be changed.
 413  *
 414  * It is guaranteed that a timer interrupt immediately after resume will be
 415  * handled, but not if CP_Compare is exactly at @count. That case is already
 416  * handled by kvm_mips_freeze_timer().
 417  *
 418  * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
 419  */
 420 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
 421                                     ktime_t now, u32 count)
 422 {
 423         struct mips_coproc *cop0 = vcpu->arch.cop0;
 424         u32 compare;
 425         u64 delta;
 426         ktime_t expire;
 427
 428         /* Calculate timeout (wrap 0 to 2^32) */
 429         compare = kvm_read_c0_guest_compare(cop0);
 430         delta = (u64)(u32)(compare - count - 1) + 1;
 431         delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
 432         expire = ktime_add_ns(now, delta);
 433
 434         /* Update hrtimer to use new timeout */
 435         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 436         hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
 437 }
 438
 439 /**
 440  * kvm_mips_write_count() - Modify the count and update timer.
 441  * @vcpu:       Virtual CPU.
 442  * @count:      Guest CP0_Count value to set.
 443  *
 444  * Sets the CP0_Count value and updates the timer accordingly.
 445  */
 446 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count)
 447 {
 448         struct mips_coproc *cop0 = vcpu->arch.cop0;
 449         ktime_t now;
 450
 451         /* Calculate bias */
 452         now = kvm_mips_count_time(vcpu);
 453         vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
 454
 455         if (kvm_mips_count_disabled(vcpu))
 456                 /* The timer's disabled, adjust the static count */
 457                 kvm_write_c0_guest_count(cop0, count);
 458         else
 459                 /* Update timeout */
 460                 kvm_mips_resume_hrtimer(vcpu, now, count);
 461 }
 462
 463 /**
 464  * kvm_mips_init_count() - Initialise timer.
 465  * @vcpu:       Virtual CPU.
 466  *
 467  * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
 468  * it going if it's enabled.
 469  */
 470 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
 471 {
 472         /* 100 MHz */
 473         vcpu->arch.count_hz = 100*1000*1000;
 474         vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
 475                                           vcpu->arch.count_hz);
 476         vcpu->arch.count_dyn_bias = 0;
 477
 478         /* Starting at 0 */
 479         kvm_mips_write_count(vcpu, 0);
 480 }
 481
 482 /**
 483  * kvm_mips_set_count_hz() - Update the frequency of the timer.
 484  * @vcpu:       Virtual CPU.
 485  * @count_hz:   Frequency of CP0_Count timer in Hz.
 486  *
 487  * Change the frequency of the CP0_Count timer. This is done atomically so that
 488  * CP0_Count is continuous and no timer interrupt is lost.
 489  *
 490  * Returns:     -EINVAL if @count_hz is out of range.
 491  *              0 on success.
 492  */
 493 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
 494 {
 495         struct mips_coproc *cop0 = vcpu->arch.cop0;
 496         int dc;
 497         ktime_t now;
 498         u32 count;
 499
 500         /* ensure the frequency is in a sensible range... */
 501         if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
 502                 return -EINVAL;
 503         /* ... and has actually changed */
 504         if (vcpu->arch.count_hz == count_hz)
 505                 return 0;
 506
 507         /* Safely freeze timer so we can keep it continuous */
 508         dc = kvm_mips_count_disabled(vcpu);
 509         if (dc) {
 510                 now = kvm_mips_count_time(vcpu);
 511                 count = kvm_read_c0_guest_count(cop0);
 512         } else {
 513                 now = kvm_mips_freeze_hrtimer(vcpu, &count);
 514         }
 515
 516         /* Update the frequency */
 517         vcpu->arch.count_hz = count_hz;
 518         vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
 519         vcpu->arch.count_dyn_bias = 0;
 520
 521         /* Calculate adjusted bias so dynamic count is unchanged */
 522         vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
 523
 524         /* Update and resume hrtimer */
 525         if (!dc)
 526                 kvm_mips_resume_hrtimer(vcpu, now, count);
 527         return 0;
 528 }
 529
 530 /**
 531  * kvm_mips_write_compare() - Modify compare and update timer.
 532  * @vcpu:       Virtual CPU.
 533  * @compare:    New CP0_Compare value.
 534  * @ack:        Whether to acknowledge timer interrupt.
 535  *
 536  * Update CP0_Compare to a new value and update the timeout.
 537  * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure
 538  * any pending timer interrupt is preserved.
 539  */
 540 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
 541 {
 542         struct mips_coproc *cop0 = vcpu->arch.cop0;
 543         int dc;
 544         u32 old_compare = kvm_read_c0_guest_compare(cop0);
 545         ktime_t now;
 546         u32 count;
 547
 548         /* if unchanged, must just be an ack */
 549         if (old_compare == compare) {
 550                 if (!ack)
 551                         return;
 552                 kvm_mips_callbacks->dequeue_timer_int(vcpu);
 553                 kvm_write_c0_guest_compare(cop0, compare);
 554                 return;
 555         }
 556
 557         /* freeze_hrtimer() takes care of timer interrupts <= count */
 558         dc = kvm_mips_count_disabled(vcpu);
 559         if (!dc)
 560                 now = kvm_mips_freeze_hrtimer(vcpu, &count);
 561
 562         if (ack)
 563                 kvm_mips_callbacks->dequeue_timer_int(vcpu);
 564
 565         kvm_write_c0_guest_compare(cop0, compare);
 566
 567         /* resume_hrtimer() takes care of timer interrupts > count */
 568         if (!dc)
 569                 kvm_mips_resume_hrtimer(vcpu, now, count);
 570 }
 571
 572 /**
 573  * kvm_mips_count_disable() - Disable count.
 574  * @vcpu:       Virtual CPU.
 575  *
 576  * Disable the CP0_Count timer. A timer interrupt on or before the final stop
 577  * time will be handled but not after.
 578  *
 579  * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
 580  * count_ctl.DC has been set (count disabled).
 581  *
 582  * Returns:     The time that the timer was stopped.
 583  */
 584 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
 585 {
 586         struct mips_coproc *cop0 = vcpu->arch.cop0;
 587         u32 count;
 588         ktime_t now;
 589
 590         /* Stop hrtimer */
 591         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 592
 593         /* Set the static count from the dynamic count, handling pending TI */
 594         now = ktime_get();
 595         count = kvm_mips_read_count_running(vcpu, now);
 596         kvm_write_c0_guest_count(cop0, count);
 597
 598         return now;
 599 }
 600
 601 /**
 602  * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
 603  * @vcpu:       Virtual CPU.
 604  *
 605  * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
 606  * before the final stop time will be handled if the timer isn't disabled by
 607  * count_ctl.DC, but not after.
 608  *
 609  * Assumes CP0_Cause.DC is clear (count enabled).
 610  */
 611 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
 612 {
 613         struct mips_coproc *cop0 = vcpu->arch.cop0;
 614
 615         kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
 616         if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
 617                 kvm_mips_count_disable(vcpu);
 618 }
 619
 620 /**
 621  * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
 622  * @vcpu:       Virtual CPU.
 623  *
 624  * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
 625  * the start time will be handled if the timer isn't disabled by count_ctl.DC,
 626  * potentially before even returning, so the caller should be careful with
 627  * ordering of CP0_Cause modifications so as not to lose it.
 628  *
 629  * Assumes CP0_Cause.DC is set (count disabled).
 630  */
 631 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
 632 {
 633         struct mips_coproc *cop0 = vcpu->arch.cop0;
 634         u32 count;
 635
 636         kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
 637
 638         /*
 639          * Set the dynamic count to match the static count.
 640          * This starts the hrtimer if count_ctl.DC allows it.
 641          * Otherwise it conveniently updates the biases.
 642          */
 643         count = kvm_read_c0_guest_count(cop0);
 644         kvm_mips_write_count(vcpu, count);
 645 }
 646
 647 /**
 648  * kvm_mips_set_count_ctl() - Update the count control KVM register.
 649  * @vcpu:       Virtual CPU.
 650  * @count_ctl:  Count control register new value.
 651  *
 652  * Set the count control KVM register. The timer is updated accordingly.
 653  *
 654  * Returns:     -EINVAL if reserved bits are set.
 655  *              0 on success.
 656  */
 657 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
 658 {
 659         struct mips_coproc *cop0 = vcpu->arch.cop0;
 660         s64 changed = count_ctl ^ vcpu->arch.count_ctl;
 661         s64 delta;
 662         ktime_t expire, now;
 663         u32 count, compare;
 664
 665         /* Only allow defined bits to be changed */
 666         if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
 667                 return -EINVAL;
 668
 669         /* Apply new value */
 670         vcpu->arch.count_ctl = count_ctl;
 671
 672         /* Master CP0_Count disable */
 673         if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
 674                 /* Is CP0_Cause.DC already disabling CP0_Count? */
 675                 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
 676                         if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
 677                                 /* Just record the current time */
 678                                 vcpu->arch.count_resume = ktime_get();
 679                 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
 680                         /* disable timer and record current time */
 681                         vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
 682                 } else {
 683                         /*
 684                          * Calculate timeout relative to static count at resume
 685                          * time (wrap 0 to 2^32).
 686                          */
 687                         count = kvm_read_c0_guest_count(cop0);
 688                         compare = kvm_read_c0_guest_compare(cop0);
 689                         delta = (u64)(u32)(compare - count - 1) + 1;
 690                         delta = div_u64(delta * NSEC_PER_SEC,
 691                                         vcpu->arch.count_hz);
 692                         expire = ktime_add_ns(vcpu->arch.count_resume, delta);
 693
 694                         /* Handle pending interrupt */
 695                         now = ktime_get();
 696                         if (ktime_compare(now, expire) >= 0)
 697                                 /* Nothing should be waiting on the timeout */
 698                                 kvm_mips_callbacks->queue_timer_int(vcpu);
 699
 700                         /* Resume hrtimer without changing bias */
 701                         count = kvm_mips_read_count_running(vcpu, now);
 702                         kvm_mips_resume_hrtimer(vcpu, now, count);
 703                 }
 704         }
 705
 706         return 0;
 707 }
 708
 709 /**
 710  * kvm_mips_set_count_resume() - Update the count resume KVM register.
 711  * @vcpu:               Virtual CPU.
 712  * @count_resume:       Count resume register new value.
 713  *
 714  * Set the count resume KVM register.
 715  *
 716  * Returns:     -EINVAL if out of valid range (0..now).
 717  *              0 on success.
 718  */
 719 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
 720 {
 721         /*
 722          * It doesn't make sense for the resume time to be in the future, as it
 723          * would be possible for the next interrupt to be more than a full
 724          * period in the future.
 725          */
 726         if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
 727                 return -EINVAL;
 728
 729         vcpu->arch.count_resume = ns_to_ktime(count_resume);
 730         return 0;
 731 }
 732
 733 /**
 734  * kvm_mips_count_timeout() - Push timer forward on timeout.
 735  * @vcpu:       Virtual CPU.
 736  *
 737  * Handle an hrtimer event by push the hrtimer forward a period.
 738  *
 739  * Returns:     The hrtimer_restart value to return to the hrtimer subsystem.
 740  */
 741 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
 742 {
 743         /* Add the Count period to the current expiry time */
 744         hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
 745                                vcpu->arch.count_period);
 746         return HRTIMER_RESTART;
 747 }
 748
 749 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
 750 {
 751         struct mips_coproc *cop0 = vcpu->arch.cop0;
 752         enum emulation_result er = EMULATE_DONE;
 753
 754         if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
 755                 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
 756                           kvm_read_c0_guest_epc(cop0));
 757                 kvm_clear_c0_guest_status(cop0, ST0_EXL);
 758                 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
 759
 760         } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
 761                 kvm_clear_c0_guest_status(cop0, ST0_ERL);
 762                 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
 763         } else {
 764                 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
 765                         vcpu->arch.pc);
 766                 er = EMULATE_FAIL;
 767         }
 768
 769         return er;
 770 }
 771
 772 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
 773 {
 774         kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
 775                   vcpu->arch.pending_exceptions);
 776
 777         ++vcpu->stat.wait_exits;
 778         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT);
 779         if (!vcpu->arch.pending_exceptions) {
 780                 vcpu->arch.wait = 1;
 781                 kvm_vcpu_block(vcpu);
 782
 783                 /*
 784                  * We we are runnable, then definitely go off to user space to
 785                  * check if any I/O interrupts are pending.
 786                  */
 787                 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
 788                         clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
 789                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
 790                 }
 791         }
 792
 793         return EMULATE_DONE;
 794 }
 795
 796 /*
 797  * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
 798  * we can catch this, if things ever change
 799  */
 800 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
 801 {
 802         struct mips_coproc *cop0 = vcpu->arch.cop0;
 803         unsigned long pc = vcpu->arch.pc;
 804
 805         kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
 806         return EMULATE_FAIL;
 807 }
 808
 809 /* Write Guest TLB Entry @ Index */
 810 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
 811 {
 812         struct mips_coproc *cop0 = vcpu->arch.cop0;
 813         int index = kvm_read_c0_guest_index(cop0);
 814         struct kvm_mips_tlb *tlb = NULL;
 815         unsigned long pc = vcpu->arch.pc;
 816
 817         if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
 818                 kvm_debug("%s: illegal index: %d\n", __func__, index);
 819                 kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
 820                           pc, index, kvm_read_c0_guest_entryhi(cop0),
 821                           kvm_read_c0_guest_entrylo0(cop0),
 822                           kvm_read_c0_guest_entrylo1(cop0),
 823                           kvm_read_c0_guest_pagemask(cop0));
 824                 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
 825         }
 826
 827         tlb = &vcpu->arch.guest_tlb[index];
 828         /*
 829          * Probe the shadow host TLB for the entry being overwritten, if one
 830          * matches, invalidate it
 831          */
 832         kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
 833
 834         tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
 835         tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
 836         tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
 837         tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
 838
 839         kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
 840                   pc, index, kvm_read_c0_guest_entryhi(cop0),
 841                   kvm_read_c0_guest_entrylo0(cop0),
 842                   kvm_read_c0_guest_entrylo1(cop0),
 843                   kvm_read_c0_guest_pagemask(cop0));
 844
 845         return EMULATE_DONE;
 846 }
 847
 848 /* Write Guest TLB Entry @ Random Index */
 849 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
 850 {
 851         struct mips_coproc *cop0 = vcpu->arch.cop0;
 852         struct kvm_mips_tlb *tlb = NULL;
 853         unsigned long pc = vcpu->arch.pc;
 854         int index;
 855
 856         get_random_bytes(&index, sizeof(index));
 857         index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
 858
 859         tlb = &vcpu->arch.guest_tlb[index];
 860
 861         /*
 862          * Probe the shadow host TLB for the entry being overwritten, if one
 863          * matches, invalidate it
 864          */
 865         kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
 866
 867         tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
 868         tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
 869         tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
 870         tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
 871
 872         kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
 873                   pc, index, kvm_read_c0_guest_entryhi(cop0),
 874                   kvm_read_c0_guest_entrylo0(cop0),
 875                   kvm_read_c0_guest_entrylo1(cop0));
 876
 877         return EMULATE_DONE;
 878 }
 879
 880 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
 881 {
 882         struct mips_coproc *cop0 = vcpu->arch.cop0;
 883         long entryhi = kvm_read_c0_guest_entryhi(cop0);
 884         unsigned long pc = vcpu->arch.pc;
 885         int index = -1;
 886
 887         index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
 888
 889         kvm_write_c0_guest_index(cop0, index);
 890
 891         kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
 892                   index);
 893
 894         return EMULATE_DONE;
 895 }
 896
 897 /**
 898  * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
 899  * @vcpu:       Virtual CPU.
 900  *
 901  * Finds the mask of bits which are writable in the guest's Config1 CP0
 902  * register, by userland (currently read-only to the guest).
 903  */
 904 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
 905 {
 906         unsigned int mask = 0;
 907
 908         /* Permit FPU to be present if FPU is supported */
 909         if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
 910                 mask |= MIPS_CONF1_FP;
 911
 912         return mask;
 913 }
 914
 915 /**
 916  * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
 917  * @vcpu:       Virtual CPU.
 918  *
 919  * Finds the mask of bits which are writable in the guest's Config3 CP0
 920  * register, by userland (currently read-only to the guest).
 921  */
 922 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
 923 {
 924         /* Config4 is optional */
 925         unsigned int mask = MIPS_CONF_M;
 926
 927         /* Permit MSA to be present if MSA is supported */
 928         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 929                 mask |= MIPS_CONF3_MSA;
 930
 931         return mask;
 932 }
 933
 934 /**
 935  * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
 936  * @vcpu:       Virtual CPU.
 937  *
 938  * Finds the mask of bits which are writable in the guest's Config4 CP0
 939  * register, by userland (currently read-only to the guest).
 940  */
 941 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
 942 {
 943         /* Config5 is optional */
 944         return MIPS_CONF_M;
 945 }
 946
 947 /**
 948  * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
 949  * @vcpu:       Virtual CPU.
 950  *
 951  * Finds the mask of bits which are writable in the guest's Config5 CP0
 952  * register, by the guest itself.
 953  */
 954 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
 955 {
 956         unsigned int mask = 0;
 957
 958         /* Permit MSAEn changes if MSA supported and enabled */
 959         if (kvm_mips_guest_has_msa(&vcpu->arch))
 960                 mask |= MIPS_CONF5_MSAEN;
 961
 962         /*
 963          * Permit guest FPU mode changes if FPU is enabled and the relevant
 964          * feature exists according to FIR register.
 965          */
 966         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
 967                 if (cpu_has_fre)
 968                         mask |= MIPS_CONF5_FRE;
 969                 /* We don't support UFR or UFE */
 970         }
 971
 972         return mask;
 973 }
 974
 975 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
 976                                            u32 *opc, u32 cause,
 977                                            struct kvm_run *run,
 978                                            struct kvm_vcpu *vcpu)
 979 {
 980         struct mips_coproc *cop0 = vcpu->arch.cop0;
 981         enum emulation_result er = EMULATE_DONE;
 982         u32 rt, rd, sel;
 983         unsigned long curr_pc;
 984
 985         /*
 986          * Update PC and hold onto current PC in case there is
 987          * an error and we want to rollback the PC
 988          */
 989         curr_pc = vcpu->arch.pc;
 990         er = update_pc(vcpu, cause);
 991         if (er == EMULATE_FAIL)
 992                 return er;
 993
 994         if (inst.co_format.co) {
 995                 switch (inst.co_format.func) {
 996                 case tlbr_op:   /*  Read indexed TLB entry  */
 997                         er = kvm_mips_emul_tlbr(vcpu);
 998                         break;
 999                 case tlbwi_op:  /*  Write indexed  */
1000                         er = kvm_mips_emul_tlbwi(vcpu);
1001                         break;
1002                 case tlbwr_op:  /*  Write random  */
1003                         er = kvm_mips_emul_tlbwr(vcpu);
1004                         break;
1005                 case tlbp_op:   /* TLB Probe */
1006                         er = kvm_mips_emul_tlbp(vcpu);
1007                         break;
1008                 case rfe_op:
1009                         kvm_err("!!!COP0_RFE!!!\n");
1010                         break;
1011                 case eret_op:
1012                         er = kvm_mips_emul_eret(vcpu);
1013                         goto dont_update_pc;
1014                 case wait_op:
1015                         er = kvm_mips_emul_wait(vcpu);
1016                         break;
1017                 }
1018         } else {
1019                 rt = inst.c0r_format.rt;
1020                 rd = inst.c0r_format.rd;
1021                 sel = inst.c0r_format.sel;
1022
1023                 switch (inst.c0r_format.rs) {
1024                 case mfc_op:
1025 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1026                         cop0->stat[rd][sel]++;
1027 #endif
1028                         /* Get reg */
1029                         if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1030                                 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1031                         } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1032                                 vcpu->arch.gprs[rt] = 0x0;
1033 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1034                                 kvm_mips_trans_mfc0(inst, opc, vcpu);
1035 #endif
1036                         } else {
1037                                 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1038
1039 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1040                                 kvm_mips_trans_mfc0(inst, opc, vcpu);
1041 #endif
1042                         }
1043
1044                         trace_kvm_hwr(vcpu, KVM_TRACE_MFC0,
1045                                       KVM_TRACE_COP0(rd, sel),
1046                                       vcpu->arch.gprs[rt]);
1047                         break;
1048
1049                 case dmfc_op:
1050                         vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1051
1052                         trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0,
1053                                       KVM_TRACE_COP0(rd, sel),
1054                                       vcpu->arch.gprs[rt]);
1055                         break;
1056
1057                 case mtc_op:
1058 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1059                         cop0->stat[rd][sel]++;
1060 #endif
1061                         trace_kvm_hwr(vcpu, KVM_TRACE_MTC0,
1062                                       KVM_TRACE_COP0(rd, sel),
1063                                       vcpu->arch.gprs[rt]);
1064
1065                         if ((rd == MIPS_CP0_TLB_INDEX)
1066                             && (vcpu->arch.gprs[rt] >=
1067                                 KVM_MIPS_GUEST_TLB_SIZE)) {
1068                                 kvm_err("Invalid TLB Index: %ld",
1069                                         vcpu->arch.gprs[rt]);
1070                                 er = EMULATE_FAIL;
1071                                 break;
1072                         }
1073 #define C0_EBASE_CORE_MASK 0xff
1074                         if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1075                                 /* Preserve CORE number */
1076                                 kvm_change_c0_guest_ebase(cop0,
1077                                                           ~(C0_EBASE_CORE_MASK),
1078                                                           vcpu->arch.gprs[rt]);
1079                                 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1080                                         kvm_read_c0_guest_ebase(cop0));
1081                         } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1082                                 u32 nasid =
1083                                         vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID;
1084                                 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1085                                     ((kvm_read_c0_guest_entryhi(cop0) &
1086                                       KVM_ENTRYHI_ASID) != nasid)) {
1087                                         trace_kvm_asid_change(vcpu,
1088                                                 kvm_read_c0_guest_entryhi(cop0)
1089                                                         & KVM_ENTRYHI_ASID,
1090                                                 nasid);
1091
1092                                         /* Blow away the shadow host TLBs */
1093                                         kvm_mips_flush_host_tlb(1);
1094                                 }
1095                                 kvm_write_c0_guest_entryhi(cop0,
1096                                                            vcpu->arch.gprs[rt]);
1097                         }
1098                         /* Are we writing to COUNT */
1099                         else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1100                                 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1101                                 goto done;
1102                         } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1103                                 /* If we are writing to COMPARE */
1104                                 /* Clear pending timer interrupt, if any */
1105                                 kvm_mips_write_compare(vcpu,
1106                                                        vcpu->arch.gprs[rt],
1107                                                        true);
1108                         } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1109                                 unsigned int old_val, val, change;
1110
1111                                 old_val = kvm_read_c0_guest_status(cop0);
1112                                 val = vcpu->arch.gprs[rt];
1113                                 change = val ^ old_val;
1114
1115                                 /* Make sure that the NMI bit is never set */
1116                                 val &= ~ST0_NMI;
1117
1118                                 /*
1119                                  * Don't allow CU1 or FR to be set unless FPU
1120                                  * capability enabled and exists in guest
1121                                  * configuration.
1122                                  */
1123                                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1124                                         val &= ~(ST0_CU1 | ST0_FR);
1125
1126                                 /*
1127                                  * Also don't allow FR to be set if host doesn't
1128                                  * support it.
1129                                  */
1130                                 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1131                                         val &= ~ST0_FR;
1132
1133
1134                                 /* Handle changes in FPU mode */
1135                                 preempt_disable();
1136
1137                                 /*
1138                                  * FPU and Vector register state is made
1139                                  * UNPREDICTABLE by a change of FR, so don't
1140                                  * even bother saving it.
1141                                  */
1142                                 if (change & ST0_FR)
1143                                         kvm_drop_fpu(vcpu);
1144
1145                                 /*
1146                                  * If MSA state is already live, it is undefined
1147                                  * how it interacts with FR=0 FPU state, and we
1148                                  * don't want to hit reserved instruction
1149                                  * exceptions trying to save the MSA state later
1150                                  * when CU=1 && FR=1, so play it safe and save
1151                                  * it first.
1152                                  */
1153                                 if (change & ST0_CU1 && !(val & ST0_FR) &&
1154                                     vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1155                                         kvm_lose_fpu(vcpu);
1156
1157                                 /*
1158                                  * Propagate CU1 (FPU enable) changes
1159                                  * immediately if the FPU context is already
1160                                  * loaded. When disabling we leave the context
1161                                  * loaded so it can be quickly enabled again in
1162                                  * the near future.
1163                                  */
1164                                 if (change & ST0_CU1 &&
1165                                     vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1166                                         change_c0_status(ST0_CU1, val);
1167
1168                                 preempt_enable();
1169
1170                                 kvm_write_c0_guest_status(cop0, val);
1171
1172 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1173                                 /*
1174                                  * If FPU present, we need CU1/FR bits to take
1175                                  * effect fairly soon.
1176                                  */
1177                                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1178                                         kvm_mips_trans_mtc0(inst, opc, vcpu);
1179 #endif
1180                         } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1181                                 unsigned int old_val, val, change, wrmask;
1182
1183                                 old_val = kvm_read_c0_guest_config5(cop0);
1184                                 val = vcpu->arch.gprs[rt];
1185
1186                                 /* Only a few bits are writable in Config5 */
1187                                 wrmask = kvm_mips_config5_wrmask(vcpu);
1188                                 change = (val ^ old_val) & wrmask;
1189                                 val = old_val ^ change;
1190
1191
1192                                 /* Handle changes in FPU/MSA modes */
1193                                 preempt_disable();
1194
1195                                 /*
1196                                  * Propagate FRE changes immediately if the FPU
1197                                  * context is already loaded.
1198                                  */
1199                                 if (change & MIPS_CONF5_FRE &&
1200                                     vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
1201                                         change_c0_config5(MIPS_CONF5_FRE, val);
1202
1203                                 /*
1204                                  * Propagate MSAEn changes immediately if the
1205                                  * MSA context is already loaded. When disabling
1206                                  * we leave the context loaded so it can be
1207                                  * quickly enabled again in the near future.
1208                                  */
1209                                 if (change & MIPS_CONF5_MSAEN &&
1210                                     vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1211                                         change_c0_config5(MIPS_CONF5_MSAEN,
1212                                                           val);
1213
1214                                 preempt_enable();
1215
1216                                 kvm_write_c0_guest_config5(cop0, val);
1217                         } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1218                                 u32 old_cause, new_cause;
1219
1220                                 old_cause = kvm_read_c0_guest_cause(cop0);
1221                                 new_cause = vcpu->arch.gprs[rt];
1222                                 /* Update R/W bits */
1223                                 kvm_change_c0_guest_cause(cop0, 0x08800300,
1224                                                           new_cause);
1225                                 /* DC bit enabling/disabling timer? */
1226                                 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1227                                         if (new_cause & CAUSEF_DC)
1228                                                 kvm_mips_count_disable_cause(vcpu);
1229                                         else
1230                                                 kvm_mips_count_enable_cause(vcpu);
1231                                 }
1232                         } else {
1233                                 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1234 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1235                                 kvm_mips_trans_mtc0(inst, opc, vcpu);
1236 #endif
1237                         }
1238                         break;
1239
1240                 case dmtc_op:
1241                         kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1242                                 vcpu->arch.pc, rt, rd, sel);
1243                         trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0,
1244                                       KVM_TRACE_COP0(rd, sel),
1245                                       vcpu->arch.gprs[rt]);
1246                         er = EMULATE_FAIL;
1247                         break;
1248
1249                 case mfmc0_op:
1250 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1251                         cop0->stat[MIPS_CP0_STATUS][0]++;
1252 #endif
1253                         if (rt != 0)
1254                                 vcpu->arch.gprs[rt] =
1255                                     kvm_read_c0_guest_status(cop0);
1256                         /* EI */
1257                         if (inst.mfmc0_format.sc) {
1258                                 kvm_debug("[%#lx] mfmc0_op: EI\n",
1259                                           vcpu->arch.pc);
1260                                 kvm_set_c0_guest_status(cop0, ST0_IE);
1261                         } else {
1262                                 kvm_debug("[%#lx] mfmc0_op: DI\n",
1263                                           vcpu->arch.pc);
1264                                 kvm_clear_c0_guest_status(cop0, ST0_IE);
1265                         }
1266
1267                         break;
1268
1269                 case wrpgpr_op:
1270                         {
1271                                 u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1272                                 u32 pss =
1273                                     (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1274                                 /*
1275                                  * We don't support any shadow register sets, so
1276                                  * SRSCtl[PSS] == SRSCtl[CSS] = 0
1277                                  */
1278                                 if (css || pss) {
1279                                         er = EMULATE_FAIL;
1280                                         break;
1281                                 }
1282                                 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1283                                           vcpu->arch.gprs[rt]);
1284                                 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1285                         }
1286                         break;
1287                 default:
1288                         kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1289                                 vcpu->arch.pc, inst.c0r_format.rs);
1290                         er = EMULATE_FAIL;
1291                         break;
1292                 }
1293         }
1294
1295 done:
1296         /* Rollback PC only if emulation was unsuccessful */
1297         if (er == EMULATE_FAIL)
1298                 vcpu->arch.pc = curr_pc;
1299
1300 dont_update_pc:
1301         /*
1302          * This is for special instructions whose emulation
1303          * updates the PC, so do not overwrite the PC under
1304          * any circumstances
1305          */
1306
1307         return er;
1308 }
1309
1310 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
1311                                              u32 cause,
1312                                              struct kvm_run *run,
1313                                              struct kvm_vcpu *vcpu)
1314 {
1315         enum emulation_result er = EMULATE_DO_MMIO;
1316         u32 rt;
1317         u32 bytes;
1318         void *data = run->mmio.data;
1319         unsigned long curr_pc;
1320
1321         /*
1322          * Update PC and hold onto current PC in case there is
1323          * an error and we want to rollback the PC
1324          */
1325         curr_pc = vcpu->arch.pc;
1326         er = update_pc(vcpu, cause);
1327         if (er == EMULATE_FAIL)
1328                 return er;
1329
1330         rt = inst.i_format.rt;
1331
1332         switch (inst.i_format.opcode) {
1333         case sb_op:
1334                 bytes = 1;
1335                 if (bytes > sizeof(run->mmio.data)) {
1336                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1337                                run->mmio.len);
1338                 }
1339                 run->mmio.phys_addr =
1340                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1341                                                    host_cp0_badvaddr);
1342                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1343                         er = EMULATE_FAIL;
1344                         break;
1345                 }
1346                 run->mmio.len = bytes;
1347                 run->mmio.is_write = 1;
1348                 vcpu->mmio_needed = 1;
1349                 vcpu->mmio_is_write = 1;
1350                 *(u8 *) data = vcpu->arch.gprs[rt];
1351                 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1352                           vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1353                           *(u8 *) data);
1354
1355                 break;
1356
1357         case sw_op:
1358                 bytes = 4;
1359                 if (bytes > sizeof(run->mmio.data)) {
1360                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1361                                run->mmio.len);
1362                 }
1363                 run->mmio.phys_addr =
1364                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1365                                                    host_cp0_badvaddr);
1366                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1367                         er = EMULATE_FAIL;
1368                         break;
1369                 }
1370
1371                 run->mmio.len = bytes;
1372                 run->mmio.is_write = 1;
1373                 vcpu->mmio_needed = 1;
1374                 vcpu->mmio_is_write = 1;
1375                 *(u32 *) data = vcpu->arch.gprs[rt];
1376
1377                 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1378                           vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1379                           vcpu->arch.gprs[rt], *(u32 *) data);
1380                 break;
1381
1382         case sh_op:
1383                 bytes = 2;
1384                 if (bytes > sizeof(run->mmio.data)) {
1385                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1386                                run->mmio.len);
1387                 }
1388                 run->mmio.phys_addr =
1389                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1390                                                    host_cp0_badvaddr);
1391                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1392                         er = EMULATE_FAIL;
1393                         break;
1394                 }
1395
1396                 run->mmio.len = bytes;
1397                 run->mmio.is_write = 1;
1398                 vcpu->mmio_needed = 1;
1399                 vcpu->mmio_is_write = 1;
1400                 *(u16 *) data = vcpu->arch.gprs[rt];
1401
1402                 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1403                           vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1404                           vcpu->arch.gprs[rt], *(u32 *) data);
1405                 break;
1406
1407         default:
1408                 kvm_err("Store not yet supported (inst=0x%08x)\n",
1409                         inst.word);
1410                 er = EMULATE_FAIL;
1411                 break;
1412         }
1413
1414         /* Rollback PC if emulation was unsuccessful */
1415         if (er == EMULATE_FAIL)
1416                 vcpu->arch.pc = curr_pc;
1417
1418         return er;
1419 }
1420
1421 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
1422                                             u32 cause, struct kvm_run *run,
1423                                             struct kvm_vcpu *vcpu)
1424 {
1425         enum emulation_result er = EMULATE_DO_MMIO;
1426         u32 op, rt;
1427         u32 bytes;
1428
1429         rt = inst.i_format.rt;
1430         op = inst.i_format.opcode;
1431
1432         vcpu->arch.pending_load_cause = cause;
1433         vcpu->arch.io_gpr = rt;
1434
1435         switch (op) {
1436         case lw_op:
1437                 bytes = 4;
1438                 if (bytes > sizeof(run->mmio.data)) {
1439                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1440                                run->mmio.len);
1441                         er = EMULATE_FAIL;
1442                         break;
1443                 }
1444                 run->mmio.phys_addr =
1445                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1446                                                    host_cp0_badvaddr);
1447                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1448                         er = EMULATE_FAIL;
1449                         break;
1450                 }
1451
1452                 run->mmio.len = bytes;
1453                 run->mmio.is_write = 0;
1454                 vcpu->mmio_needed = 1;
1455                 vcpu->mmio_is_write = 0;
1456                 break;
1457
1458         case lh_op:
1459         case lhu_op:
1460                 bytes = 2;
1461                 if (bytes > sizeof(run->mmio.data)) {
1462                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1463                                run->mmio.len);
1464                         er = EMULATE_FAIL;
1465                         break;
1466                 }
1467                 run->mmio.phys_addr =
1468                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1469                                                    host_cp0_badvaddr);
1470                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1471                         er = EMULATE_FAIL;
1472                         break;
1473                 }
1474
1475                 run->mmio.len = bytes;
1476                 run->mmio.is_write = 0;
1477                 vcpu->mmio_needed = 1;
1478                 vcpu->mmio_is_write = 0;
1479
1480                 if (op == lh_op)
1481                         vcpu->mmio_needed = 2;
1482                 else
1483                         vcpu->mmio_needed = 1;
1484
1485                 break;
1486
1487         case lbu_op:
1488         case lb_op:
1489                 bytes = 1;
1490                 if (bytes > sizeof(run->mmio.data)) {
1491                         kvm_err("%s: bad MMIO length: %d\n", __func__,
1492                                run->mmio.len);
1493                         er = EMULATE_FAIL;
1494                         break;
1495                 }
1496                 run->mmio.phys_addr =
1497                     kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1498                                                    host_cp0_badvaddr);
1499                 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1500                         er = EMULATE_FAIL;
1501                         break;
1502                 }
1503
1504                 run->mmio.len = bytes;
1505                 run->mmio.is_write = 0;
1506                 vcpu->mmio_is_write = 0;
1507
1508                 if (op == lb_op)
1509                         vcpu->mmio_needed = 2;
1510                 else
1511                         vcpu->mmio_needed = 1;
1512
1513                 break;
1514
1515         default:
1516                 kvm_err("Load not yet supported (inst=0x%08x)\n",
1517                         inst.word);
1518                 er = EMULATE_FAIL;
1519                 break;
1520         }
1521
1522         return er;
1523 }
1524
1525 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
1526                                              u32 *opc, u32 cause,
1527                                              struct kvm_run *run,
1528                                              struct kvm_vcpu *vcpu)
1529 {
1530         struct mips_coproc *cop0 = vcpu->arch.cop0;
1531         enum emulation_result er = EMULATE_DONE;
1532         u32 cache, op_inst, op, base;
1533         s16 offset;
1534         struct kvm_vcpu_arch *arch = &vcpu->arch;
1535         unsigned long va;
1536         unsigned long curr_pc;
1537
1538         /*
1539          * Update PC and hold onto current PC in case there is
1540          * an error and we want to rollback the PC
1541          */
1542         curr_pc = vcpu->arch.pc;
1543         er = update_pc(vcpu, cause);
1544         if (er == EMULATE_FAIL)
1545                 return er;
1546
1547         base = inst.i_format.rs;
1548         op_inst = inst.i_format.rt;
1549         offset = inst.i_format.simmediate;
1550         cache = op_inst & CacheOp_Cache;
1551         op = op_inst & CacheOp_Op;
1552
1553         va = arch->gprs[base] + offset;
1554
1555         kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1556                   cache, op, base, arch->gprs[base], offset);
1557
1558         /*
1559          * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1560          * invalidate the caches entirely by stepping through all the
1561          * ways/indexes
1562          */
1563         if (op == Index_Writeback_Inv) {
1564                 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1565                           vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1566                           arch->gprs[base], offset);
1567
1568                 if (cache == Cache_D)
1569                         r4k_blast_dcache();
1570                 else if (cache == Cache_I)
1571                         r4k_blast_icache();
1572                 else {
1573                         kvm_err("%s: unsupported CACHE INDEX operation\n",
1574                                 __func__);
1575                         return EMULATE_FAIL;
1576                 }
1577
1578 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1579                 kvm_mips_trans_cache_index(inst, opc, vcpu);
1580 #endif
1581                 goto done;
1582         }
1583
1584         preempt_disable();
1585         if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1586                 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0)
1587                         kvm_mips_handle_kseg0_tlb_fault(va, vcpu);
1588         } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1589                    KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1590                 int index;
1591
1592                 /* If an entry already exists then skip */
1593                 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1594                         goto skip_fault;
1595
1596                 /*
1597                  * If address not in the guest TLB, then give the guest a fault,
1598                  * the resulting handler will do the right thing
1599                  */
1600                 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1601                                                   (kvm_read_c0_guest_entryhi
1602                                                    (cop0) & KVM_ENTRYHI_ASID));
1603
1604                 if (index < 0) {
1605                         vcpu->arch.host_cp0_badvaddr = va;
1606                         vcpu->arch.pc = curr_pc;
1607                         er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1608                                                          vcpu);
1609                         preempt_enable();
1610                         goto dont_update_pc;
1611                 } else {
1612                         struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1613                         /*
1614                          * Check if the entry is valid, if not then setup a TLB
1615                          * invalid exception to the guest
1616                          */
1617                         if (!TLB_IS_VALID(*tlb, va)) {
1618                                 vcpu->arch.host_cp0_badvaddr = va;
1619                                 vcpu->arch.pc = curr_pc;
1620                                 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1621                                                                 run, vcpu);
1622                                 preempt_enable();
1623                                 goto dont_update_pc;
1624                         } else {
1625                                 /*
1626                                  * We fault an entry from the guest tlb to the
1627                                  * shadow host TLB
1628                                  */
1629                                 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb);
1630                         }
1631                 }
1632         } else {
1633                 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1634                         cache, op, base, arch->gprs[base], offset);
1635                 er = EMULATE_FAIL;
1636                 preempt_enable();
1637                 goto done;
1638
1639         }
1640
1641 skip_fault:
1642         /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1643         if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
1644                 flush_dcache_line(va);
1645
1646 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1647                 /*
1648                  * Replace the CACHE instruction, with a SYNCI, not the same,
1649                  * but avoids a trap
1650                  */
1651                 kvm_mips_trans_cache_va(inst, opc, vcpu);
1652 #endif
1653         } else if (op_inst == Hit_Invalidate_I) {
1654                 flush_dcache_line(va);
1655                 flush_icache_line(va);
1656
1657 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1658                 /* Replace the CACHE instruction, with a SYNCI */
1659                 kvm_mips_trans_cache_va(inst, opc, vcpu);
1660 #endif
1661         } else {
1662                 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1663                         cache, op, base, arch->gprs[base], offset);
1664                 er = EMULATE_FAIL;
1665         }
1666
1667         preempt_enable();
1668 done:
1669         /* Rollback PC only if emulation was unsuccessful */
1670         if (er == EMULATE_FAIL)
1671                 vcpu->arch.pc = curr_pc;
1672
1673 dont_update_pc:
1674         /*
1675          * This is for exceptions whose emulation updates the PC, so do not
1676          * overwrite the PC under any circumstances
1677          */
1678
1679         return er;
1680 }
1681
1682 enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
1683                                             struct kvm_run *run,
1684                                             struct kvm_vcpu *vcpu)
1685 {
1686         union mips_instruction inst;
1687         enum emulation_result er = EMULATE_DONE;
1688
1689         /* Fetch the instruction. */
1690         if (cause & CAUSEF_BD)
1691                 opc += 1;
1692
1693         inst.word = kvm_get_inst(opc, vcpu);
1694
1695         switch (inst.r_format.opcode) {
1696         case cop0_op:
1697                 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1698                 break;
1699         case sb_op:
1700         case sh_op:
1701         case sw_op:
1702                 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1703                 break;
1704         case lb_op:
1705         case lbu_op:
1706         case lhu_op:
1707         case lh_op:
1708         case lw_op:
1709                 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1710                 break;
1711
1712         case cache_op:
1713                 ++vcpu->stat.cache_exits;
1714                 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
1715                 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1716                 break;
1717
1718         default:
1719                 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1720                         inst.word);
1721                 kvm_arch_vcpu_dump_regs(vcpu);
1722                 er = EMULATE_FAIL;
1723                 break;
1724         }
1725
1726         return er;
1727 }
1728
1729 enum emulation_result kvm_mips_emulate_syscall(u32 cause,
1730                                                u32 *opc,
1731                                                struct kvm_run *run,
1732                                                struct kvm_vcpu *vcpu)
1733 {
1734         struct mips_coproc *cop0 = vcpu->arch.cop0;
1735         struct kvm_vcpu_arch *arch = &vcpu->arch;
1736         enum emulation_result er = EMULATE_DONE;
1737
1738         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1739                 /* save old pc */
1740                 kvm_write_c0_guest_epc(cop0, arch->pc);
1741                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1742
1743                 if (cause & CAUSEF_BD)
1744                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1745                 else
1746                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1747
1748                 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1749
1750                 kvm_change_c0_guest_cause(cop0, (0xff),
1751                                           (EXCCODE_SYS << CAUSEB_EXCCODE));
1752
1753                 /* Set PC to the exception entry point */
1754                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1755
1756         } else {
1757                 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1758                 er = EMULATE_FAIL;
1759         }
1760
1761         return er;
1762 }
1763
1764 enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
1765                                                   u32 *opc,
1766                                                   struct kvm_run *run,
1767                                                   struct kvm_vcpu *vcpu)
1768 {
1769         struct mips_coproc *cop0 = vcpu->arch.cop0;
1770         struct kvm_vcpu_arch *arch = &vcpu->arch;
1771         unsigned long entryhi = (vcpu->arch.  host_cp0_badvaddr & VPN2_MASK) |
1772                         (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1773
1774         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1775                 /* save old pc */
1776                 kvm_write_c0_guest_epc(cop0, arch->pc);
1777                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1778
1779                 if (cause & CAUSEF_BD)
1780                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1781                 else
1782                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1783
1784                 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1785                           arch->pc);
1786
1787                 /* set pc to the exception entry point */
1788                 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1789
1790         } else {
1791                 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1792                           arch->pc);
1793
1794                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1795         }
1796
1797         kvm_change_c0_guest_cause(cop0, (0xff),
1798                                   (EXCCODE_TLBL << CAUSEB_EXCCODE));
1799
1800         /* setup badvaddr, context and entryhi registers for the guest */
1801         kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1802         /* XXXKYMA: is the context register used by linux??? */
1803         kvm_write_c0_guest_entryhi(cop0, entryhi);
1804         /* Blow away the shadow host TLBs */
1805         kvm_mips_flush_host_tlb(1);
1806
1807         return EMULATE_DONE;
1808 }
1809
1810 enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
1811                                                  u32 *opc,
1812                                                  struct kvm_run *run,
1813                                                  struct kvm_vcpu *vcpu)
1814 {
1815         struct mips_coproc *cop0 = vcpu->arch.cop0;
1816         struct kvm_vcpu_arch *arch = &vcpu->arch;
1817         unsigned long entryhi =
1818                 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1819                 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1820
1821         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1822                 /* save old pc */
1823                 kvm_write_c0_guest_epc(cop0, arch->pc);
1824                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1825
1826                 if (cause & CAUSEF_BD)
1827                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1828                 else
1829                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1830
1831                 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1832                           arch->pc);
1833
1834                 /* set pc to the exception entry point */
1835                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1836
1837         } else {
1838                 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1839                           arch->pc);
1840                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1841         }
1842
1843         kvm_change_c0_guest_cause(cop0, (0xff),
1844                                   (EXCCODE_TLBL << CAUSEB_EXCCODE));
1845
1846         /* setup badvaddr, context and entryhi registers for the guest */
1847         kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1848         /* XXXKYMA: is the context register used by linux??? */
1849         kvm_write_c0_guest_entryhi(cop0, entryhi);
1850         /* Blow away the shadow host TLBs */
1851         kvm_mips_flush_host_tlb(1);
1852
1853         return EMULATE_DONE;
1854 }
1855
1856 enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
1857                                                   u32 *opc,
1858                                                   struct kvm_run *run,
1859                                                   struct kvm_vcpu *vcpu)
1860 {
1861         struct mips_coproc *cop0 = vcpu->arch.cop0;
1862         struct kvm_vcpu_arch *arch = &vcpu->arch;
1863         unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1864                         (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1865
1866         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1867                 /* save old pc */
1868                 kvm_write_c0_guest_epc(cop0, arch->pc);
1869                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1870
1871                 if (cause & CAUSEF_BD)
1872                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1873                 else
1874                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1875
1876                 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1877                           arch->pc);
1878
1879                 /* Set PC to the exception entry point */
1880                 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1881         } else {
1882                 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1883                           arch->pc);
1884                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1885         }
1886
1887         kvm_change_c0_guest_cause(cop0, (0xff),
1888                                   (EXCCODE_TLBS << CAUSEB_EXCCODE));
1889
1890         /* setup badvaddr, context and entryhi registers for the guest */
1891         kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1892         /* XXXKYMA: is the context register used by linux??? */
1893         kvm_write_c0_guest_entryhi(cop0, entryhi);
1894         /* Blow away the shadow host TLBs */
1895         kvm_mips_flush_host_tlb(1);
1896
1897         return EMULATE_DONE;
1898 }
1899
1900 enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
1901                                                  u32 *opc,
1902                                                  struct kvm_run *run,
1903                                                  struct kvm_vcpu *vcpu)
1904 {
1905         struct mips_coproc *cop0 = vcpu->arch.cop0;
1906         struct kvm_vcpu_arch *arch = &vcpu->arch;
1907         unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1908                 (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1909
1910         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1911                 /* save old pc */
1912                 kvm_write_c0_guest_epc(cop0, arch->pc);
1913                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1914
1915                 if (cause & CAUSEF_BD)
1916                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1917                 else
1918                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1919
1920                 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1921                           arch->pc);
1922
1923                 /* Set PC to the exception entry point */
1924                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1925         } else {
1926                 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1927                           arch->pc);
1928                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1929         }
1930
1931         kvm_change_c0_guest_cause(cop0, (0xff),
1932                                   (EXCCODE_TLBS << CAUSEB_EXCCODE));
1933
1934         /* setup badvaddr, context and entryhi registers for the guest */
1935         kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1936         /* XXXKYMA: is the context register used by linux??? */
1937         kvm_write_c0_guest_entryhi(cop0, entryhi);
1938         /* Blow away the shadow host TLBs */
1939         kvm_mips_flush_host_tlb(1);
1940
1941         return EMULATE_DONE;
1942 }
1943
1944 /* TLBMOD: store into address matching TLB with Dirty bit off */
1945 enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc,
1946                                              struct kvm_run *run,
1947                                              struct kvm_vcpu *vcpu)
1948 {
1949         enum emulation_result er = EMULATE_DONE;
1950 #ifdef DEBUG
1951         struct mips_coproc *cop0 = vcpu->arch.cop0;
1952         unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1953                         (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1954         int index;
1955
1956         /* If address not in the guest TLB, then we are in trouble */
1957         index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
1958         if (index < 0) {
1959                 /* XXXKYMA Invalidate and retry */
1960                 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
1961                 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
1962                      __func__, entryhi);
1963                 kvm_mips_dump_guest_tlbs(vcpu);
1964                 kvm_mips_dump_host_tlbs();
1965                 return EMULATE_FAIL;
1966         }
1967 #endif
1968
1969         er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
1970         return er;
1971 }
1972
1973 enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
1974                                               u32 *opc,
1975                                               struct kvm_run *run,
1976                                               struct kvm_vcpu *vcpu)
1977 {
1978         struct mips_coproc *cop0 = vcpu->arch.cop0;
1979         unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1980                         (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
1981         struct kvm_vcpu_arch *arch = &vcpu->arch;
1982
1983         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1984                 /* save old pc */
1985                 kvm_write_c0_guest_epc(cop0, arch->pc);
1986                 kvm_set_c0_guest_status(cop0, ST0_EXL);
1987
1988                 if (cause & CAUSEF_BD)
1989                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1990                 else
1991                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1992
1993                 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
1994                           arch->pc);
1995
1996                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1997         } else {
1998                 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
1999                           arch->pc);
2000                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2001         }
2002
2003         kvm_change_c0_guest_cause(cop0, (0xff),
2004                                   (EXCCODE_MOD << CAUSEB_EXCCODE));
2005
2006         /* setup badvaddr, context and entryhi registers for the guest */
2007         kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2008         /* XXXKYMA: is the context register used by linux??? */
2009         kvm_write_c0_guest_entryhi(cop0, entryhi);
2010         /* Blow away the shadow host TLBs */
2011         kvm_mips_flush_host_tlb(1);
2012
2013         return EMULATE_DONE;
2014 }
2015
2016 enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
2017                                                u32 *opc,
2018                                                struct kvm_run *run,
2019                                                struct kvm_vcpu *vcpu)
2020 {
2021         struct mips_coproc *cop0 = vcpu->arch.cop0;
2022         struct kvm_vcpu_arch *arch = &vcpu->arch;
2023
2024         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2025                 /* save old pc */
2026                 kvm_write_c0_guest_epc(cop0, arch->pc);
2027                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2028
2029                 if (cause & CAUSEF_BD)
2030                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2031                 else
2032                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2033
2034         }
2035
2036         arch->pc = KVM_GUEST_KSEG0 + 0x180;
2037
2038         kvm_change_c0_guest_cause(cop0, (0xff),
2039                                   (EXCCODE_CPU << CAUSEB_EXCCODE));
2040         kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2041
2042         return EMULATE_DONE;
2043 }
2044
2045 enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
2046                                               u32 *opc,
2047                                               struct kvm_run *run,
2048                                               struct kvm_vcpu *vcpu)
2049 {
2050         struct mips_coproc *cop0 = vcpu->arch.cop0;
2051         struct kvm_vcpu_arch *arch = &vcpu->arch;
2052         enum emulation_result er = EMULATE_DONE;
2053
2054         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2055                 /* save old pc */
2056                 kvm_write_c0_guest_epc(cop0, arch->pc);
2057                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2058
2059                 if (cause & CAUSEF_BD)
2060                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2061                 else
2062                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2063
2064                 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2065
2066                 kvm_change_c0_guest_cause(cop0, (0xff),
2067                                           (EXCCODE_RI << CAUSEB_EXCCODE));
2068
2069                 /* Set PC to the exception entry point */
2070                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2071
2072         } else {
2073                 kvm_err("Trying to deliver RI when EXL is already set\n");
2074                 er = EMULATE_FAIL;
2075         }
2076
2077         return er;
2078 }
2079
2080 enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
2081                                               u32 *opc,
2082                                               struct kvm_run *run,
2083                                               struct kvm_vcpu *vcpu)
2084 {
2085         struct mips_coproc *cop0 = vcpu->arch.cop0;
2086         struct kvm_vcpu_arch *arch = &vcpu->arch;
2087         enum emulation_result er = EMULATE_DONE;
2088
2089         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2090                 /* save old pc */
2091                 kvm_write_c0_guest_epc(cop0, arch->pc);
2092                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2093
2094                 if (cause & CAUSEF_BD)
2095                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2096                 else
2097                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2098
2099                 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2100
2101                 kvm_change_c0_guest_cause(cop0, (0xff),
2102                                           (EXCCODE_BP << CAUSEB_EXCCODE));
2103
2104                 /* Set PC to the exception entry point */
2105                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2106
2107         } else {
2108                 kvm_err("Trying to deliver BP when EXL is already set\n");
2109                 er = EMULATE_FAIL;
2110         }
2111
2112         return er;
2113 }
2114
2115 enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
2116                                                 u32 *opc,
2117                                                 struct kvm_run *run,
2118                                                 struct kvm_vcpu *vcpu)
2119 {
2120         struct mips_coproc *cop0 = vcpu->arch.cop0;
2121         struct kvm_vcpu_arch *arch = &vcpu->arch;
2122         enum emulation_result er = EMULATE_DONE;
2123
2124         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2125                 /* save old pc */
2126                 kvm_write_c0_guest_epc(cop0, arch->pc);
2127                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2128
2129                 if (cause & CAUSEF_BD)
2130                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2131                 else
2132                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2133
2134                 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2135
2136                 kvm_change_c0_guest_cause(cop0, (0xff),
2137                                           (EXCCODE_TR << CAUSEB_EXCCODE));
2138
2139                 /* Set PC to the exception entry point */
2140                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2141
2142         } else {
2143                 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2144                 er = EMULATE_FAIL;
2145         }
2146
2147         return er;
2148 }
2149
2150 enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
2151                                                   u32 *opc,
2152                                                   struct kvm_run *run,
2153                                                   struct kvm_vcpu *vcpu)
2154 {
2155         struct mips_coproc *cop0 = vcpu->arch.cop0;
2156         struct kvm_vcpu_arch *arch = &vcpu->arch;
2157         enum emulation_result er = EMULATE_DONE;
2158
2159         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2160                 /* save old pc */
2161                 kvm_write_c0_guest_epc(cop0, arch->pc);
2162                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2163
2164                 if (cause & CAUSEF_BD)
2165                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2166                 else
2167                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2168
2169                 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2170
2171                 kvm_change_c0_guest_cause(cop0, (0xff),
2172                                           (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
2173
2174                 /* Set PC to the exception entry point */
2175                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2176
2177         } else {
2178                 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2179                 er = EMULATE_FAIL;
2180         }
2181
2182         return er;
2183 }
2184
2185 enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
2186                                                u32 *opc,
2187                                                struct kvm_run *run,
2188                                                struct kvm_vcpu *vcpu)
2189 {
2190         struct mips_coproc *cop0 = vcpu->arch.cop0;
2191         struct kvm_vcpu_arch *arch = &vcpu->arch;
2192         enum emulation_result er = EMULATE_DONE;
2193
2194         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2195                 /* save old pc */
2196                 kvm_write_c0_guest_epc(cop0, arch->pc);
2197                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2198
2199                 if (cause & CAUSEF_BD)
2200                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2201                 else
2202                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2203
2204                 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2205
2206                 kvm_change_c0_guest_cause(cop0, (0xff),
2207                                           (EXCCODE_FPE << CAUSEB_EXCCODE));
2208
2209                 /* Set PC to the exception entry point */
2210                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2211
2212         } else {
2213                 kvm_err("Trying to deliver FPE when EXL is already set\n");
2214                 er = EMULATE_FAIL;
2215         }
2216
2217         return er;
2218 }
2219
2220 enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
2221                                                   u32 *opc,
2222                                                   struct kvm_run *run,
2223                                                   struct kvm_vcpu *vcpu)
2224 {
2225         struct mips_coproc *cop0 = vcpu->arch.cop0;
2226         struct kvm_vcpu_arch *arch = &vcpu->arch;
2227         enum emulation_result er = EMULATE_DONE;
2228
2229         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2230                 /* save old pc */
2231                 kvm_write_c0_guest_epc(cop0, arch->pc);
2232                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2233
2234                 if (cause & CAUSEF_BD)
2235                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2236                 else
2237                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2238
2239                 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2240
2241                 kvm_change_c0_guest_cause(cop0, (0xff),
2242                                           (EXCCODE_MSADIS << CAUSEB_EXCCODE));
2243
2244                 /* Set PC to the exception entry point */
2245                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2246
2247         } else {
2248                 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2249                 er = EMULATE_FAIL;
2250         }
2251
2252         return er;
2253 }
2254
2255 enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
2256                                          struct kvm_run *run,
2257                                          struct kvm_vcpu *vcpu)
2258 {
2259         struct mips_coproc *cop0 = vcpu->arch.cop0;
2260         struct kvm_vcpu_arch *arch = &vcpu->arch;
2261         enum emulation_result er = EMULATE_DONE;
2262         unsigned long curr_pc;
2263         union mips_instruction inst;
2264
2265         /*
2266          * Update PC and hold onto current PC in case there is
2267          * an error and we want to rollback the PC
2268          */
2269         curr_pc = vcpu->arch.pc;
2270         er = update_pc(vcpu, cause);
2271         if (er == EMULATE_FAIL)
2272                 return er;
2273
2274         /* Fetch the instruction. */
2275         if (cause & CAUSEF_BD)
2276                 opc += 1;
2277
2278         inst.word = kvm_get_inst(opc, vcpu);
2279
2280         if (inst.word == KVM_INVALID_INST) {
2281                 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2282                 return EMULATE_FAIL;
2283         }
2284
2285         if (inst.r_format.opcode == spec3_op &&
2286             inst.r_format.func == rdhwr_op) {
2287                 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2288                 int rd = inst.r_format.rd;
2289                 int rt = inst.r_format.rt;
2290                 int sel = inst.r_format.re & 0x7;
2291
2292                 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2293                 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2294                         kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2295                                   rd, opc);
2296                         goto emulate_ri;
2297                 }
2298                 switch (rd) {
2299                 case MIPS_HWR_CPUNUM:           /* CPU number */
2300                         arch->gprs[rt] = 0;
2301                         break;
2302                 case MIPS_HWR_SYNCISTEP:        /* SYNCI length */
2303                         arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2304                                              current_cpu_data.icache.linesz);
2305                         break;
2306                 case MIPS_HWR_CC:               /* Read count register */
2307                         arch->gprs[rt] = kvm_mips_read_count(vcpu);
2308                         break;
2309                 case MIPS_HWR_CCRES:            /* Count register resolution */
2310                         switch (current_cpu_data.cputype) {
2311                         case CPU_20KC:
2312                         case CPU_25KF:
2313                                 arch->gprs[rt] = 1;
2314                                 break;
2315                         default:
2316                                 arch->gprs[rt] = 2;
2317                         }
2318                         break;
2319                 case MIPS_HWR_ULR:              /* Read UserLocal register */
2320                         arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2321                         break;
2322
2323                 default:
2324                         kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2325                         goto emulate_ri;
2326                 }
2327
2328                 trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
2329                               vcpu->arch.gprs[rt]);
2330         } else {
2331                 kvm_debug("Emulate RI not supported @ %p: %#x\n",
2332                           opc, inst.word);
2333                 goto emulate_ri;
2334         }
2335
2336         return EMULATE_DONE;
2337
2338 emulate_ri:
2339         /*
2340          * Rollback PC (if in branch delay slot then the PC already points to
2341          * branch target), and pass the RI exception to the guest OS.
2342          */
2343         vcpu->arch.pc = curr_pc;
2344         return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2345 }
2346
2347 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2348                                                   struct kvm_run *run)
2349 {
2350         unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2351         enum emulation_result er = EMULATE_DONE;
2352
2353         if (run->mmio.len > sizeof(*gpr)) {
2354                 kvm_err("Bad MMIO length: %d", run->mmio.len);
2355                 er = EMULATE_FAIL;
2356                 goto done;
2357         }
2358
2359         er = update_pc(vcpu, vcpu->arch.pending_load_cause);
2360         if (er == EMULATE_FAIL)
2361                 return er;
2362
2363         switch (run->mmio.len) {
2364         case 4:
2365                 *gpr = *(s32 *) run->mmio.data;
2366                 break;
2367
2368         case 2:
2369                 if (vcpu->mmio_needed == 2)
2370                         *gpr = *(s16 *) run->mmio.data;
2371                 else
2372                         *gpr = *(u16 *)run->mmio.data;
2373
2374                 break;
2375         case 1:
2376                 if (vcpu->mmio_needed == 2)
2377                         *gpr = *(s8 *) run->mmio.data;
2378                 else
2379                         *gpr = *(u8 *) run->mmio.data;
2380                 break;
2381         }
2382
2383         if (vcpu->arch.pending_load_cause & CAUSEF_BD)
2384                 kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n",
2385                           vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr,
2386                           vcpu->mmio_needed);
2387
2388 done:
2389         return er;
2390 }
2391
2392 static enum emulation_result kvm_mips_emulate_exc(u32 cause,
2393                                                   u32 *opc,
2394                                                   struct kvm_run *run,
2395                                                   struct kvm_vcpu *vcpu)
2396 {
2397         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2398         struct mips_coproc *cop0 = vcpu->arch.cop0;
2399         struct kvm_vcpu_arch *arch = &vcpu->arch;
2400         enum emulation_result er = EMULATE_DONE;
2401
2402         if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2403                 /* save old pc */
2404                 kvm_write_c0_guest_epc(cop0, arch->pc);
2405                 kvm_set_c0_guest_status(cop0, ST0_EXL);
2406
2407                 if (cause & CAUSEF_BD)
2408                         kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2409                 else
2410                         kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2411
2412                 kvm_change_c0_guest_cause(cop0, (0xff),
2413                                           (exccode << CAUSEB_EXCCODE));
2414
2415                 /* Set PC to the exception entry point */
2416                 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2417                 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2418
2419                 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2420                           exccode, kvm_read_c0_guest_epc(cop0),
2421                           kvm_read_c0_guest_badvaddr(cop0));
2422         } else {
2423                 kvm_err("Trying to deliver EXC when EXL is already set\n");
2424                 er = EMULATE_FAIL;
2425         }
2426
2427         return er;
2428 }
2429
2430 enum emulation_result kvm_mips_check_privilege(u32 cause,
2431                                                u32 *opc,
2432                                                struct kvm_run *run,
2433                                                struct kvm_vcpu *vcpu)
2434 {
2435         enum emulation_result er = EMULATE_DONE;
2436         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2437         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2438
2439         int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2440
2441         if (usermode) {
2442                 switch (exccode) {
2443                 case EXCCODE_INT:
2444                 case EXCCODE_SYS:
2445                 case EXCCODE_BP:
2446                 case EXCCODE_RI:
2447                 case EXCCODE_TR:
2448                 case EXCCODE_MSAFPE:
2449                 case EXCCODE_FPE:
2450                 case EXCCODE_MSADIS:
2451                         break;
2452
2453                 case EXCCODE_CPU:
2454                         if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2455                                 er = EMULATE_PRIV_FAIL;
2456                         break;
2457
2458                 case EXCCODE_MOD:
2459                         break;
2460
2461                 case EXCCODE_TLBL:
2462                         /*
2463                          * We we are accessing Guest kernel space, then send an
2464                          * address error exception to the guest
2465                          */
2466                         if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2467                                 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2468                                           badvaddr);
2469                                 cause &= ~0xff;
2470                                 cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
2471                                 er = EMULATE_PRIV_FAIL;
2472                         }
2473                         break;
2474
2475                 case EXCCODE_TLBS:
2476                         /*
2477                          * We we are accessing Guest kernel space, then send an
2478                          * address error exception to the guest
2479                          */
2480                         if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2481                                 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2482                                           badvaddr);
2483                                 cause &= ~0xff;
2484                                 cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
2485                                 er = EMULATE_PRIV_FAIL;
2486                         }
2487                         break;
2488
2489                 case EXCCODE_ADES:
2490                         kvm_debug("%s: address error ST @ %#lx\n", __func__,
2491                                   badvaddr);
2492                         if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2493                                 cause &= ~0xff;
2494                                 cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
2495                         }
2496                         er = EMULATE_PRIV_FAIL;
2497                         break;
2498                 case EXCCODE_ADEL:
2499                         kvm_debug("%s: address error LD @ %#lx\n", __func__,
2500                                   badvaddr);
2501                         if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2502                                 cause &= ~0xff;
2503                                 cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
2504                         }
2505                         er = EMULATE_PRIV_FAIL;
2506                         break;
2507                 default:
2508                         er = EMULATE_PRIV_FAIL;
2509                         break;
2510                 }
2511         }
2512
2513         if (er == EMULATE_PRIV_FAIL)
2514                 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2515
2516         return er;
2517 }
2518
2519 /*
2520  * User Address (UA) fault, this could happen if
2521  * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2522  *     case we pass on the fault to the guest kernel and let it handle it.
2523  * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2524  *     case we inject the TLB from the Guest TLB into the shadow host TLB
2525  */
2526 enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
2527                                               u32 *opc,
2528                                               struct kvm_run *run,
2529                                               struct kvm_vcpu *vcpu)
2530 {
2531         enum emulation_result er = EMULATE_DONE;
2532         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2533         unsigned long va = vcpu->arch.host_cp0_badvaddr;
2534         int index;
2535
2536         kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n",
2537                   vcpu->arch.host_cp0_badvaddr);
2538
2539         /*
2540          * KVM would not have got the exception if this entry was valid in the
2541          * shadow host TLB. Check the Guest TLB, if the entry is not there then
2542          * send the guest an exception. The guest exc handler should then inject
2543          * an entry into the guest TLB.
2544          */
2545         index = kvm_mips_guest_tlb_lookup(vcpu,
2546                       (va & VPN2_MASK) |
2547                       (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) &
2548                        KVM_ENTRYHI_ASID));
2549         if (index < 0) {
2550                 if (exccode == EXCCODE_TLBL) {
2551                         er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2552                 } else if (exccode == EXCCODE_TLBS) {
2553                         er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2554                 } else {
2555                         kvm_err("%s: invalid exc code: %d\n", __func__,
2556                                 exccode);
2557                         er = EMULATE_FAIL;
2558                 }
2559         } else {
2560                 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2561
2562                 /*
2563                  * Check if the entry is valid, if not then setup a TLB invalid
2564                  * exception to the guest
2565                  */
2566                 if (!TLB_IS_VALID(*tlb, va)) {
2567                         if (exccode == EXCCODE_TLBL) {
2568                                 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2569                                                                 vcpu);
2570                         } else if (exccode == EXCCODE_TLBS) {
2571                                 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2572                                                                 vcpu);
2573                         } else {
2574                                 kvm_err("%s: invalid exc code: %d\n", __func__,
2575                                         exccode);
2576                                 er = EMULATE_FAIL;
2577                         }
2578                 } else {
2579                         kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2580                                   tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);
2581                         /*
2582                          * OK we have a Guest TLB entry, now inject it into the
2583                          * shadow host TLB
2584                          */
2585                         kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb);
2586                 }
2587         }
2588
2589         return er;
2590 }