2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
88 #include <asm/debug.h>
90 #include <asm/fpu_emulator.h>
92 #include <asm/mmu_context.h>
93 #include <linux/uaccess.h>
95 #define STR(x) __STR(x)
99 UNALIGNED_ACTION_QUIET,
100 UNALIGNED_ACTION_SIGNAL,
101 UNALIGNED_ACTION_SHOW,
103 #ifdef CONFIG_DEBUG_FS
104 static u32 unaligned_instructions;
105 static u32 unaligned_action;
107 #define unaligned_action UNALIGNED_ACTION_QUIET
109 extern void show_registers(struct pt_regs *regs);
112 #define _LoadHW(addr, value, res, type) \
114 __asm__ __volatile__ (".set\tnoat\n" \
115 "1:\t"type##_lb("%0", "0(%2)")"\n" \
116 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
122 ".section\t.fixup,\"ax\"\n\t" \
123 "4:\tli\t%1, %3\n\t" \
126 ".section\t__ex_table,\"a\"\n\t" \
127 STR(PTR)"\t1b, 4b\n\t" \
128 STR(PTR)"\t2b, 4b\n\t" \
130 : "=&r" (value), "=r" (res) \
131 : "r" (addr), "i" (-EFAULT)); \
134 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
135 #define _LoadW(addr, value, res, type) \
137 __asm__ __volatile__ ( \
138 "1:\t"type##_lwl("%0", "(%2)")"\n" \
139 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
143 ".section\t.fixup,\"ax\"\n\t" \
144 "4:\tli\t%1, %3\n\t" \
147 ".section\t__ex_table,\"a\"\n\t" \
148 STR(PTR)"\t1b, 4b\n\t" \
149 STR(PTR)"\t2b, 4b\n\t" \
151 : "=&r" (value), "=r" (res) \
152 : "r" (addr), "i" (-EFAULT)); \
155 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
156 /* For CPUs without lwl instruction */
157 #define _LoadW(addr, value, res, type) \
159 __asm__ __volatile__ ( \
162 "1:"type##_lb("%0", "0(%2)")"\n\t" \
163 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
166 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
169 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
176 ".section\t.fixup,\"ax\"\n\t" \
177 "11:\tli\t%1, %3\n\t" \
180 ".section\t__ex_table,\"a\"\n\t" \
181 STR(PTR)"\t1b, 11b\n\t" \
182 STR(PTR)"\t2b, 11b\n\t" \
183 STR(PTR)"\t3b, 11b\n\t" \
184 STR(PTR)"\t4b, 11b\n\t" \
186 : "=&r" (value), "=r" (res) \
187 : "r" (addr), "i" (-EFAULT)); \
190 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
192 #define _LoadHWU(addr, value, res, type) \
194 __asm__ __volatile__ ( \
196 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
197 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
204 ".section\t.fixup,\"ax\"\n\t" \
205 "4:\tli\t%1, %3\n\t" \
208 ".section\t__ex_table,\"a\"\n\t" \
209 STR(PTR)"\t1b, 4b\n\t" \
210 STR(PTR)"\t2b, 4b\n\t" \
212 : "=&r" (value), "=r" (res) \
213 : "r" (addr), "i" (-EFAULT)); \
216 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
217 #define _LoadWU(addr, value, res, type) \
219 __asm__ __volatile__ ( \
220 "1:\t"type##_lwl("%0", "(%2)")"\n" \
221 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
222 "dsll\t%0, %0, 32\n\t" \
223 "dsrl\t%0, %0, 32\n\t" \
227 "\t.section\t.fixup,\"ax\"\n\t" \
228 "4:\tli\t%1, %3\n\t" \
231 ".section\t__ex_table,\"a\"\n\t" \
232 STR(PTR)"\t1b, 4b\n\t" \
233 STR(PTR)"\t2b, 4b\n\t" \
235 : "=&r" (value), "=r" (res) \
236 : "r" (addr), "i" (-EFAULT)); \
239 #define _LoadDW(addr, value, res) \
241 __asm__ __volatile__ ( \
242 "1:\tldl\t%0, (%2)\n" \
243 "2:\tldr\t%0, 7(%2)\n\t" \
247 "\t.section\t.fixup,\"ax\"\n\t" \
248 "4:\tli\t%1, %3\n\t" \
251 ".section\t__ex_table,\"a\"\n\t" \
252 STR(PTR)"\t1b, 4b\n\t" \
253 STR(PTR)"\t2b, 4b\n\t" \
255 : "=&r" (value), "=r" (res) \
256 : "r" (addr), "i" (-EFAULT)); \
259 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
260 /* For CPUs without lwl and ldl instructions */
261 #define _LoadWU(addr, value, res, type) \
263 __asm__ __volatile__ ( \
266 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
267 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
270 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
273 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
280 ".section\t.fixup,\"ax\"\n\t" \
281 "11:\tli\t%1, %3\n\t" \
284 ".section\t__ex_table,\"a\"\n\t" \
285 STR(PTR)"\t1b, 11b\n\t" \
286 STR(PTR)"\t2b, 11b\n\t" \
287 STR(PTR)"\t3b, 11b\n\t" \
288 STR(PTR)"\t4b, 11b\n\t" \
290 : "=&r" (value), "=r" (res) \
291 : "r" (addr), "i" (-EFAULT)); \
294 #define _LoadDW(addr, value, res) \
296 __asm__ __volatile__ ( \
299 "1:lb\t%0, 0(%2)\n\t" \
300 "2:lbu\t $1, 1(%2)\n\t" \
301 "dsll\t%0, 0x8\n\t" \
303 "3:lbu\t$1, 2(%2)\n\t" \
304 "dsll\t%0, 0x8\n\t" \
306 "4:lbu\t$1, 3(%2)\n\t" \
307 "dsll\t%0, 0x8\n\t" \
309 "5:lbu\t$1, 4(%2)\n\t" \
310 "dsll\t%0, 0x8\n\t" \
312 "6:lbu\t$1, 5(%2)\n\t" \
313 "dsll\t%0, 0x8\n\t" \
315 "7:lbu\t$1, 6(%2)\n\t" \
316 "dsll\t%0, 0x8\n\t" \
318 "8:lbu\t$1, 7(%2)\n\t" \
319 "dsll\t%0, 0x8\n\t" \
325 ".section\t.fixup,\"ax\"\n\t" \
326 "11:\tli\t%1, %3\n\t" \
329 ".section\t__ex_table,\"a\"\n\t" \
330 STR(PTR)"\t1b, 11b\n\t" \
331 STR(PTR)"\t2b, 11b\n\t" \
332 STR(PTR)"\t3b, 11b\n\t" \
333 STR(PTR)"\t4b, 11b\n\t" \
334 STR(PTR)"\t5b, 11b\n\t" \
335 STR(PTR)"\t6b, 11b\n\t" \
336 STR(PTR)"\t7b, 11b\n\t" \
337 STR(PTR)"\t8b, 11b\n\t" \
339 : "=&r" (value), "=r" (res) \
340 : "r" (addr), "i" (-EFAULT)); \
343 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
346 #define _StoreHW(addr, value, res, type) \
348 __asm__ __volatile__ ( \
350 "1:\t"type##_sb("%1", "1(%2)")"\n" \
351 "srl\t$1, %1, 0x8\n" \
352 "2:\t"type##_sb("$1", "0(%2)")"\n" \
357 ".section\t.fixup,\"ax\"\n\t" \
358 "4:\tli\t%0, %3\n\t" \
361 ".section\t__ex_table,\"a\"\n\t" \
362 STR(PTR)"\t1b, 4b\n\t" \
363 STR(PTR)"\t2b, 4b\n\t" \
366 : "r" (value), "r" (addr), "i" (-EFAULT));\
369 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
370 #define _StoreW(addr, value, res, type) \
372 __asm__ __volatile__ ( \
373 "1:\t"type##_swl("%1", "(%2)")"\n" \
374 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
378 ".section\t.fixup,\"ax\"\n\t" \
379 "4:\tli\t%0, %3\n\t" \
382 ".section\t__ex_table,\"a\"\n\t" \
383 STR(PTR)"\t1b, 4b\n\t" \
384 STR(PTR)"\t2b, 4b\n\t" \
387 : "r" (value), "r" (addr), "i" (-EFAULT)); \
390 #define _StoreDW(addr, value, res) \
392 __asm__ __volatile__ ( \
393 "1:\tsdl\t%1,(%2)\n" \
394 "2:\tsdr\t%1, 7(%2)\n\t" \
398 ".section\t.fixup,\"ax\"\n\t" \
399 "4:\tli\t%0, %3\n\t" \
402 ".section\t__ex_table,\"a\"\n\t" \
403 STR(PTR)"\t1b, 4b\n\t" \
404 STR(PTR)"\t2b, 4b\n\t" \
407 : "r" (value), "r" (addr), "i" (-EFAULT)); \
410 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
411 #define _StoreW(addr, value, res, type) \
413 __asm__ __volatile__ ( \
416 "1:"type##_sb("%1", "3(%2)")"\n\t" \
417 "srl\t$1, %1, 0x8\n\t" \
418 "2:"type##_sb("$1", "2(%2)")"\n\t" \
419 "srl\t$1, $1, 0x8\n\t" \
420 "3:"type##_sb("$1", "1(%2)")"\n\t" \
421 "srl\t$1, $1, 0x8\n\t" \
422 "4:"type##_sb("$1", "0(%2)")"\n\t" \
427 ".section\t.fixup,\"ax\"\n\t" \
428 "11:\tli\t%0, %3\n\t" \
431 ".section\t__ex_table,\"a\"\n\t" \
432 STR(PTR)"\t1b, 11b\n\t" \
433 STR(PTR)"\t2b, 11b\n\t" \
434 STR(PTR)"\t3b, 11b\n\t" \
435 STR(PTR)"\t4b, 11b\n\t" \
438 : "r" (value), "r" (addr), "i" (-EFAULT) \
442 #define _StoreDW(addr, value, res) \
444 __asm__ __volatile__ ( \
447 "1:sb\t%1, 7(%2)\n\t" \
448 "dsrl\t$1, %1, 0x8\n\t" \
449 "2:sb\t$1, 6(%2)\n\t" \
450 "dsrl\t$1, $1, 0x8\n\t" \
451 "3:sb\t$1, 5(%2)\n\t" \
452 "dsrl\t$1, $1, 0x8\n\t" \
453 "4:sb\t$1, 4(%2)\n\t" \
454 "dsrl\t$1, $1, 0x8\n\t" \
455 "5:sb\t$1, 3(%2)\n\t" \
456 "dsrl\t$1, $1, 0x8\n\t" \
457 "6:sb\t$1, 2(%2)\n\t" \
458 "dsrl\t$1, $1, 0x8\n\t" \
459 "7:sb\t$1, 1(%2)\n\t" \
460 "dsrl\t$1, $1, 0x8\n\t" \
461 "8:sb\t$1, 0(%2)\n\t" \
462 "dsrl\t$1, $1, 0x8\n\t" \
467 ".section\t.fixup,\"ax\"\n\t" \
468 "11:\tli\t%0, %3\n\t" \
471 ".section\t__ex_table,\"a\"\n\t" \
472 STR(PTR)"\t1b, 11b\n\t" \
473 STR(PTR)"\t2b, 11b\n\t" \
474 STR(PTR)"\t3b, 11b\n\t" \
475 STR(PTR)"\t4b, 11b\n\t" \
476 STR(PTR)"\t5b, 11b\n\t" \
477 STR(PTR)"\t6b, 11b\n\t" \
478 STR(PTR)"\t7b, 11b\n\t" \
479 STR(PTR)"\t8b, 11b\n\t" \
482 : "r" (value), "r" (addr), "i" (-EFAULT) \
486 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
488 #else /* __BIG_ENDIAN */
490 #define _LoadHW(addr, value, res, type) \
492 __asm__ __volatile__ (".set\tnoat\n" \
493 "1:\t"type##_lb("%0", "1(%2)")"\n" \
494 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
500 ".section\t.fixup,\"ax\"\n\t" \
501 "4:\tli\t%1, %3\n\t" \
504 ".section\t__ex_table,\"a\"\n\t" \
505 STR(PTR)"\t1b, 4b\n\t" \
506 STR(PTR)"\t2b, 4b\n\t" \
508 : "=&r" (value), "=r" (res) \
509 : "r" (addr), "i" (-EFAULT)); \
512 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
513 #define _LoadW(addr, value, res, type) \
515 __asm__ __volatile__ ( \
516 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
517 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
521 ".section\t.fixup,\"ax\"\n\t" \
522 "4:\tli\t%1, %3\n\t" \
525 ".section\t__ex_table,\"a\"\n\t" \
526 STR(PTR)"\t1b, 4b\n\t" \
527 STR(PTR)"\t2b, 4b\n\t" \
529 : "=&r" (value), "=r" (res) \
530 : "r" (addr), "i" (-EFAULT)); \
533 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
534 /* For CPUs without lwl instruction */
535 #define _LoadW(addr, value, res, type) \
537 __asm__ __volatile__ ( \
540 "1:"type##_lb("%0", "3(%2)")"\n\t" \
541 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
544 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
547 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
554 ".section\t.fixup,\"ax\"\n\t" \
555 "11:\tli\t%1, %3\n\t" \
558 ".section\t__ex_table,\"a\"\n\t" \
559 STR(PTR)"\t1b, 11b\n\t" \
560 STR(PTR)"\t2b, 11b\n\t" \
561 STR(PTR)"\t3b, 11b\n\t" \
562 STR(PTR)"\t4b, 11b\n\t" \
564 : "=&r" (value), "=r" (res) \
565 : "r" (addr), "i" (-EFAULT)); \
568 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
571 #define _LoadHWU(addr, value, res, type) \
573 __asm__ __volatile__ ( \
575 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
576 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
583 ".section\t.fixup,\"ax\"\n\t" \
584 "4:\tli\t%1, %3\n\t" \
587 ".section\t__ex_table,\"a\"\n\t" \
588 STR(PTR)"\t1b, 4b\n\t" \
589 STR(PTR)"\t2b, 4b\n\t" \
591 : "=&r" (value), "=r" (res) \
592 : "r" (addr), "i" (-EFAULT)); \
595 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
596 #define _LoadWU(addr, value, res, type) \
598 __asm__ __volatile__ ( \
599 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
600 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
601 "dsll\t%0, %0, 32\n\t" \
602 "dsrl\t%0, %0, 32\n\t" \
606 "\t.section\t.fixup,\"ax\"\n\t" \
607 "4:\tli\t%1, %3\n\t" \
610 ".section\t__ex_table,\"a\"\n\t" \
611 STR(PTR)"\t1b, 4b\n\t" \
612 STR(PTR)"\t2b, 4b\n\t" \
614 : "=&r" (value), "=r" (res) \
615 : "r" (addr), "i" (-EFAULT)); \
618 #define _LoadDW(addr, value, res) \
620 __asm__ __volatile__ ( \
621 "1:\tldl\t%0, 7(%2)\n" \
622 "2:\tldr\t%0, (%2)\n\t" \
626 "\t.section\t.fixup,\"ax\"\n\t" \
627 "4:\tli\t%1, %3\n\t" \
630 ".section\t__ex_table,\"a\"\n\t" \
631 STR(PTR)"\t1b, 4b\n\t" \
632 STR(PTR)"\t2b, 4b\n\t" \
634 : "=&r" (value), "=r" (res) \
635 : "r" (addr), "i" (-EFAULT)); \
638 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
639 /* For CPUs without lwl and ldl instructions */
640 #define _LoadWU(addr, value, res, type) \
642 __asm__ __volatile__ ( \
645 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
646 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
649 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
652 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
659 ".section\t.fixup,\"ax\"\n\t" \
660 "11:\tli\t%1, %3\n\t" \
663 ".section\t__ex_table,\"a\"\n\t" \
664 STR(PTR)"\t1b, 11b\n\t" \
665 STR(PTR)"\t2b, 11b\n\t" \
666 STR(PTR)"\t3b, 11b\n\t" \
667 STR(PTR)"\t4b, 11b\n\t" \
669 : "=&r" (value), "=r" (res) \
670 : "r" (addr), "i" (-EFAULT)); \
673 #define _LoadDW(addr, value, res) \
675 __asm__ __volatile__ ( \
678 "1:lb\t%0, 7(%2)\n\t" \
679 "2:lbu\t$1, 6(%2)\n\t" \
680 "dsll\t%0, 0x8\n\t" \
682 "3:lbu\t$1, 5(%2)\n\t" \
683 "dsll\t%0, 0x8\n\t" \
685 "4:lbu\t$1, 4(%2)\n\t" \
686 "dsll\t%0, 0x8\n\t" \
688 "5:lbu\t$1, 3(%2)\n\t" \
689 "dsll\t%0, 0x8\n\t" \
691 "6:lbu\t$1, 2(%2)\n\t" \
692 "dsll\t%0, 0x8\n\t" \
694 "7:lbu\t$1, 1(%2)\n\t" \
695 "dsll\t%0, 0x8\n\t" \
697 "8:lbu\t$1, 0(%2)\n\t" \
698 "dsll\t%0, 0x8\n\t" \
704 ".section\t.fixup,\"ax\"\n\t" \
705 "11:\tli\t%1, %3\n\t" \
708 ".section\t__ex_table,\"a\"\n\t" \
709 STR(PTR)"\t1b, 11b\n\t" \
710 STR(PTR)"\t2b, 11b\n\t" \
711 STR(PTR)"\t3b, 11b\n\t" \
712 STR(PTR)"\t4b, 11b\n\t" \
713 STR(PTR)"\t5b, 11b\n\t" \
714 STR(PTR)"\t6b, 11b\n\t" \
715 STR(PTR)"\t7b, 11b\n\t" \
716 STR(PTR)"\t8b, 11b\n\t" \
718 : "=&r" (value), "=r" (res) \
719 : "r" (addr), "i" (-EFAULT)); \
721 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
723 #define _StoreHW(addr, value, res, type) \
725 __asm__ __volatile__ ( \
727 "1:\t"type##_sb("%1", "0(%2)")"\n" \
728 "srl\t$1,%1, 0x8\n" \
729 "2:\t"type##_sb("$1", "1(%2)")"\n" \
734 ".section\t.fixup,\"ax\"\n\t" \
735 "4:\tli\t%0, %3\n\t" \
738 ".section\t__ex_table,\"a\"\n\t" \
739 STR(PTR)"\t1b, 4b\n\t" \
740 STR(PTR)"\t2b, 4b\n\t" \
743 : "r" (value), "r" (addr), "i" (-EFAULT));\
746 #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
747 #define _StoreW(addr, value, res, type) \
749 __asm__ __volatile__ ( \
750 "1:\t"type##_swl("%1", "3(%2)")"\n" \
751 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
755 ".section\t.fixup,\"ax\"\n\t" \
756 "4:\tli\t%0, %3\n\t" \
759 ".section\t__ex_table,\"a\"\n\t" \
760 STR(PTR)"\t1b, 4b\n\t" \
761 STR(PTR)"\t2b, 4b\n\t" \
764 : "r" (value), "r" (addr), "i" (-EFAULT)); \
767 #define _StoreDW(addr, value, res) \
769 __asm__ __volatile__ ( \
770 "1:\tsdl\t%1, 7(%2)\n" \
771 "2:\tsdr\t%1, (%2)\n\t" \
775 ".section\t.fixup,\"ax\"\n\t" \
776 "4:\tli\t%0, %3\n\t" \
779 ".section\t__ex_table,\"a\"\n\t" \
780 STR(PTR)"\t1b, 4b\n\t" \
781 STR(PTR)"\t2b, 4b\n\t" \
784 : "r" (value), "r" (addr), "i" (-EFAULT)); \
787 #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
788 /* For CPUs without swl and sdl instructions */
789 #define _StoreW(addr, value, res, type) \
791 __asm__ __volatile__ ( \
794 "1:"type##_sb("%1", "0(%2)")"\n\t" \
795 "srl\t$1, %1, 0x8\n\t" \
796 "2:"type##_sb("$1", "1(%2)")"\n\t" \
797 "srl\t$1, $1, 0x8\n\t" \
798 "3:"type##_sb("$1", "2(%2)")"\n\t" \
799 "srl\t$1, $1, 0x8\n\t" \
800 "4:"type##_sb("$1", "3(%2)")"\n\t" \
805 ".section\t.fixup,\"ax\"\n\t" \
806 "11:\tli\t%0, %3\n\t" \
809 ".section\t__ex_table,\"a\"\n\t" \
810 STR(PTR)"\t1b, 11b\n\t" \
811 STR(PTR)"\t2b, 11b\n\t" \
812 STR(PTR)"\t3b, 11b\n\t" \
813 STR(PTR)"\t4b, 11b\n\t" \
816 : "r" (value), "r" (addr), "i" (-EFAULT) \
820 #define _StoreDW(addr, value, res) \
822 __asm__ __volatile__ ( \
825 "1:sb\t%1, 0(%2)\n\t" \
826 "dsrl\t$1, %1, 0x8\n\t" \
827 "2:sb\t$1, 1(%2)\n\t" \
828 "dsrl\t$1, $1, 0x8\n\t" \
829 "3:sb\t$1, 2(%2)\n\t" \
830 "dsrl\t$1, $1, 0x8\n\t" \
831 "4:sb\t$1, 3(%2)\n\t" \
832 "dsrl\t$1, $1, 0x8\n\t" \
833 "5:sb\t$1, 4(%2)\n\t" \
834 "dsrl\t$1, $1, 0x8\n\t" \
835 "6:sb\t$1, 5(%2)\n\t" \
836 "dsrl\t$1, $1, 0x8\n\t" \
837 "7:sb\t$1, 6(%2)\n\t" \
838 "dsrl\t$1, $1, 0x8\n\t" \
839 "8:sb\t$1, 7(%2)\n\t" \
840 "dsrl\t$1, $1, 0x8\n\t" \
845 ".section\t.fixup,\"ax\"\n\t" \
846 "11:\tli\t%0, %3\n\t" \
849 ".section\t__ex_table,\"a\"\n\t" \
850 STR(PTR)"\t1b, 11b\n\t" \
851 STR(PTR)"\t2b, 11b\n\t" \
852 STR(PTR)"\t3b, 11b\n\t" \
853 STR(PTR)"\t4b, 11b\n\t" \
854 STR(PTR)"\t5b, 11b\n\t" \
855 STR(PTR)"\t6b, 11b\n\t" \
856 STR(PTR)"\t7b, 11b\n\t" \
857 STR(PTR)"\t8b, 11b\n\t" \
860 : "r" (value), "r" (addr), "i" (-EFAULT) \
864 #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
867 #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
868 #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
869 #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
870 #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
871 #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
872 #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
873 #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
874 #define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
875 #define LoadDW(addr, value, res) _LoadDW(addr, value, res)
877 #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
878 #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
879 #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
880 #define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
881 #define StoreDW(addr, value, res) _StoreDW(addr, value, res)
883 static void emulate_load_store_insn(struct pt_regs *regs,
884 void __user *addr, unsigned int __user *pc)
886 unsigned long origpc, orig31, value;
887 union mips_instruction insn;
892 origpc = (unsigned long)pc;
893 orig31 = regs->regs[31];
895 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
898 * This load never faults.
900 __get_user(insn.word, pc);
902 switch (insn.i_format.opcode) {
904 * These are instructions that a compiler doesn't generate. We
905 * can assume therefore that the code is MIPS-aware and
906 * really buggy. Emulating these instructions would break the
915 * For these instructions the only way to create an address
916 * error is an attempted access to kernel/supervisor address
933 * The remaining opcodes are the ones that are really of
937 if (insn.dsp_format.func == lx_op) {
938 switch (insn.dsp_format.op) {
940 if (!access_ok(addr, 4))
942 LoadW(addr, value, res);
945 compute_return_epc(regs);
946 regs->regs[insn.dsp_format.rd] = value;
949 if (!access_ok(addr, 2))
951 LoadHW(addr, value, res);
954 compute_return_epc(regs);
955 regs->regs[insn.dsp_format.rd] = value;
964 * we can land here only from kernel accessing user
965 * memory, so we need to "switch" the address limit to
966 * user space, so that address check can work properly.
970 switch (insn.spec3_format.func) {
972 if (!access_ok(addr, 2)) {
976 LoadHWE(addr, value, res);
981 compute_return_epc(regs);
982 regs->regs[insn.spec3_format.rt] = value;
985 if (!access_ok(addr, 4)) {
989 LoadWE(addr, value, res);
994 compute_return_epc(regs);
995 regs->regs[insn.spec3_format.rt] = value;
998 if (!access_ok(addr, 2)) {
1002 LoadHWUE(addr, value, res);
1007 compute_return_epc(regs);
1008 regs->regs[insn.spec3_format.rt] = value;
1011 if (!access_ok(addr, 2)) {
1015 compute_return_epc(regs);
1016 value = regs->regs[insn.spec3_format.rt];
1017 StoreHWE(addr, value, res);
1024 if (!access_ok(addr, 4)) {
1028 compute_return_epc(regs);
1029 value = regs->regs[insn.spec3_format.rt];
1030 StoreWE(addr, value, res);
1045 if (!access_ok(addr, 2))
1048 if (IS_ENABLED(CONFIG_EVA)) {
1049 if (uaccess_kernel())
1050 LoadHW(addr, value, res);
1052 LoadHWE(addr, value, res);
1054 LoadHW(addr, value, res);
1059 compute_return_epc(regs);
1060 regs->regs[insn.i_format.rt] = value;
1064 if (!access_ok(addr, 4))
1067 if (IS_ENABLED(CONFIG_EVA)) {
1068 if (uaccess_kernel())
1069 LoadW(addr, value, res);
1071 LoadWE(addr, value, res);
1073 LoadW(addr, value, res);
1078 compute_return_epc(regs);
1079 regs->regs[insn.i_format.rt] = value;
1083 if (!access_ok(addr, 2))
1086 if (IS_ENABLED(CONFIG_EVA)) {
1087 if (uaccess_kernel())
1088 LoadHWU(addr, value, res);
1090 LoadHWUE(addr, value, res);
1092 LoadHWU(addr, value, res);
1097 compute_return_epc(regs);
1098 regs->regs[insn.i_format.rt] = value;
1104 * A 32-bit kernel might be running on a 64-bit processor. But
1105 * if we're on a 32-bit processor and an i-cache incoherency
1106 * or race makes us see a 64-bit instruction here the sdl/sdr
1107 * would blow up, so for now we don't handle unaligned 64-bit
1108 * instructions on 32-bit kernels.
1110 if (!access_ok(addr, 4))
1113 LoadWU(addr, value, res);
1116 compute_return_epc(regs);
1117 regs->regs[insn.i_format.rt] = value;
1119 #endif /* CONFIG_64BIT */
1121 /* Cannot handle 64-bit instructions in 32-bit kernel */
1127 * A 32-bit kernel might be running on a 64-bit processor. But
1128 * if we're on a 32-bit processor and an i-cache incoherency
1129 * or race makes us see a 64-bit instruction here the sdl/sdr
1130 * would blow up, so for now we don't handle unaligned 64-bit
1131 * instructions on 32-bit kernels.
1133 if (!access_ok(addr, 8))
1136 LoadDW(addr, value, res);
1139 compute_return_epc(regs);
1140 regs->regs[insn.i_format.rt] = value;
1142 #endif /* CONFIG_64BIT */
1144 /* Cannot handle 64-bit instructions in 32-bit kernel */
1148 if (!access_ok(addr, 2))
1151 compute_return_epc(regs);
1152 value = regs->regs[insn.i_format.rt];
1154 if (IS_ENABLED(CONFIG_EVA)) {
1155 if (uaccess_kernel())
1156 StoreHW(addr, value, res);
1158 StoreHWE(addr, value, res);
1160 StoreHW(addr, value, res);
1168 if (!access_ok(addr, 4))
1171 compute_return_epc(regs);
1172 value = regs->regs[insn.i_format.rt];
1174 if (IS_ENABLED(CONFIG_EVA)) {
1175 if (uaccess_kernel())
1176 StoreW(addr, value, res);
1178 StoreWE(addr, value, res);
1180 StoreW(addr, value, res);
1190 * A 32-bit kernel might be running on a 64-bit processor. But
1191 * if we're on a 32-bit processor and an i-cache incoherency
1192 * or race makes us see a 64-bit instruction here the sdl/sdr
1193 * would blow up, so for now we don't handle unaligned 64-bit
1194 * instructions on 32-bit kernels.
1196 if (!access_ok(addr, 8))
1199 compute_return_epc(regs);
1200 value = regs->regs[insn.i_format.rt];
1201 StoreDW(addr, value, res);
1205 #endif /* CONFIG_64BIT */
1207 /* Cannot handle 64-bit instructions in 32-bit kernel */
1210 #ifdef CONFIG_MIPS_FP_SUPPORT
1217 void __user *fault_addr = NULL;
1219 die_if_kernel("Unaligned FP access in kernel code", regs);
1220 BUG_ON(!used_math());
1222 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1224 own_fpu(1); /* Restore FPU state. */
1226 /* Signal if something went wrong. */
1227 process_fpemu_return(res, fault_addr, 0);
1233 #endif /* CONFIG_MIPS_FP_SUPPORT */
1235 #ifdef CONFIG_CPU_HAS_MSA
1238 unsigned int wd, preempted;
1246 * If we've reached this point then userland should have taken
1247 * the MSA disabled exception & initialised vector context at
1248 * some point in the past.
1250 BUG_ON(!thread_msa_context_live());
1252 df = insn.msa_mi10_format.df;
1253 wd = insn.msa_mi10_format.wd;
1254 fpr = ¤t->thread.fpu.fpr[wd];
1256 switch (insn.msa_mi10_format.func) {
1258 if (!access_ok(addr, sizeof(*fpr)))
1263 * If we have live MSA context keep track of
1264 * whether we get preempted in order to avoid
1265 * the register context we load being clobbered
1266 * by the live context as it's saved during
1267 * preemption. If we don't have live context
1268 * then it can't be saved to clobber the value
1271 preempted = test_thread_flag(TIF_USEDMSA);
1273 res = __copy_from_user_inatomic(fpr, addr,
1279 * Update the hardware register if it is in use
1280 * by the task in this quantum, in order to
1281 * avoid having to save & restore the whole
1285 if (test_thread_flag(TIF_USEDMSA)) {
1286 write_msa_wr(wd, fpr, df);
1290 } while (preempted);
1294 if (!access_ok(addr, sizeof(*fpr)))
1298 * Update from the hardware register if it is in use by
1299 * the task in this quantum, in order to avoid having to
1300 * save & restore the whole vector context.
1303 if (test_thread_flag(TIF_USEDMSA))
1304 read_msa_wr(wd, fpr, df);
1307 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
1316 compute_return_epc(regs);
1319 #endif /* CONFIG_CPU_HAS_MSA */
1321 #ifndef CONFIG_CPU_MIPSR6
1323 * COP2 is available to implementor for application specific use.
1324 * It's up to applications to register a notifier chain and do
1325 * whatever they have to do, including possible sending of signals.
1327 * This instruction has been reallocated in Release 6
1330 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
1334 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
1338 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
1342 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
1347 * Pheeee... We encountered an yet unknown instruction or
1348 * cache coherence problem. Die sucker, die ...
1353 #ifdef CONFIG_DEBUG_FS
1354 unaligned_instructions++;
1360 /* roll back jump/branch */
1361 regs->cp0_epc = origpc;
1362 regs->regs[31] = orig31;
1363 /* Did we have an exception handler installed? */
1364 if (fixup_exception(regs))
1367 die_if_kernel("Unhandled kernel unaligned access", regs);
1368 force_sig(SIGSEGV, current);
1373 die_if_kernel("Unhandled kernel unaligned access", regs);
1374 force_sig(SIGBUS, current);
1380 ("Unhandled kernel unaligned access or invalid instruction", regs);
1381 force_sig(SIGILL, current);
1384 /* Recode table from 16-bit register notation to 32-bit GPR. */
1385 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
1387 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
1388 static const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
1390 static void emulate_load_store_microMIPS(struct pt_regs *regs,
1393 unsigned long value;
1396 unsigned int reg = 0, rvar;
1397 unsigned long orig31;
1401 unsigned long origpc, contpc;
1402 union mips_instruction insn;
1403 struct mm_decoded_insn mminsn;
1405 origpc = regs->cp0_epc;
1406 orig31 = regs->regs[31];
1408 mminsn.micro_mips_mode = 1;
1411 * This load never faults.
1413 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
1414 __get_user(halfword, pc16);
1416 contpc = regs->cp0_epc + 2;
1417 word = ((unsigned int)halfword << 16);
1420 if (!mm_insn_16bit(halfword)) {
1421 __get_user(halfword, pc16);
1423 contpc = regs->cp0_epc + 4;
1429 if (get_user(halfword, pc16))
1431 mminsn.next_pc_inc = 2;
1432 word = ((unsigned int)halfword << 16);
1434 if (!mm_insn_16bit(halfword)) {
1436 if (get_user(halfword, pc16))
1438 mminsn.next_pc_inc = 4;
1441 mminsn.next_insn = word;
1443 insn = (union mips_instruction)(mminsn.insn);
1444 if (mm_isBranchInstr(regs, mminsn, &contpc))
1445 insn = (union mips_instruction)(mminsn.next_insn);
1447 /* Parse instruction to find what to do */
1449 switch (insn.mm_i_format.opcode) {
1452 switch (insn.mm_x_format.func) {
1454 reg = insn.mm_x_format.rd;
1461 switch (insn.mm_m_format.func) {
1463 reg = insn.mm_m_format.rd;
1467 if (!access_ok(addr, 8))
1470 LoadW(addr, value, res);
1473 regs->regs[reg] = value;
1475 LoadW(addr, value, res);
1478 regs->regs[reg + 1] = value;
1482 reg = insn.mm_m_format.rd;
1486 if (!access_ok(addr, 8))
1489 value = regs->regs[reg];
1490 StoreW(addr, value, res);
1494 value = regs->regs[reg + 1];
1495 StoreW(addr, value, res);
1502 reg = insn.mm_m_format.rd;
1506 if (!access_ok(addr, 16))
1509 LoadDW(addr, value, res);
1512 regs->regs[reg] = value;
1514 LoadDW(addr, value, res);
1517 regs->regs[reg + 1] = value;
1519 #endif /* CONFIG_64BIT */
1525 reg = insn.mm_m_format.rd;
1529 if (!access_ok(addr, 16))
1532 value = regs->regs[reg];
1533 StoreDW(addr, value, res);
1537 value = regs->regs[reg + 1];
1538 StoreDW(addr, value, res);
1542 #endif /* CONFIG_64BIT */
1547 reg = insn.mm_m_format.rd;
1549 if ((rvar > 9) || !reg)
1552 if (!access_ok(addr, 4 * (rvar + 1)))
1555 if (!access_ok(addr, 4 * rvar))
1560 for (i = 16; rvar; rvar--, i++) {
1561 LoadW(addr, value, res);
1565 regs->regs[i] = value;
1567 if ((reg & 0xf) == 9) {
1568 LoadW(addr, value, res);
1572 regs->regs[30] = value;
1575 LoadW(addr, value, res);
1578 regs->regs[31] = value;
1583 reg = insn.mm_m_format.rd;
1585 if ((rvar > 9) || !reg)
1588 if (!access_ok(addr, 4 * (rvar + 1)))
1591 if (!access_ok(addr, 4 * rvar))
1596 for (i = 16; rvar; rvar--, i++) {
1597 value = regs->regs[i];
1598 StoreW(addr, value, res);
1603 if ((reg & 0xf) == 9) {
1604 value = regs->regs[30];
1605 StoreW(addr, value, res);
1611 value = regs->regs[31];
1612 StoreW(addr, value, res);
1620 reg = insn.mm_m_format.rd;
1622 if ((rvar > 9) || !reg)
1625 if (!access_ok(addr, 8 * (rvar + 1)))
1628 if (!access_ok(addr, 8 * rvar))
1634 for (i = 16; rvar; rvar--, i++) {
1635 LoadDW(addr, value, res);
1639 regs->regs[i] = value;
1641 if ((reg & 0xf) == 9) {
1642 LoadDW(addr, value, res);
1646 regs->regs[30] = value;
1649 LoadDW(addr, value, res);
1652 regs->regs[31] = value;
1655 #endif /* CONFIG_64BIT */
1661 reg = insn.mm_m_format.rd;
1663 if ((rvar > 9) || !reg)
1666 if (!access_ok(addr, 8 * (rvar + 1)))
1669 if (!access_ok(addr, 8 * rvar))
1675 for (i = 16; rvar; rvar--, i++) {
1676 value = regs->regs[i];
1677 StoreDW(addr, value, res);
1682 if ((reg & 0xf) == 9) {
1683 value = regs->regs[30];
1684 StoreDW(addr, value, res);
1690 value = regs->regs[31];
1691 StoreDW(addr, value, res);
1696 #endif /* CONFIG_64BIT */
1700 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1706 switch (insn.mm_m_format.func) {
1708 reg = insn.mm_m_format.rd;
1712 /* LL,SC,LLD,SCD are not serviced */
1715 #ifdef CONFIG_MIPS_FP_SUPPORT
1717 switch (insn.mm_x_format.func) {
1730 case mm_swc132_op: {
1731 void __user *fault_addr = NULL;
1734 /* roll back jump/branch */
1735 regs->cp0_epc = origpc;
1736 regs->regs[31] = orig31;
1738 die_if_kernel("Unaligned FP access in kernel code", regs);
1739 BUG_ON(!used_math());
1740 BUG_ON(!is_fpu_owner());
1742 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1744 own_fpu(1); /* restore FPU state */
1746 /* If something went wrong, signal */
1747 process_fpemu_return(res, fault_addr, 0);
1753 #endif /* CONFIG_MIPS_FP_SUPPORT */
1756 reg = insn.mm_i_format.rt;
1760 reg = insn.mm_i_format.rt;
1764 reg = insn.mm_i_format.rt;
1768 reg = insn.mm_i_format.rt;
1772 reg = insn.mm_i_format.rt;
1776 reg = insn.mm_i_format.rt;
1780 reg = insn.mm_i_format.rt;
1784 switch (insn.mm16_m_format.func) {
1786 reg = insn.mm16_m_format.rlist;
1788 if (!access_ok(addr, 4 * rvar))
1791 for (i = 16; rvar; rvar--, i++) {
1792 LoadW(addr, value, res);
1796 regs->regs[i] = value;
1798 LoadW(addr, value, res);
1801 regs->regs[31] = value;
1806 reg = insn.mm16_m_format.rlist;
1808 if (!access_ok(addr, 4 * rvar))
1811 for (i = 16; rvar; rvar--, i++) {
1812 value = regs->regs[i];
1813 StoreW(addr, value, res);
1818 value = regs->regs[31];
1819 StoreW(addr, value, res);
1830 reg = reg16to32[insn.mm16_rb_format.rt];
1834 reg = reg16to32[insn.mm16_rb_format.rt];
1838 reg = reg16to32st[insn.mm16_rb_format.rt];
1842 reg = reg16to32st[insn.mm16_rb_format.rt];
1846 reg = insn.mm16_r5_format.rt;
1850 reg = insn.mm16_r5_format.rt;
1854 reg = reg16to32[insn.mm16_r3_format.rt];
1862 if (!access_ok(addr, 2))
1865 LoadHW(addr, value, res);
1868 regs->regs[reg] = value;
1872 if (!access_ok(addr, 2))
1875 LoadHWU(addr, value, res);
1878 regs->regs[reg] = value;
1882 if (!access_ok(addr, 4))
1885 LoadW(addr, value, res);
1888 regs->regs[reg] = value;
1894 * A 32-bit kernel might be running on a 64-bit processor. But
1895 * if we're on a 32-bit processor and an i-cache incoherency
1896 * or race makes us see a 64-bit instruction here the sdl/sdr
1897 * would blow up, so for now we don't handle unaligned 64-bit
1898 * instructions on 32-bit kernels.
1900 if (!access_ok(addr, 4))
1903 LoadWU(addr, value, res);
1906 regs->regs[reg] = value;
1908 #endif /* CONFIG_64BIT */
1910 /* Cannot handle 64-bit instructions in 32-bit kernel */
1916 * A 32-bit kernel might be running on a 64-bit processor. But
1917 * if we're on a 32-bit processor and an i-cache incoherency
1918 * or race makes us see a 64-bit instruction here the sdl/sdr
1919 * would blow up, so for now we don't handle unaligned 64-bit
1920 * instructions on 32-bit kernels.
1922 if (!access_ok(addr, 8))
1925 LoadDW(addr, value, res);
1928 regs->regs[reg] = value;
1930 #endif /* CONFIG_64BIT */
1932 /* Cannot handle 64-bit instructions in 32-bit kernel */
1936 if (!access_ok(addr, 2))
1939 value = regs->regs[reg];
1940 StoreHW(addr, value, res);
1946 if (!access_ok(addr, 4))
1949 value = regs->regs[reg];
1950 StoreW(addr, value, res);
1958 * A 32-bit kernel might be running on a 64-bit processor. But
1959 * if we're on a 32-bit processor and an i-cache incoherency
1960 * or race makes us see a 64-bit instruction here the sdl/sdr
1961 * would blow up, so for now we don't handle unaligned 64-bit
1962 * instructions on 32-bit kernels.
1964 if (!access_ok(addr, 8))
1967 value = regs->regs[reg];
1968 StoreDW(addr, value, res);
1972 #endif /* CONFIG_64BIT */
1974 /* Cannot handle 64-bit instructions in 32-bit kernel */
1978 regs->cp0_epc = contpc; /* advance or branch */
1980 #ifdef CONFIG_DEBUG_FS
1981 unaligned_instructions++;
1986 /* roll back jump/branch */
1987 regs->cp0_epc = origpc;
1988 regs->regs[31] = orig31;
1989 /* Did we have an exception handler installed? */
1990 if (fixup_exception(regs))
1993 die_if_kernel("Unhandled kernel unaligned access", regs);
1994 force_sig(SIGSEGV, current);
1999 die_if_kernel("Unhandled kernel unaligned access", regs);
2000 force_sig(SIGBUS, current);
2006 ("Unhandled kernel unaligned access or invalid instruction", regs);
2007 force_sig(SIGILL, current);
2010 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
2012 unsigned long value;
2015 unsigned long orig31;
2017 unsigned long origpc;
2018 union mips16e_instruction mips16inst, oldinst;
2019 unsigned int opcode;
2022 origpc = regs->cp0_epc;
2023 orig31 = regs->regs[31];
2024 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
2026 * This load never faults.
2028 __get_user(mips16inst.full, pc16);
2029 oldinst = mips16inst;
2031 /* skip EXTEND instruction */
2032 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
2035 __get_user(mips16inst.full, pc16);
2036 } else if (delay_slot(regs)) {
2037 /* skip jump instructions */
2038 /* JAL/JALX are 32 bits but have OPCODE in first short int */
2039 if (mips16inst.ri.opcode == MIPS16e_jal_op)
2042 if (get_user(mips16inst.full, pc16))
2046 opcode = mips16inst.ri.opcode;
2048 case MIPS16e_i64_op: /* I64 or RI64 instruction */
2049 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
2050 case MIPS16e_ldpc_func:
2051 case MIPS16e_ldsp_func:
2052 reg = reg16to32[mips16inst.ri64.ry];
2055 case MIPS16e_sdsp_func:
2056 reg = reg16to32[mips16inst.ri64.ry];
2059 case MIPS16e_sdrasp_func:
2060 reg = 29; /* GPRSP */
2066 case MIPS16e_swsp_op:
2067 reg = reg16to32[mips16inst.ri.rx];
2068 if (extended && cpu_has_mips16e2)
2069 switch (mips16inst.ri.imm >> 5) {
2074 opcode = MIPS16e_sh_op;
2081 case MIPS16e_lwpc_op:
2082 reg = reg16to32[mips16inst.ri.rx];
2085 case MIPS16e_lwsp_op:
2086 reg = reg16to32[mips16inst.ri.rx];
2087 if (extended && cpu_has_mips16e2)
2088 switch (mips16inst.ri.imm >> 5) {
2093 opcode = MIPS16e_lh_op;
2096 opcode = MIPS16e_lhu_op;
2104 if (mips16inst.i8.func != MIPS16e_swrasp_func)
2106 reg = 29; /* GPRSP */
2110 reg = reg16to32[mips16inst.rri.ry];
2117 case MIPS16e_lbu_op:
2122 if (!access_ok(addr, 2))
2125 LoadHW(addr, value, res);
2128 MIPS16e_compute_return_epc(regs, &oldinst);
2129 regs->regs[reg] = value;
2132 case MIPS16e_lhu_op:
2133 if (!access_ok(addr, 2))
2136 LoadHWU(addr, value, res);
2139 MIPS16e_compute_return_epc(regs, &oldinst);
2140 regs->regs[reg] = value;
2144 case MIPS16e_lwpc_op:
2145 case MIPS16e_lwsp_op:
2146 if (!access_ok(addr, 4))
2149 LoadW(addr, value, res);
2152 MIPS16e_compute_return_epc(regs, &oldinst);
2153 regs->regs[reg] = value;
2156 case MIPS16e_lwu_op:
2159 * A 32-bit kernel might be running on a 64-bit processor. But
2160 * if we're on a 32-bit processor and an i-cache incoherency
2161 * or race makes us see a 64-bit instruction here the sdl/sdr
2162 * would blow up, so for now we don't handle unaligned 64-bit
2163 * instructions on 32-bit kernels.
2165 if (!access_ok(addr, 4))
2168 LoadWU(addr, value, res);
2171 MIPS16e_compute_return_epc(regs, &oldinst);
2172 regs->regs[reg] = value;
2174 #endif /* CONFIG_64BIT */
2176 /* Cannot handle 64-bit instructions in 32-bit kernel */
2183 * A 32-bit kernel might be running on a 64-bit processor. But
2184 * if we're on a 32-bit processor and an i-cache incoherency
2185 * or race makes us see a 64-bit instruction here the sdl/sdr
2186 * would blow up, so for now we don't handle unaligned 64-bit
2187 * instructions on 32-bit kernels.
2189 if (!access_ok(addr, 8))
2192 LoadDW(addr, value, res);
2195 MIPS16e_compute_return_epc(regs, &oldinst);
2196 regs->regs[reg] = value;
2198 #endif /* CONFIG_64BIT */
2200 /* Cannot handle 64-bit instructions in 32-bit kernel */
2204 if (!access_ok(addr, 2))
2207 MIPS16e_compute_return_epc(regs, &oldinst);
2208 value = regs->regs[reg];
2209 StoreHW(addr, value, res);
2215 case MIPS16e_swsp_op:
2216 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
2217 if (!access_ok(addr, 4))
2220 MIPS16e_compute_return_epc(regs, &oldinst);
2221 value = regs->regs[reg];
2222 StoreW(addr, value, res);
2231 * A 32-bit kernel might be running on a 64-bit processor. But
2232 * if we're on a 32-bit processor and an i-cache incoherency
2233 * or race makes us see a 64-bit instruction here the sdl/sdr
2234 * would blow up, so for now we don't handle unaligned 64-bit
2235 * instructions on 32-bit kernels.
2237 if (!access_ok(addr, 8))
2240 MIPS16e_compute_return_epc(regs, &oldinst);
2241 value = regs->regs[reg];
2242 StoreDW(addr, value, res);
2246 #endif /* CONFIG_64BIT */
2248 /* Cannot handle 64-bit instructions in 32-bit kernel */
2253 * Pheeee... We encountered an yet unknown instruction or
2254 * cache coherence problem. Die sucker, die ...
2259 #ifdef CONFIG_DEBUG_FS
2260 unaligned_instructions++;
2266 /* roll back jump/branch */
2267 regs->cp0_epc = origpc;
2268 regs->regs[31] = orig31;
2269 /* Did we have an exception handler installed? */
2270 if (fixup_exception(regs))
2273 die_if_kernel("Unhandled kernel unaligned access", regs);
2274 force_sig(SIGSEGV, current);
2279 die_if_kernel("Unhandled kernel unaligned access", regs);
2280 force_sig(SIGBUS, current);
2286 ("Unhandled kernel unaligned access or invalid instruction", regs);
2287 force_sig(SIGILL, current);
2290 asmlinkage void do_ade(struct pt_regs *regs)
2292 enum ctx_state prev_state;
2293 unsigned int __user *pc;
2296 prev_state = exception_enter();
2297 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
2298 1, regs, regs->cp0_badvaddr);
2300 * Did we catch a fault trying to load an instruction?
2302 if (regs->cp0_badvaddr == regs->cp0_epc)
2305 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
2307 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
2311 * Do branch emulation only if we didn't forward the exception.
2312 * This is all so but ugly ...
2316 * Are we running in microMIPS mode?
2318 if (get_isa16_mode(regs->cp0_epc)) {
2320 * Did we catch a fault trying to load an instruction in
2323 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
2325 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2326 show_registers(regs);
2328 if (cpu_has_mmips) {
2330 if (!user_mode(regs))
2332 emulate_load_store_microMIPS(regs,
2333 (void __user *)regs->cp0_badvaddr);
2339 if (cpu_has_mips16) {
2341 if (!user_mode(regs))
2343 emulate_load_store_MIPS16e(regs,
2344 (void __user *)regs->cp0_badvaddr);
2353 if (unaligned_action == UNALIGNED_ACTION_SHOW)
2354 show_registers(regs);
2355 pc = (unsigned int __user *)exception_epc(regs);
2358 if (!user_mode(regs))
2360 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
2366 die_if_kernel("Kernel unaligned instruction access", regs);
2367 force_sig(SIGBUS, current);
2370 * XXX On return from the signal handler we should advance the epc
2372 exception_exit(prev_state);
2375 #ifdef CONFIG_DEBUG_FS
2376 static int __init debugfs_unaligned(void)
2378 debugfs_create_u32("unaligned_instructions", S_IRUGO, mips_debugfs_dir,
2379 &unaligned_instructions);
2380 debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
2381 mips_debugfs_dir, &unaligned_action);
2384 arch_initcall(debugfs_unaligned);