2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
88 #include <asm/debug.h>
90 #include <asm/fpu_emulator.h>
92 #include <asm/unaligned-emul.h>
93 #include <asm/mmu_context.h>
94 #include <linux/uaccess.h>
97 UNALIGNED_ACTION_QUIET,
98 UNALIGNED_ACTION_SIGNAL,
99 UNALIGNED_ACTION_SHOW,
101 #ifdef CONFIG_DEBUG_FS
102 static u32 unaligned_instructions;
103 static u32 unaligned_action;
105 #define unaligned_action UNALIGNED_ACTION_QUIET
107 extern void show_registers(struct pt_regs *regs);
109 static void emulate_load_store_insn(struct pt_regs *regs,
110 void __user *addr, unsigned int __user *pc)
112 unsigned long origpc, orig31, value;
113 union mips_instruction insn;
118 origpc = (unsigned long)pc;
119 orig31 = regs->regs[31];
121 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
124 * This load never faults.
126 __get_user(insn.word, pc);
128 switch (insn.i_format.opcode) {
130 * These are instructions that a compiler doesn't generate. We
131 * can assume therefore that the code is MIPS-aware and
132 * really buggy. Emulating these instructions would break the
141 * For these instructions the only way to create an address
142 * error is an attempted access to kernel/supervisor address
159 * The remaining opcodes are the ones that are really of
163 if (insn.dsp_format.func == lx_op) {
164 switch (insn.dsp_format.op) {
166 if (!access_ok(addr, 4))
168 LoadW(addr, value, res);
171 compute_return_epc(regs);
172 regs->regs[insn.dsp_format.rd] = value;
175 if (!access_ok(addr, 2))
177 LoadHW(addr, value, res);
180 compute_return_epc(regs);
181 regs->regs[insn.dsp_format.rd] = value;
190 * we can land here only from kernel accessing user
191 * memory, so we need to "switch" the address limit to
192 * user space, so that address check can work properly.
194 seg = force_uaccess_begin();
195 switch (insn.spec3_format.func) {
197 if (!access_ok(addr, 2)) {
198 force_uaccess_end(seg);
201 LoadHWE(addr, value, res);
203 force_uaccess_end(seg);
206 compute_return_epc(regs);
207 regs->regs[insn.spec3_format.rt] = value;
210 if (!access_ok(addr, 4)) {
211 force_uaccess_end(seg);
214 LoadWE(addr, value, res);
216 force_uaccess_end(seg);
219 compute_return_epc(regs);
220 regs->regs[insn.spec3_format.rt] = value;
223 if (!access_ok(addr, 2)) {
224 force_uaccess_end(seg);
227 LoadHWUE(addr, value, res);
229 force_uaccess_end(seg);
232 compute_return_epc(regs);
233 regs->regs[insn.spec3_format.rt] = value;
236 if (!access_ok(addr, 2)) {
237 force_uaccess_end(seg);
240 compute_return_epc(regs);
241 value = regs->regs[insn.spec3_format.rt];
242 StoreHWE(addr, value, res);
244 force_uaccess_end(seg);
249 if (!access_ok(addr, 4)) {
250 force_uaccess_end(seg);
253 compute_return_epc(regs);
254 value = regs->regs[insn.spec3_format.rt];
255 StoreWE(addr, value, res);
257 force_uaccess_end(seg);
262 force_uaccess_end(seg);
265 force_uaccess_end(seg);
270 if (!access_ok(addr, 2))
273 if (IS_ENABLED(CONFIG_EVA)) {
274 if (uaccess_kernel())
275 LoadHW(addr, value, res);
277 LoadHWE(addr, value, res);
279 LoadHW(addr, value, res);
284 compute_return_epc(regs);
285 regs->regs[insn.i_format.rt] = value;
289 if (!access_ok(addr, 4))
292 if (IS_ENABLED(CONFIG_EVA)) {
293 if (uaccess_kernel())
294 LoadW(addr, value, res);
296 LoadWE(addr, value, res);
298 LoadW(addr, value, res);
303 compute_return_epc(regs);
304 regs->regs[insn.i_format.rt] = value;
308 if (!access_ok(addr, 2))
311 if (IS_ENABLED(CONFIG_EVA)) {
312 if (uaccess_kernel())
313 LoadHWU(addr, value, res);
315 LoadHWUE(addr, value, res);
317 LoadHWU(addr, value, res);
322 compute_return_epc(regs);
323 regs->regs[insn.i_format.rt] = value;
329 * A 32-bit kernel might be running on a 64-bit processor. But
330 * if we're on a 32-bit processor and an i-cache incoherency
331 * or race makes us see a 64-bit instruction here the sdl/sdr
332 * would blow up, so for now we don't handle unaligned 64-bit
333 * instructions on 32-bit kernels.
335 if (!access_ok(addr, 4))
338 LoadWU(addr, value, res);
341 compute_return_epc(regs);
342 regs->regs[insn.i_format.rt] = value;
344 #endif /* CONFIG_64BIT */
346 /* Cannot handle 64-bit instructions in 32-bit kernel */
352 * A 32-bit kernel might be running on a 64-bit processor. But
353 * if we're on a 32-bit processor and an i-cache incoherency
354 * or race makes us see a 64-bit instruction here the sdl/sdr
355 * would blow up, so for now we don't handle unaligned 64-bit
356 * instructions on 32-bit kernels.
358 if (!access_ok(addr, 8))
361 LoadDW(addr, value, res);
364 compute_return_epc(regs);
365 regs->regs[insn.i_format.rt] = value;
367 #endif /* CONFIG_64BIT */
369 /* Cannot handle 64-bit instructions in 32-bit kernel */
373 if (!access_ok(addr, 2))
376 compute_return_epc(regs);
377 value = regs->regs[insn.i_format.rt];
379 if (IS_ENABLED(CONFIG_EVA)) {
380 if (uaccess_kernel())
381 StoreHW(addr, value, res);
383 StoreHWE(addr, value, res);
385 StoreHW(addr, value, res);
393 if (!access_ok(addr, 4))
396 compute_return_epc(regs);
397 value = regs->regs[insn.i_format.rt];
399 if (IS_ENABLED(CONFIG_EVA)) {
400 if (uaccess_kernel())
401 StoreW(addr, value, res);
403 StoreWE(addr, value, res);
405 StoreW(addr, value, res);
415 * A 32-bit kernel might be running on a 64-bit processor. But
416 * if we're on a 32-bit processor and an i-cache incoherency
417 * or race makes us see a 64-bit instruction here the sdl/sdr
418 * would blow up, so for now we don't handle unaligned 64-bit
419 * instructions on 32-bit kernels.
421 if (!access_ok(addr, 8))
424 compute_return_epc(regs);
425 value = regs->regs[insn.i_format.rt];
426 StoreDW(addr, value, res);
430 #endif /* CONFIG_64BIT */
432 /* Cannot handle 64-bit instructions in 32-bit kernel */
435 #ifdef CONFIG_MIPS_FP_SUPPORT
442 void __user *fault_addr = NULL;
444 die_if_kernel("Unaligned FP access in kernel code", regs);
445 BUG_ON(!used_math());
447 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
449 own_fpu(1); /* Restore FPU state. */
451 /* Signal if something went wrong. */
452 process_fpemu_return(res, fault_addr, 0);
458 #endif /* CONFIG_MIPS_FP_SUPPORT */
460 #ifdef CONFIG_CPU_HAS_MSA
463 unsigned int wd, preempted;
471 * If we've reached this point then userland should have taken
472 * the MSA disabled exception & initialised vector context at
473 * some point in the past.
475 BUG_ON(!thread_msa_context_live());
477 df = insn.msa_mi10_format.df;
478 wd = insn.msa_mi10_format.wd;
479 fpr = ¤t->thread.fpu.fpr[wd];
481 switch (insn.msa_mi10_format.func) {
483 if (!access_ok(addr, sizeof(*fpr)))
488 * If we have live MSA context keep track of
489 * whether we get preempted in order to avoid
490 * the register context we load being clobbered
491 * by the live context as it's saved during
492 * preemption. If we don't have live context
493 * then it can't be saved to clobber the value
496 preempted = test_thread_flag(TIF_USEDMSA);
498 res = __copy_from_user_inatomic(fpr, addr,
504 * Update the hardware register if it is in use
505 * by the task in this quantum, in order to
506 * avoid having to save & restore the whole
510 if (test_thread_flag(TIF_USEDMSA)) {
511 write_msa_wr(wd, fpr, df);
519 if (!access_ok(addr, sizeof(*fpr)))
523 * Update from the hardware register if it is in use by
524 * the task in this quantum, in order to avoid having to
525 * save & restore the whole vector context.
528 if (test_thread_flag(TIF_USEDMSA))
529 read_msa_wr(wd, fpr, df);
532 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr));
541 compute_return_epc(regs);
544 #endif /* CONFIG_CPU_HAS_MSA */
546 #ifndef CONFIG_CPU_MIPSR6
548 * COP2 is available to implementor for application specific use.
549 * It's up to applications to register a notifier chain and do
550 * whatever they have to do, including possible sending of signals.
552 * This instruction has been reallocated in Release 6
555 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
559 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
563 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
567 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
572 * Pheeee... We encountered an yet unknown instruction or
573 * cache coherence problem. Die sucker, die ...
578 #ifdef CONFIG_DEBUG_FS
579 unaligned_instructions++;
585 /* roll back jump/branch */
586 regs->cp0_epc = origpc;
587 regs->regs[31] = orig31;
588 /* Did we have an exception handler installed? */
589 if (fixup_exception(regs))
592 die_if_kernel("Unhandled kernel unaligned access", regs);
598 die_if_kernel("Unhandled kernel unaligned access", regs);
605 ("Unhandled kernel unaligned access or invalid instruction", regs);
609 /* Recode table from 16-bit register notation to 32-bit GPR. */
610 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
612 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
613 static const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
615 static void emulate_load_store_microMIPS(struct pt_regs *regs,
621 unsigned int reg = 0, rvar;
622 unsigned long orig31;
626 unsigned long origpc, contpc;
627 union mips_instruction insn;
628 struct mm_decoded_insn mminsn;
630 origpc = regs->cp0_epc;
631 orig31 = regs->regs[31];
633 mminsn.micro_mips_mode = 1;
636 * This load never faults.
638 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
639 __get_user(halfword, pc16);
641 contpc = regs->cp0_epc + 2;
642 word = ((unsigned int)halfword << 16);
645 if (!mm_insn_16bit(halfword)) {
646 __get_user(halfword, pc16);
648 contpc = regs->cp0_epc + 4;
654 if (get_user(halfword, pc16))
656 mminsn.next_pc_inc = 2;
657 word = ((unsigned int)halfword << 16);
659 if (!mm_insn_16bit(halfword)) {
661 if (get_user(halfword, pc16))
663 mminsn.next_pc_inc = 4;
666 mminsn.next_insn = word;
668 insn = (union mips_instruction)(mminsn.insn);
669 if (mm_isBranchInstr(regs, mminsn, &contpc))
670 insn = (union mips_instruction)(mminsn.next_insn);
672 /* Parse instruction to find what to do */
674 switch (insn.mm_i_format.opcode) {
677 switch (insn.mm_x_format.func) {
679 reg = insn.mm_x_format.rd;
686 switch (insn.mm_m_format.func) {
688 reg = insn.mm_m_format.rd;
692 if (!access_ok(addr, 8))
695 LoadW(addr, value, res);
698 regs->regs[reg] = value;
700 LoadW(addr, value, res);
703 regs->regs[reg + 1] = value;
707 reg = insn.mm_m_format.rd;
711 if (!access_ok(addr, 8))
714 value = regs->regs[reg];
715 StoreW(addr, value, res);
719 value = regs->regs[reg + 1];
720 StoreW(addr, value, res);
727 reg = insn.mm_m_format.rd;
731 if (!access_ok(addr, 16))
734 LoadDW(addr, value, res);
737 regs->regs[reg] = value;
739 LoadDW(addr, value, res);
742 regs->regs[reg + 1] = value;
744 #endif /* CONFIG_64BIT */
750 reg = insn.mm_m_format.rd;
754 if (!access_ok(addr, 16))
757 value = regs->regs[reg];
758 StoreDW(addr, value, res);
762 value = regs->regs[reg + 1];
763 StoreDW(addr, value, res);
767 #endif /* CONFIG_64BIT */
772 reg = insn.mm_m_format.rd;
774 if ((rvar > 9) || !reg)
777 if (!access_ok(addr, 4 * (rvar + 1)))
780 if (!access_ok(addr, 4 * rvar))
785 for (i = 16; rvar; rvar--, i++) {
786 LoadW(addr, value, res);
790 regs->regs[i] = value;
792 if ((reg & 0xf) == 9) {
793 LoadW(addr, value, res);
797 regs->regs[30] = value;
800 LoadW(addr, value, res);
803 regs->regs[31] = value;
808 reg = insn.mm_m_format.rd;
810 if ((rvar > 9) || !reg)
813 if (!access_ok(addr, 4 * (rvar + 1)))
816 if (!access_ok(addr, 4 * rvar))
821 for (i = 16; rvar; rvar--, i++) {
822 value = regs->regs[i];
823 StoreW(addr, value, res);
828 if ((reg & 0xf) == 9) {
829 value = regs->regs[30];
830 StoreW(addr, value, res);
836 value = regs->regs[31];
837 StoreW(addr, value, res);
845 reg = insn.mm_m_format.rd;
847 if ((rvar > 9) || !reg)
850 if (!access_ok(addr, 8 * (rvar + 1)))
853 if (!access_ok(addr, 8 * rvar))
859 for (i = 16; rvar; rvar--, i++) {
860 LoadDW(addr, value, res);
864 regs->regs[i] = value;
866 if ((reg & 0xf) == 9) {
867 LoadDW(addr, value, res);
871 regs->regs[30] = value;
874 LoadDW(addr, value, res);
877 regs->regs[31] = value;
880 #endif /* CONFIG_64BIT */
886 reg = insn.mm_m_format.rd;
888 if ((rvar > 9) || !reg)
891 if (!access_ok(addr, 8 * (rvar + 1)))
894 if (!access_ok(addr, 8 * rvar))
900 for (i = 16; rvar; rvar--, i++) {
901 value = regs->regs[i];
902 StoreDW(addr, value, res);
907 if ((reg & 0xf) == 9) {
908 value = regs->regs[30];
909 StoreDW(addr, value, res);
915 value = regs->regs[31];
916 StoreDW(addr, value, res);
921 #endif /* CONFIG_64BIT */
925 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
931 switch (insn.mm_m_format.func) {
933 reg = insn.mm_m_format.rd;
937 /* LL,SC,LLD,SCD are not serviced */
940 #ifdef CONFIG_MIPS_FP_SUPPORT
942 switch (insn.mm_x_format.func) {
956 void __user *fault_addr = NULL;
959 /* roll back jump/branch */
960 regs->cp0_epc = origpc;
961 regs->regs[31] = orig31;
963 die_if_kernel("Unaligned FP access in kernel code", regs);
964 BUG_ON(!used_math());
965 BUG_ON(!is_fpu_owner());
967 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
969 own_fpu(1); /* restore FPU state */
971 /* If something went wrong, signal */
972 process_fpemu_return(res, fault_addr, 0);
978 #endif /* CONFIG_MIPS_FP_SUPPORT */
981 reg = insn.mm_i_format.rt;
985 reg = insn.mm_i_format.rt;
989 reg = insn.mm_i_format.rt;
993 reg = insn.mm_i_format.rt;
997 reg = insn.mm_i_format.rt;
1001 reg = insn.mm_i_format.rt;
1005 reg = insn.mm_i_format.rt;
1009 switch (insn.mm16_m_format.func) {
1011 reg = insn.mm16_m_format.rlist;
1013 if (!access_ok(addr, 4 * rvar))
1016 for (i = 16; rvar; rvar--, i++) {
1017 LoadW(addr, value, res);
1021 regs->regs[i] = value;
1023 LoadW(addr, value, res);
1026 regs->regs[31] = value;
1031 reg = insn.mm16_m_format.rlist;
1033 if (!access_ok(addr, 4 * rvar))
1036 for (i = 16; rvar; rvar--, i++) {
1037 value = regs->regs[i];
1038 StoreW(addr, value, res);
1043 value = regs->regs[31];
1044 StoreW(addr, value, res);
1055 reg = reg16to32[insn.mm16_rb_format.rt];
1059 reg = reg16to32[insn.mm16_rb_format.rt];
1063 reg = reg16to32st[insn.mm16_rb_format.rt];
1067 reg = reg16to32st[insn.mm16_rb_format.rt];
1071 reg = insn.mm16_r5_format.rt;
1075 reg = insn.mm16_r5_format.rt;
1079 reg = reg16to32[insn.mm16_r3_format.rt];
1087 if (!access_ok(addr, 2))
1090 LoadHW(addr, value, res);
1093 regs->regs[reg] = value;
1097 if (!access_ok(addr, 2))
1100 LoadHWU(addr, value, res);
1103 regs->regs[reg] = value;
1107 if (!access_ok(addr, 4))
1110 LoadW(addr, value, res);
1113 regs->regs[reg] = value;
1119 * A 32-bit kernel might be running on a 64-bit processor. But
1120 * if we're on a 32-bit processor and an i-cache incoherency
1121 * or race makes us see a 64-bit instruction here the sdl/sdr
1122 * would blow up, so for now we don't handle unaligned 64-bit
1123 * instructions on 32-bit kernels.
1125 if (!access_ok(addr, 4))
1128 LoadWU(addr, value, res);
1131 regs->regs[reg] = value;
1133 #endif /* CONFIG_64BIT */
1135 /* Cannot handle 64-bit instructions in 32-bit kernel */
1141 * A 32-bit kernel might be running on a 64-bit processor. But
1142 * if we're on a 32-bit processor and an i-cache incoherency
1143 * or race makes us see a 64-bit instruction here the sdl/sdr
1144 * would blow up, so for now we don't handle unaligned 64-bit
1145 * instructions on 32-bit kernels.
1147 if (!access_ok(addr, 8))
1150 LoadDW(addr, value, res);
1153 regs->regs[reg] = value;
1155 #endif /* CONFIG_64BIT */
1157 /* Cannot handle 64-bit instructions in 32-bit kernel */
1161 if (!access_ok(addr, 2))
1164 value = regs->regs[reg];
1165 StoreHW(addr, value, res);
1171 if (!access_ok(addr, 4))
1174 value = regs->regs[reg];
1175 StoreW(addr, value, res);
1183 * A 32-bit kernel might be running on a 64-bit processor. But
1184 * if we're on a 32-bit processor and an i-cache incoherency
1185 * or race makes us see a 64-bit instruction here the sdl/sdr
1186 * would blow up, so for now we don't handle unaligned 64-bit
1187 * instructions on 32-bit kernels.
1189 if (!access_ok(addr, 8))
1192 value = regs->regs[reg];
1193 StoreDW(addr, value, res);
1197 #endif /* CONFIG_64BIT */
1199 /* Cannot handle 64-bit instructions in 32-bit kernel */
1203 regs->cp0_epc = contpc; /* advance or branch */
1205 #ifdef CONFIG_DEBUG_FS
1206 unaligned_instructions++;
1211 /* roll back jump/branch */
1212 regs->cp0_epc = origpc;
1213 regs->regs[31] = orig31;
1214 /* Did we have an exception handler installed? */
1215 if (fixup_exception(regs))
1218 die_if_kernel("Unhandled kernel unaligned access", regs);
1224 die_if_kernel("Unhandled kernel unaligned access", regs);
1231 ("Unhandled kernel unaligned access or invalid instruction", regs);
1235 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1237 unsigned long value;
1240 unsigned long orig31;
1242 unsigned long origpc;
1243 union mips16e_instruction mips16inst, oldinst;
1244 unsigned int opcode;
1247 origpc = regs->cp0_epc;
1248 orig31 = regs->regs[31];
1249 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1251 * This load never faults.
1253 __get_user(mips16inst.full, pc16);
1254 oldinst = mips16inst;
1256 /* skip EXTEND instruction */
1257 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1260 __get_user(mips16inst.full, pc16);
1261 } else if (delay_slot(regs)) {
1262 /* skip jump instructions */
1263 /* JAL/JALX are 32 bits but have OPCODE in first short int */
1264 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1267 if (get_user(mips16inst.full, pc16))
1271 opcode = mips16inst.ri.opcode;
1273 case MIPS16e_i64_op: /* I64 or RI64 instruction */
1274 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
1275 case MIPS16e_ldpc_func:
1276 case MIPS16e_ldsp_func:
1277 reg = reg16to32[mips16inst.ri64.ry];
1280 case MIPS16e_sdsp_func:
1281 reg = reg16to32[mips16inst.ri64.ry];
1284 case MIPS16e_sdrasp_func:
1285 reg = 29; /* GPRSP */
1291 case MIPS16e_swsp_op:
1292 reg = reg16to32[mips16inst.ri.rx];
1293 if (extended && cpu_has_mips16e2)
1294 switch (mips16inst.ri.imm >> 5) {
1299 opcode = MIPS16e_sh_op;
1306 case MIPS16e_lwpc_op:
1307 reg = reg16to32[mips16inst.ri.rx];
1310 case MIPS16e_lwsp_op:
1311 reg = reg16to32[mips16inst.ri.rx];
1312 if (extended && cpu_has_mips16e2)
1313 switch (mips16inst.ri.imm >> 5) {
1318 opcode = MIPS16e_lh_op;
1321 opcode = MIPS16e_lhu_op;
1329 if (mips16inst.i8.func != MIPS16e_swrasp_func)
1331 reg = 29; /* GPRSP */
1335 reg = reg16to32[mips16inst.rri.ry];
1342 case MIPS16e_lbu_op:
1347 if (!access_ok(addr, 2))
1350 LoadHW(addr, value, res);
1353 MIPS16e_compute_return_epc(regs, &oldinst);
1354 regs->regs[reg] = value;
1357 case MIPS16e_lhu_op:
1358 if (!access_ok(addr, 2))
1361 LoadHWU(addr, value, res);
1364 MIPS16e_compute_return_epc(regs, &oldinst);
1365 regs->regs[reg] = value;
1369 case MIPS16e_lwpc_op:
1370 case MIPS16e_lwsp_op:
1371 if (!access_ok(addr, 4))
1374 LoadW(addr, value, res);
1377 MIPS16e_compute_return_epc(regs, &oldinst);
1378 regs->regs[reg] = value;
1381 case MIPS16e_lwu_op:
1384 * A 32-bit kernel might be running on a 64-bit processor. But
1385 * if we're on a 32-bit processor and an i-cache incoherency
1386 * or race makes us see a 64-bit instruction here the sdl/sdr
1387 * would blow up, so for now we don't handle unaligned 64-bit
1388 * instructions on 32-bit kernels.
1390 if (!access_ok(addr, 4))
1393 LoadWU(addr, value, res);
1396 MIPS16e_compute_return_epc(regs, &oldinst);
1397 regs->regs[reg] = value;
1399 #endif /* CONFIG_64BIT */
1401 /* Cannot handle 64-bit instructions in 32-bit kernel */
1408 * A 32-bit kernel might be running on a 64-bit processor. But
1409 * if we're on a 32-bit processor and an i-cache incoherency
1410 * or race makes us see a 64-bit instruction here the sdl/sdr
1411 * would blow up, so for now we don't handle unaligned 64-bit
1412 * instructions on 32-bit kernels.
1414 if (!access_ok(addr, 8))
1417 LoadDW(addr, value, res);
1420 MIPS16e_compute_return_epc(regs, &oldinst);
1421 regs->regs[reg] = value;
1423 #endif /* CONFIG_64BIT */
1425 /* Cannot handle 64-bit instructions in 32-bit kernel */
1429 if (!access_ok(addr, 2))
1432 MIPS16e_compute_return_epc(regs, &oldinst);
1433 value = regs->regs[reg];
1434 StoreHW(addr, value, res);
1440 case MIPS16e_swsp_op:
1441 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
1442 if (!access_ok(addr, 4))
1445 MIPS16e_compute_return_epc(regs, &oldinst);
1446 value = regs->regs[reg];
1447 StoreW(addr, value, res);
1456 * A 32-bit kernel might be running on a 64-bit processor. But
1457 * if we're on a 32-bit processor and an i-cache incoherency
1458 * or race makes us see a 64-bit instruction here the sdl/sdr
1459 * would blow up, so for now we don't handle unaligned 64-bit
1460 * instructions on 32-bit kernels.
1462 if (!access_ok(addr, 8))
1465 MIPS16e_compute_return_epc(regs, &oldinst);
1466 value = regs->regs[reg];
1467 StoreDW(addr, value, res);
1471 #endif /* CONFIG_64BIT */
1473 /* Cannot handle 64-bit instructions in 32-bit kernel */
1478 * Pheeee... We encountered an yet unknown instruction or
1479 * cache coherence problem. Die sucker, die ...
1484 #ifdef CONFIG_DEBUG_FS
1485 unaligned_instructions++;
1491 /* roll back jump/branch */
1492 regs->cp0_epc = origpc;
1493 regs->regs[31] = orig31;
1494 /* Did we have an exception handler installed? */
1495 if (fixup_exception(regs))
1498 die_if_kernel("Unhandled kernel unaligned access", regs);
1504 die_if_kernel("Unhandled kernel unaligned access", regs);
1511 ("Unhandled kernel unaligned access or invalid instruction", regs);
1515 asmlinkage void do_ade(struct pt_regs *regs)
1517 enum ctx_state prev_state;
1518 unsigned int __user *pc;
1521 prev_state = exception_enter();
1522 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
1523 1, regs, regs->cp0_badvaddr);
1525 * Did we catch a fault trying to load an instruction?
1527 if (regs->cp0_badvaddr == regs->cp0_epc)
1530 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
1532 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
1536 * Do branch emulation only if we didn't forward the exception.
1537 * This is all so but ugly ...
1541 * Are we running in microMIPS mode?
1543 if (get_isa16_mode(regs->cp0_epc)) {
1545 * Did we catch a fault trying to load an instruction in
1548 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
1550 if (unaligned_action == UNALIGNED_ACTION_SHOW)
1551 show_registers(regs);
1553 if (cpu_has_mmips) {
1555 if (!user_mode(regs))
1557 emulate_load_store_microMIPS(regs,
1558 (void __user *)regs->cp0_badvaddr);
1564 if (cpu_has_mips16) {
1566 if (!user_mode(regs))
1568 emulate_load_store_MIPS16e(regs,
1569 (void __user *)regs->cp0_badvaddr);
1578 if (unaligned_action == UNALIGNED_ACTION_SHOW)
1579 show_registers(regs);
1580 pc = (unsigned int __user *)exception_epc(regs);
1583 if (!user_mode(regs))
1585 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
1591 die_if_kernel("Kernel unaligned instruction access", regs);
1595 * XXX On return from the signal handler we should advance the epc
1597 exception_exit(prev_state);
1600 #ifdef CONFIG_DEBUG_FS
1601 static int __init debugfs_unaligned(void)
1603 debugfs_create_u32("unaligned_instructions", S_IRUGO, mips_debugfs_dir,
1604 &unaligned_instructions);
1605 debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
1606 mips_debugfs_dir, &unaligned_action);
1609 arch_initcall(debugfs_unaligned);