2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/compiler.h>
18 #include <linux/context_tracking.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/kexec.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/extable.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/debug.h>
28 #include <linux/smp.h>
29 #include <linux/spinlock.h>
30 #include <linux/kallsyms.h>
31 #include <linux/memblock.h>
32 #include <linux/interrupt.h>
33 #include <linux/ptrace.h>
34 #include <linux/kgdb.h>
35 #include <linux/kdebug.h>
36 #include <linux/kprobes.h>
37 #include <linux/notifier.h>
38 #include <linux/kdb.h>
39 #include <linux/irq.h>
40 #include <linux/perf_event.h>
42 #include <asm/addrspace.h>
43 #include <asm/bootinfo.h>
44 #include <asm/branch.h>
45 #include <asm/break.h>
48 #include <asm/cpu-type.h>
51 #include <asm/fpu_emulator.h>
53 #include <asm/isa-rev.h>
54 #include <asm/mips-cps.h>
55 #include <asm/mips-r2-to-r6-emul.h>
56 #include <asm/mipsregs.h>
57 #include <asm/mipsmtregs.h>
58 #include <asm/module.h>
60 #include <asm/ptrace.h>
61 #include <asm/sections.h>
62 #include <asm/siginfo.h>
63 #include <asm/tlbdebug.h>
64 #include <asm/traps.h>
65 #include <linux/uaccess.h>
66 #include <asm/watch.h>
67 #include <asm/mmu_context.h>
68 #include <asm/types.h>
69 #include <asm/stacktrace.h>
70 #include <asm/tlbex.h>
73 #include <asm/mach-loongson64/cpucfg-emul.h>
75 extern void check_wait(void);
76 extern asmlinkage void rollback_handle_int(void);
77 extern asmlinkage void handle_int(void);
78 extern asmlinkage void handle_adel(void);
79 extern asmlinkage void handle_ades(void);
80 extern asmlinkage void handle_ibe(void);
81 extern asmlinkage void handle_dbe(void);
82 extern asmlinkage void handle_sys(void);
83 extern asmlinkage void handle_bp(void);
84 extern asmlinkage void handle_ri(void);
85 extern asmlinkage void handle_ri_rdhwr_tlbp(void);
86 extern asmlinkage void handle_ri_rdhwr(void);
87 extern asmlinkage void handle_cpu(void);
88 extern asmlinkage void handle_ov(void);
89 extern asmlinkage void handle_tr(void);
90 extern asmlinkage void handle_msa_fpe(void);
91 extern asmlinkage void handle_fpe(void);
92 extern asmlinkage void handle_ftlb(void);
93 extern asmlinkage void handle_gsexc(void);
94 extern asmlinkage void handle_msa(void);
95 extern asmlinkage void handle_mdmx(void);
96 extern asmlinkage void handle_watch(void);
97 extern asmlinkage void handle_mt(void);
98 extern asmlinkage void handle_dsp(void);
99 extern asmlinkage void handle_mcheck(void);
100 extern asmlinkage void handle_reserved(void);
101 extern void tlb_do_page_fault_0(void);
103 void (*board_be_init)(void);
104 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
105 void (*board_nmi_handler_setup)(void);
106 void (*board_ejtag_handler_setup)(void);
107 void (*board_bind_eic_interrupt)(int irq, int regset);
108 void (*board_ebase_setup)(void);
109 void(*board_cache_error_setup)(void);
111 static void show_raw_backtrace(unsigned long reg29, const char *loglvl)
113 unsigned long *sp = (unsigned long *)(reg29 & ~3);
116 printk("%sCall Trace:", loglvl);
117 #ifdef CONFIG_KALLSYMS
118 printk("%s\n", loglvl);
120 while (!kstack_end(sp)) {
121 unsigned long __user *p =
122 (unsigned long __user *)(unsigned long)sp++;
123 if (__get_user(addr, p)) {
124 printk("%s (Bad stack address)", loglvl);
127 if (__kernel_text_address(addr))
128 print_ip_sym(loglvl, addr);
130 printk("%s\n", loglvl);
133 #ifdef CONFIG_KALLSYMS
135 static int __init set_raw_show_trace(char *str)
140 __setup("raw_show_trace", set_raw_show_trace);
143 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
146 unsigned long sp = regs->regs[29];
147 unsigned long ra = regs->regs[31];
148 unsigned long pc = regs->cp0_epc;
153 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
154 show_raw_backtrace(sp, loglvl);
157 printk("%sCall Trace:\n", loglvl);
159 print_ip_sym(loglvl, pc);
160 pc = unwind_stack(task, &sp, pc, &ra);
166 * This routine abuses get_user()/put_user() to reference pointers
167 * with at least a bit of error checking ...
169 static void show_stacktrace(struct task_struct *task,
170 const struct pt_regs *regs, const char *loglvl)
172 const int field = 2 * sizeof(unsigned long);
175 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
177 printk("%sStack :", loglvl);
179 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
180 if (i && ((i % (64 / field)) == 0)) {
182 printk("%s ", loglvl);
189 if (__get_user(stackdata, sp++)) {
190 pr_cont(" (Bad stack address)");
194 pr_cont(" %0*lx", field, stackdata);
198 show_backtrace(task, regs, loglvl);
201 void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
204 mm_segment_t old_fs = get_fs();
206 regs.cp0_status = KSU_KERNEL;
208 regs.regs[29] = (unsigned long)sp;
212 if (task && task != current) {
213 regs.regs[29] = task->thread.reg29;
215 regs.cp0_epc = task->thread.reg31;
217 prepare_frametrace(®s);
221 * show_stack() deals exclusively with kernel mode, so be sure to access
222 * the stack in the kernel (not user) address space.
225 show_stacktrace(task, ®s, loglvl);
229 static void show_code(unsigned int __user *pc)
232 unsigned short __user *pc16 = NULL;
236 if ((unsigned long)pc & 1)
237 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
238 for(i = -3 ; i < 6 ; i++) {
240 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
241 pr_cont(" (Bad address in epc)\n");
244 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
249 static void __show_regs(const struct pt_regs *regs)
251 const int field = 2 * sizeof(unsigned long);
252 unsigned int cause = regs->cp0_cause;
253 unsigned int exccode;
256 show_regs_print_info(KERN_DEFAULT);
259 * Saved main processor registers
261 for (i = 0; i < 32; ) {
265 pr_cont(" %0*lx", field, 0UL);
266 else if (i == 26 || i == 27)
267 pr_cont(" %*s", field, "");
269 pr_cont(" %0*lx", field, regs->regs[i]);
276 #ifdef CONFIG_CPU_HAS_SMARTMIPS
277 printk("Acx : %0*lx\n", field, regs->acx);
279 if (MIPS_ISA_REV < 6) {
280 printk("Hi : %0*lx\n", field, regs->hi);
281 printk("Lo : %0*lx\n", field, regs->lo);
285 * Saved cp0 registers
287 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
288 (void *) regs->cp0_epc);
289 printk("ra : %0*lx %pS\n", field, regs->regs[31],
290 (void *) regs->regs[31]);
292 printk("Status: %08x ", (uint32_t) regs->cp0_status);
295 if (regs->cp0_status & ST0_KUO)
297 if (regs->cp0_status & ST0_IEO)
299 if (regs->cp0_status & ST0_KUP)
301 if (regs->cp0_status & ST0_IEP)
303 if (regs->cp0_status & ST0_KUC)
305 if (regs->cp0_status & ST0_IEC)
307 } else if (cpu_has_4kex) {
308 if (regs->cp0_status & ST0_KX)
310 if (regs->cp0_status & ST0_SX)
312 if (regs->cp0_status & ST0_UX)
314 switch (regs->cp0_status & ST0_KSU) {
319 pr_cont("SUPERVISOR ");
325 pr_cont("BAD_MODE ");
328 if (regs->cp0_status & ST0_ERL)
330 if (regs->cp0_status & ST0_EXL)
332 if (regs->cp0_status & ST0_IE)
337 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
338 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
340 if (1 <= exccode && exccode <= 5)
341 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
343 printk("PrId : %08x (%s)\n", read_c0_prid(),
348 * FIXME: really the generic show_regs should take a const pointer argument.
350 void show_regs(struct pt_regs *regs)
356 void show_registers(struct pt_regs *regs)
358 const int field = 2 * sizeof(unsigned long);
359 mm_segment_t old_fs = get_fs();
363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
364 current->comm, current->pid, current_thread_info(), current,
365 field, current_thread_info()->tp_value);
366 if (cpu_has_userlocal) {
369 tls = read_c0_userlocal();
370 if (tls != current_thread_info()->tp_value)
371 printk("*HwTLS: %0*lx\n", field, tls);
374 if (!user_mode(regs))
375 /* Necessary for getting the correct stack content */
377 show_stacktrace(current, regs, KERN_DEFAULT);
378 show_code((unsigned int __user *) regs->cp0_epc);
383 static DEFINE_RAW_SPINLOCK(die_lock);
385 void __noreturn die(const char *str, struct pt_regs *regs)
387 static int die_counter;
392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
393 SIGSEGV) == NOTIFY_STOP)
397 raw_spin_lock_irq(&die_lock);
400 printk("%s[#%d]:\n", str, ++die_counter);
401 show_registers(regs);
402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
403 raw_spin_unlock_irq(&die_lock);
408 panic("Fatal exception in interrupt");
411 panic("Fatal exception");
413 if (regs && kexec_should_crash(current))
419 extern struct exception_table_entry __start___dbe_table[];
420 extern struct exception_table_entry __stop___dbe_table[];
423 " .section __dbe_table, \"a\"\n"
426 /* Given an address, look for it in the exception tables. */
427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
429 const struct exception_table_entry *e;
431 e = search_extable(__start___dbe_table,
432 __stop___dbe_table - __start___dbe_table, addr);
434 e = search_module_dbetables(addr);
438 asmlinkage void do_be(struct pt_regs *regs)
440 const int field = 2 * sizeof(unsigned long);
441 const struct exception_table_entry *fixup = NULL;
442 int data = regs->cp0_cause & 4;
443 int action = MIPS_BE_FATAL;
444 enum ctx_state prev_state;
446 prev_state = exception_enter();
447 /* XXX For now. Fixme, this searches the wrong table ... */
448 if (data && !user_mode(regs))
449 fixup = search_dbe_tables(exception_epc(regs));
452 action = MIPS_BE_FIXUP;
454 if (board_be_handler)
455 action = board_be_handler(regs, fixup != NULL);
457 mips_cm_error_report();
460 case MIPS_BE_DISCARD:
464 regs->cp0_epc = fixup->nextinsn;
473 * Assume it would be too dangerous to continue ...
475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
476 data ? "Data" : "Instruction",
477 field, regs->cp0_epc, field, regs->regs[31]);
478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
479 SIGBUS) == NOTIFY_STOP)
482 die_if_kernel("Oops", regs);
486 exception_exit(prev_state);
490 * ll/sc, rdhwr, sync emulation
493 #define OPCODE 0xfc000000
494 #define BASE 0x03e00000
495 #define RT 0x001f0000
496 #define OFFSET 0x0000ffff
497 #define LL 0xc0000000
498 #define SC 0xe0000000
499 #define SPEC0 0x00000000
500 #define SPEC3 0x7c000000
501 #define RD 0x0000f800
502 #define FUNC 0x0000003f
503 #define SYNC 0x0000000f
504 #define RDHWR 0x0000003b
506 /* microMIPS definitions */
507 #define MM_POOL32A_FUNC 0xfc00ffff
508 #define MM_RDHWR 0x00006b3c
509 #define MM_RS 0x001f0000
510 #define MM_RT 0x03e00000
513 * The ll_bit is cleared by r*_switch.S
517 struct task_struct *ll_task;
519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
521 unsigned long value, __user *vaddr;
525 * analyse the ll instruction that just caused a ri exception
526 * and put the referenced address to addr.
529 /* sign extend offset */
530 offset = opcode & OFFSET;
534 vaddr = (unsigned long __user *)
535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
537 if ((unsigned long)vaddr & 3)
539 if (get_user(value, vaddr))
544 if (ll_task == NULL || ll_task == current) {
553 regs->regs[(opcode & RT) >> 16] = value;
558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
560 unsigned long __user *vaddr;
565 * analyse the sc instruction that just caused a ri exception
566 * and put the referenced address to addr.
569 /* sign extend offset */
570 offset = opcode & OFFSET;
574 vaddr = (unsigned long __user *)
575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
576 reg = (opcode & RT) >> 16;
578 if ((unsigned long)vaddr & 3)
583 if (ll_bit == 0 || ll_task != current) {
591 if (put_user(regs->regs[reg], vaddr))
600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
601 * opcodes are supposed to result in coprocessor unusable exceptions if
602 * executed on ll/sc-less processors. That's the theory. In practice a
603 * few processors such as NEC's VR4100 throw reserved instruction exceptions
604 * instead, so we're doing the emulation thing in both exception handlers.
606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
608 if ((opcode & OPCODE) == LL) {
609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
611 return simulate_ll(regs, opcode);
613 if ((opcode & OPCODE) == SC) {
614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
616 return simulate_sc(regs, opcode);
619 return -1; /* Must be something else ... */
623 * Simulate trapping 'rdhwr' instructions to provide user accessible
624 * registers not implemented in hardware.
626 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
628 struct thread_info *ti = task_thread_info(current);
630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
633 case MIPS_HWR_CPUNUM: /* CPU number */
634 regs->regs[rt] = smp_processor_id();
636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
637 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
638 current_cpu_data.icache.linesz);
640 case MIPS_HWR_CC: /* Read count register */
641 regs->regs[rt] = read_c0_count();
643 case MIPS_HWR_CCRES: /* Count register resolution */
644 switch (current_cpu_type()) {
653 case MIPS_HWR_ULR: /* Read UserLocal register */
654 regs->regs[rt] = ti->tp_value;
661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
664 int rd = (opcode & RD) >> 11;
665 int rt = (opcode & RT) >> 16;
667 simulate_rdhwr(regs, rd, rt);
675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
678 int rd = (opcode & MM_RS) >> 16;
679 int rt = (opcode & MM_RT) >> 21;
680 simulate_rdhwr(regs, rd, rt);
688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
696 return -1; /* Must be something else ... */
700 * Loongson-3 CSR instructions emulation
703 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
705 #define LWC2 0xc8000000
707 #define CSR_OPCODE2 0x00000118
708 #define CSR_OPCODE2_MASK 0x000007ff
709 #define CSR_FUNC_MASK RT
710 #define CSR_FUNC_CPUCFG 0x8
712 static int simulate_loongson3_cpucfg(struct pt_regs *regs,
715 int op = opcode & OPCODE;
716 int op2 = opcode & CSR_OPCODE2_MASK;
717 int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
719 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {
720 int rd = (opcode & RD) >> 11;
721 int rs = (opcode & RS) >> 21;
722 __u64 sel = regs->regs[rs];
724 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
726 /* Do not emulate on unsupported core models. */
728 if (!loongson3_cpucfg_emulation_enabled(¤t_cpu_data)) {
732 regs->regs[rd] = loongson3_cpucfg_read_synthesized(
733 ¤t_cpu_data, sel);
741 #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */
743 asmlinkage void do_ov(struct pt_regs *regs)
745 enum ctx_state prev_state;
747 prev_state = exception_enter();
748 die_if_kernel("Integer overflow", regs);
750 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);
751 exception_exit(prev_state);
754 #ifdef CONFIG_MIPS_FP_SUPPORT
757 * Send SIGFPE according to FCSR Cause bits, which must have already
758 * been masked against Enable bits. This is impotant as Inexact can
759 * happen together with Overflow or Underflow, and `ptrace' can set
762 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
763 struct task_struct *tsk)
765 int si_code = FPE_FLTUNK;
767 if (fcr31 & FPU_CSR_INV_X)
768 si_code = FPE_FLTINV;
769 else if (fcr31 & FPU_CSR_DIV_X)
770 si_code = FPE_FLTDIV;
771 else if (fcr31 & FPU_CSR_OVF_X)
772 si_code = FPE_FLTOVF;
773 else if (fcr31 & FPU_CSR_UDF_X)
774 si_code = FPE_FLTUND;
775 else if (fcr31 & FPU_CSR_INE_X)
776 si_code = FPE_FLTRES;
778 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk);
781 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
784 struct vm_area_struct *vma;
791 force_fcr31_sig(fcr31, fault_addr, current);
795 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
799 mmap_read_lock(current->mm);
800 vma = find_vma(current->mm, (unsigned long)fault_addr);
801 if (vma && (vma->vm_start <= (unsigned long)fault_addr))
802 si_code = SEGV_ACCERR;
804 si_code = SEGV_MAPERR;
805 mmap_read_unlock(current->mm);
806 force_sig_fault(SIGSEGV, si_code, fault_addr);
815 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
816 unsigned long old_epc, unsigned long old_ra)
818 union mips_instruction inst = { .word = opcode };
819 void __user *fault_addr;
823 /* If it's obviously not an FP instruction, skip it */
824 switch (inst.i_format.opcode) {
838 * do_ri skipped over the instruction via compute_return_epc, undo
839 * that for the FPU emulator.
841 regs->cp0_epc = old_epc;
842 regs->regs[31] = old_ra;
844 /* Run the emulator */
845 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
849 * We can't allow the emulated instruction to leave any
850 * enabled Cause bits set in $fcr31.
852 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
853 current->thread.fpu.fcr31 &= ~fcr31;
855 /* Restore the hardware register state */
858 /* Send a signal if required. */
859 process_fpemu_return(sig, fault_addr, fcr31);
865 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
867 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
869 enum ctx_state prev_state;
870 void __user *fault_addr;
873 prev_state = exception_enter();
874 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
875 SIGFPE) == NOTIFY_STOP)
878 /* Clear FCSR.Cause before enabling interrupts */
879 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
882 die_if_kernel("FP exception in kernel code", regs);
884 if (fcr31 & FPU_CSR_UNI_X) {
886 * Unimplemented operation exception. If we've got the full
887 * software emulator on-board, let's use it...
889 * Force FPU to dump state into task/thread context. We're
890 * moving a lot of data here for what is probably a single
891 * instruction, but the alternative is to pre-decode the FP
892 * register operands before invoking the emulator, which seems
893 * a bit extreme for what should be an infrequent event.
896 /* Run the emulator */
897 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
901 * We can't allow the emulated instruction to leave any
902 * enabled Cause bits set in $fcr31.
904 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
905 current->thread.fpu.fcr31 &= ~fcr31;
907 /* Restore the hardware register state */
908 own_fpu(1); /* Using the FPU again. */
911 fault_addr = (void __user *) regs->cp0_epc;
914 /* Send a signal if required. */
915 process_fpemu_return(sig, fault_addr, fcr31);
918 exception_exit(prev_state);
922 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
923 * emulated more than some threshold number of instructions, force migration to
924 * a "CPU" that has FP support.
926 static void mt_ase_fp_affinity(void)
928 #ifdef CONFIG_MIPS_MT_FPAFF
929 if (mt_fpemul_threshold > 0 &&
930 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
932 * If there's no FPU present, or if the application has already
933 * restricted the allowed set to exclude any CPUs with FPUs,
934 * we'll skip the procedure.
936 if (cpumask_intersects(¤t->cpus_mask, &mt_fpu_cpumask)) {
939 current->thread.user_cpus_allowed
940 = current->cpus_mask;
941 cpumask_and(&tmask, ¤t->cpus_mask,
943 set_cpus_allowed_ptr(current, &tmask);
944 set_thread_flag(TIF_FPUBOUND);
947 #endif /* CONFIG_MIPS_MT_FPAFF */
950 #else /* !CONFIG_MIPS_FP_SUPPORT */
952 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
953 unsigned long old_epc, unsigned long old_ra)
958 #endif /* !CONFIG_MIPS_FP_SUPPORT */
960 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
965 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
966 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
967 SIGTRAP) == NOTIFY_STOP)
969 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
971 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
972 SIGTRAP) == NOTIFY_STOP)
976 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
977 * insns, even for trap and break codes that indicate arithmetic
978 * failures. Weird ...
979 * But should we continue the brokenness??? --macro
984 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
985 die_if_kernel(b, regs);
986 force_sig_fault(SIGFPE,
987 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
988 (void __user *) regs->cp0_epc);
991 die_if_kernel("Kernel bug detected", regs);
996 * This breakpoint code is used by the FPU emulator to retake
997 * control of the CPU after executing the instruction from the
998 * delay slot of an emulated branch.
1000 * Terminate if exception was recognized as a delay slot return
1001 * otherwise handle as normal.
1003 if (do_dsemulret(regs))
1006 die_if_kernel("Math emu break/trap", regs);
1010 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
1011 die_if_kernel(b, regs);
1013 force_sig_fault(SIGTRAP, si_code, NULL);
1020 asmlinkage void do_bp(struct pt_regs *regs)
1022 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1023 unsigned int opcode, bcode;
1024 enum ctx_state prev_state;
1028 if (!user_mode(regs))
1031 prev_state = exception_enter();
1032 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1033 if (get_isa16_mode(regs->cp0_epc)) {
1036 if (__get_user(instr[0], (u16 __user *)epc))
1039 if (!cpu_has_mmips) {
1041 bcode = (instr[0] >> 5) & 0x3f;
1042 } else if (mm_insn_16bit(instr[0])) {
1043 /* 16-bit microMIPS BREAK */
1044 bcode = instr[0] & 0xf;
1046 /* 32-bit microMIPS BREAK */
1047 if (__get_user(instr[1], (u16 __user *)(epc + 2)))
1049 opcode = (instr[0] << 16) | instr[1];
1050 bcode = (opcode >> 6) & ((1 << 20) - 1);
1053 if (__get_user(opcode, (unsigned int __user *)epc))
1055 bcode = (opcode >> 6) & ((1 << 20) - 1);
1059 * There is the ancient bug in the MIPS assemblers that the break
1060 * code starts left to bit 16 instead to bit 6 in the opcode.
1061 * Gas is bug-compatible, but not always, grrr...
1062 * We handle both cases with a simple heuristics. --macro
1064 if (bcode >= (1 << 10))
1065 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
1068 * notify the kprobe handlers, if instruction is likely to
1073 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1074 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1078 case BRK_UPROBE_XOL:
1079 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1080 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1085 if (notify_die(DIE_BREAK, "debug", regs, bcode,
1086 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1090 case BRK_KPROBE_SSTEPBP:
1091 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
1092 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1100 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
1104 exception_exit(prev_state);
1112 asmlinkage void do_tr(struct pt_regs *regs)
1114 u32 opcode, tcode = 0;
1115 enum ctx_state prev_state;
1118 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1121 if (!user_mode(regs))
1124 prev_state = exception_enter();
1125 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1126 if (get_isa16_mode(regs->cp0_epc)) {
1127 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
1128 __get_user(instr[1], (u16 __user *)(epc + 2)))
1130 opcode = (instr[0] << 16) | instr[1];
1131 /* Immediate versions don't provide a code. */
1132 if (!(opcode & OPCODE))
1133 tcode = (opcode >> 12) & ((1 << 4) - 1);
1135 if (__get_user(opcode, (u32 __user *)epc))
1137 /* Immediate versions don't provide a code. */
1138 if (!(opcode & OPCODE))
1139 tcode = (opcode >> 6) & ((1 << 10) - 1);
1142 do_trap_or_bp(regs, tcode, 0, "Trap");
1146 exception_exit(prev_state);
1154 asmlinkage void do_ri(struct pt_regs *regs)
1156 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1157 unsigned long old_epc = regs->cp0_epc;
1158 unsigned long old31 = regs->regs[31];
1159 enum ctx_state prev_state;
1160 unsigned int opcode = 0;
1164 * Avoid any kernel code. Just emulate the R2 instruction
1165 * as quickly as possible.
1167 if (mipsr2_emulation && cpu_has_mips_r6 &&
1168 likely(user_mode(regs)) &&
1169 likely(get_user(opcode, epc) >= 0)) {
1170 unsigned long fcr31 = 0;
1172 status = mipsr2_decoder(regs, opcode, &fcr31);
1180 process_fpemu_return(status,
1181 ¤t->thread.cp0_baduaddr,
1189 prev_state = exception_enter();
1190 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1192 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
1193 SIGILL) == NOTIFY_STOP)
1196 die_if_kernel("Reserved instruction in kernel code", regs);
1198 if (unlikely(compute_return_epc(regs) < 0))
1201 if (!get_isa16_mode(regs->cp0_epc)) {
1202 if (unlikely(get_user(opcode, epc) < 0))
1205 if (!cpu_has_llsc && status < 0)
1206 status = simulate_llsc(regs, opcode);
1209 status = simulate_rdhwr_normal(regs, opcode);
1212 status = simulate_sync(regs, opcode);
1215 status = simulate_fp(regs, opcode, old_epc, old31);
1217 #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
1219 status = simulate_loongson3_cpucfg(regs, opcode);
1221 } else if (cpu_has_mmips) {
1222 unsigned short mmop[2] = { 0 };
1224 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1226 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1229 opcode = (opcode << 16) | mmop[1];
1232 status = simulate_rdhwr_mm(regs, opcode);
1238 if (unlikely(status > 0)) {
1239 regs->cp0_epc = old_epc; /* Undo skip-over. */
1240 regs->regs[31] = old31;
1245 exception_exit(prev_state);
1249 * No lock; only written during early bootup by CPU 0.
1251 static RAW_NOTIFIER_HEAD(cu2_chain);
1253 int __ref register_cu2_notifier(struct notifier_block *nb)
1255 return raw_notifier_chain_register(&cu2_chain, nb);
1258 int cu2_notifier_call_chain(unsigned long val, void *v)
1260 return raw_notifier_call_chain(&cu2_chain, val, v);
1263 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1266 struct pt_regs *regs = data;
1268 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1269 "instruction", regs);
1275 #ifdef CONFIG_MIPS_FP_SUPPORT
1277 static int enable_restore_fp_context(int msa)
1279 int err, was_fpu_owner, prior_msa;
1282 /* Initialize context if it hasn't been used already */
1283 first_fp = init_fp_ctx(current);
1287 err = own_fpu_inatomic(1);
1290 set_thread_flag(TIF_USEDMSA);
1291 set_thread_flag(TIF_MSA_CTX_LIVE);
1298 * This task has formerly used the FP context.
1300 * If this thread has no live MSA vector context then we can simply
1301 * restore the scalar FP context. If it has live MSA vector context
1302 * (that is, it has or may have used MSA since last performing a
1303 * function call) then we'll need to restore the vector context. This
1304 * applies even if we're currently only executing a scalar FP
1305 * instruction. This is because if we were to later execute an MSA
1306 * instruction then we'd either have to:
1308 * - Restore the vector context & clobber any registers modified by
1309 * scalar FP instructions between now & then.
1313 * - Not restore the vector context & lose the most significant bits
1314 * of all vector registers.
1316 * Neither of those options is acceptable. We cannot restore the least
1317 * significant bits of the registers now & only restore the most
1318 * significant bits later because the most significant bits of any
1319 * vector registers whose aliased FP register is modified now will have
1320 * been zeroed. We'd have no way to know that when restoring the vector
1321 * context & thus may load an outdated value for the most significant
1322 * bits of a vector register.
1324 if (!msa && !thread_msa_context_live())
1328 * This task is using or has previously used MSA. Thus we require
1329 * that Status.FR == 1.
1332 was_fpu_owner = is_fpu_owner();
1333 err = own_fpu_inatomic(0);
1338 write_msa_csr(current->thread.fpu.msacsr);
1339 set_thread_flag(TIF_USEDMSA);
1342 * If this is the first time that the task is using MSA and it has
1343 * previously used scalar FP in this time slice then we already nave
1344 * FP context which we shouldn't clobber. We do however need to clear
1345 * the upper 64b of each vector register so that this task has no
1346 * opportunity to see data left behind by another.
1348 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1349 if (!prior_msa && was_fpu_owner) {
1357 * Restore the least significant 64b of each vector register
1358 * from the existing scalar FP context.
1360 _restore_fp(current);
1363 * The task has not formerly used MSA, so clear the upper 64b
1364 * of each vector register such that it cannot see data left
1365 * behind by another task.
1369 /* We need to restore the vector context. */
1370 restore_msa(current);
1372 /* Restore the scalar FP control & status register */
1374 write_32bit_cp1_register(CP1_STATUS,
1375 current->thread.fpu.fcr31);
1384 #else /* !CONFIG_MIPS_FP_SUPPORT */
1386 static int enable_restore_fp_context(int msa)
1391 #endif /* CONFIG_MIPS_FP_SUPPORT */
1393 asmlinkage void do_cpu(struct pt_regs *regs)
1395 enum ctx_state prev_state;
1396 unsigned int __user *epc;
1397 unsigned long old_epc, old31;
1398 unsigned int opcode;
1402 prev_state = exception_enter();
1403 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1406 die_if_kernel("do_cpu invoked from kernel context!", regs);
1410 epc = (unsigned int __user *)exception_epc(regs);
1411 old_epc = regs->cp0_epc;
1412 old31 = regs->regs[31];
1416 if (unlikely(compute_return_epc(regs) < 0))
1419 if (!get_isa16_mode(regs->cp0_epc)) {
1420 if (unlikely(get_user(opcode, epc) < 0))
1423 if (!cpu_has_llsc && status < 0)
1424 status = simulate_llsc(regs, opcode);
1430 if (unlikely(status > 0)) {
1431 regs->cp0_epc = old_epc; /* Undo skip-over. */
1432 regs->regs[31] = old31;
1438 #ifdef CONFIG_MIPS_FP_SUPPORT
1441 * The COP3 opcode space and consequently the CP0.Status.CU3
1442 * bit and the CP0.Cause.CE=3 encoding have been removed as
1443 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1444 * up the space has been reused for COP1X instructions, that
1445 * are enabled by the CP0.Status.CU1 bit and consequently
1446 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1447 * exceptions. Some FPU-less processors that implement one
1448 * of these ISAs however use this code erroneously for COP1X
1449 * instructions. Therefore we redirect this trap to the FP
1452 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1458 void __user *fault_addr;
1459 unsigned long fcr31;
1462 err = enable_restore_fp_context(0);
1464 if (raw_cpu_has_fpu && !err)
1467 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0,
1471 * We can't allow the emulated instruction to leave
1472 * any enabled Cause bits set in $fcr31.
1474 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1475 current->thread.fpu.fcr31 &= ~fcr31;
1477 /* Send a signal if required. */
1478 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1479 mt_ase_fp_affinity();
1483 #else /* CONFIG_MIPS_FP_SUPPORT */
1488 #endif /* CONFIG_MIPS_FP_SUPPORT */
1491 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1495 exception_exit(prev_state);
1498 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
1500 enum ctx_state prev_state;
1502 prev_state = exception_enter();
1503 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
1504 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
1505 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
1508 /* Clear MSACSR.Cause before enabling interrupts */
1509 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1512 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1515 exception_exit(prev_state);
1518 asmlinkage void do_msa(struct pt_regs *regs)
1520 enum ctx_state prev_state;
1523 prev_state = exception_enter();
1525 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1530 die_if_kernel("do_msa invoked from kernel context!", regs);
1532 err = enable_restore_fp_context(1);
1536 exception_exit(prev_state);
1539 asmlinkage void do_mdmx(struct pt_regs *regs)
1541 enum ctx_state prev_state;
1543 prev_state = exception_enter();
1545 exception_exit(prev_state);
1549 * Called with interrupts disabled.
1551 asmlinkage void do_watch(struct pt_regs *regs)
1553 enum ctx_state prev_state;
1555 prev_state = exception_enter();
1557 * Clear WP (bit 22) bit of cause register so we don't loop
1560 clear_c0_cause(CAUSEF_WP);
1563 * If the current thread has the watch registers loaded, save
1564 * their values and send SIGTRAP. Otherwise another thread
1565 * left the registers set, clear them and continue.
1567 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1568 mips_read_watch_registers();
1570 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL);
1572 mips_clear_watch_registers();
1575 exception_exit(prev_state);
1578 asmlinkage void do_mcheck(struct pt_regs *regs)
1580 int multi_match = regs->cp0_status & ST0_TS;
1581 enum ctx_state prev_state;
1582 mm_segment_t old_fs = get_fs();
1584 prev_state = exception_enter();
1593 if (!user_mode(regs))
1596 show_code((unsigned int __user *) regs->cp0_epc);
1601 * Some chips may have other causes of machine check (e.g. SB1
1604 panic("Caught Machine Check exception - %scaused by multiple "
1605 "matching entries in the TLB.",
1606 (multi_match) ? "" : "not ");
1609 asmlinkage void do_mt(struct pt_regs *regs)
1613 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1614 >> VPECONTROL_EXCPT_SHIFT;
1617 printk(KERN_DEBUG "Thread Underflow\n");
1620 printk(KERN_DEBUG "Thread Overflow\n");
1623 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1626 printk(KERN_DEBUG "Gating Storage Exception\n");
1629 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1632 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1635 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1639 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1645 asmlinkage void do_dsp(struct pt_regs *regs)
1648 panic("Unexpected DSP exception");
1653 asmlinkage void do_reserved(struct pt_regs *regs)
1656 * Game over - no way to handle this if it ever occurs. Most probably
1657 * caused by a new unknown cpu type or after another deadly
1658 * hard/software error.
1661 panic("Caught reserved exception %ld - should not happen.",
1662 (regs->cp0_cause & 0x7f) >> 2);
1665 static int __initdata l1parity = 1;
1666 static int __init nol1parity(char *s)
1671 __setup("nol1par", nol1parity);
1672 static int __initdata l2parity = 1;
1673 static int __init nol2parity(char *s)
1678 __setup("nol2par", nol2parity);
1681 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1682 * it different ways.
1684 static inline __init void parity_protection_init(void)
1686 #define ERRCTL_PE 0x80000000
1687 #define ERRCTL_L2P 0x00800000
1689 if (mips_cm_revision() >= CM_REV_CM3) {
1690 ulong gcr_ectl, cp0_ectl;
1693 * With CM3 systems we need to ensure that the L1 & L2
1694 * parity enables are set to the same value, since this
1695 * is presumed by the hardware engineers.
1697 * If the user disabled either of L1 or L2 ECC checking,
1700 l1parity &= l2parity;
1701 l2parity &= l1parity;
1703 /* Probe L1 ECC support */
1704 cp0_ectl = read_c0_ecc();
1705 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1706 back_to_back_c0_hazard();
1707 cp0_ectl = read_c0_ecc();
1709 /* Probe L2 ECC support */
1710 gcr_ectl = read_gcr_err_control();
1712 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
1713 !(cp0_ectl & ERRCTL_PE)) {
1715 * One of L1 or L2 ECC checking isn't supported,
1716 * so we cannot enable either.
1718 l1parity = l2parity = 0;
1721 /* Configure L1 ECC checking */
1723 cp0_ectl |= ERRCTL_PE;
1725 cp0_ectl &= ~ERRCTL_PE;
1726 write_c0_ecc(cp0_ectl);
1727 back_to_back_c0_hazard();
1728 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1730 /* Configure L2 ECC checking */
1732 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1734 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
1735 write_gcr_err_control(gcr_ectl);
1736 gcr_ectl = read_gcr_err_control();
1737 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
1738 WARN_ON(!!gcr_ectl != l2parity);
1740 pr_info("Cache parity protection %sabled\n",
1741 l1parity ? "en" : "dis");
1745 switch (current_cpu_type()) {
1751 case CPU_INTERAPTIV:
1754 case CPU_QEMU_GENERIC:
1757 unsigned long errctl;
1758 unsigned int l1parity_present, l2parity_present;
1760 errctl = read_c0_ecc();
1761 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1763 /* probe L1 parity support */
1764 write_c0_ecc(errctl | ERRCTL_PE);
1765 back_to_back_c0_hazard();
1766 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1768 /* probe L2 parity support */
1769 write_c0_ecc(errctl|ERRCTL_L2P);
1770 back_to_back_c0_hazard();
1771 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1773 if (l1parity_present && l2parity_present) {
1775 errctl |= ERRCTL_PE;
1776 if (l1parity ^ l2parity)
1777 errctl |= ERRCTL_L2P;
1778 } else if (l1parity_present) {
1780 errctl |= ERRCTL_PE;
1781 } else if (l2parity_present) {
1783 errctl |= ERRCTL_L2P;
1785 /* No parity available */
1788 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1790 write_c0_ecc(errctl);
1791 back_to_back_c0_hazard();
1792 errctl = read_c0_ecc();
1793 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1795 if (l1parity_present)
1796 printk(KERN_INFO "Cache parity protection %sabled\n",
1797 (errctl & ERRCTL_PE) ? "en" : "dis");
1799 if (l2parity_present) {
1800 if (l1parity_present && l1parity)
1801 errctl ^= ERRCTL_L2P;
1802 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1803 (errctl & ERRCTL_L2P) ? "en" : "dis");
1810 case CPU_LOONGSON32:
1811 write_c0_ecc(0x80000000);
1812 back_to_back_c0_hazard();
1813 /* Set the PE bit (bit 31) in the c0_errctl register. */
1814 printk(KERN_INFO "Cache parity protection %sabled\n",
1815 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1819 /* Clear the DE bit (bit 16) in the c0_status register. */
1820 printk(KERN_INFO "Enable cache parity protection for "
1821 "MIPS 20KC/25KF CPUs.\n");
1822 clear_c0_status(ST0_DE);
1829 asmlinkage void cache_parity_error(void)
1831 const int field = 2 * sizeof(unsigned long);
1832 unsigned int reg_val;
1834 /* For the moment, report the problem and hang. */
1835 printk("Cache error exception:\n");
1836 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1837 reg_val = read_c0_cacheerr();
1838 printk("c0_cacheerr == %08x\n", reg_val);
1840 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1841 reg_val & (1<<30) ? "secondary" : "primary",
1842 reg_val & (1<<31) ? "data" : "insn");
1843 if ((cpu_has_mips_r2_r6) &&
1844 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1845 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1846 reg_val & (1<<29) ? "ED " : "",
1847 reg_val & (1<<28) ? "ET " : "",
1848 reg_val & (1<<27) ? "ES " : "",
1849 reg_val & (1<<26) ? "EE " : "",
1850 reg_val & (1<<25) ? "EB " : "",
1851 reg_val & (1<<24) ? "EI " : "",
1852 reg_val & (1<<23) ? "E1 " : "",
1853 reg_val & (1<<22) ? "E0 " : "");
1855 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1856 reg_val & (1<<29) ? "ED " : "",
1857 reg_val & (1<<28) ? "ET " : "",
1858 reg_val & (1<<26) ? "EE " : "",
1859 reg_val & (1<<25) ? "EB " : "",
1860 reg_val & (1<<24) ? "EI " : "",
1861 reg_val & (1<<23) ? "E1 " : "",
1862 reg_val & (1<<22) ? "E0 " : "");
1864 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1866 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1867 if (reg_val & (1<<22))
1868 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1870 if (reg_val & (1<<23))
1871 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1874 panic("Can't handle the cache error!");
1877 asmlinkage void do_ftlb(void)
1879 const int field = 2 * sizeof(unsigned long);
1880 unsigned int reg_val;
1882 /* For the moment, report the problem and hang. */
1883 if ((cpu_has_mips_r2_r6) &&
1884 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1885 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
1886 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1888 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1889 reg_val = read_c0_cacheerr();
1890 pr_err("c0_cacheerr == %08x\n", reg_val);
1892 if ((reg_val & 0xc0000000) == 0xc0000000) {
1893 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1895 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1896 reg_val & (1<<30) ? "secondary" : "primary",
1897 reg_val & (1<<31) ? "data" : "insn");
1900 pr_err("FTLB error exception\n");
1902 /* Just print the cacheerr bits for now */
1903 cache_parity_error();
1906 asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
1908 u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >>
1909 LOONGSON_DIAG1_EXCCODE_SHIFT;
1910 enum ctx_state prev_state;
1912 prev_state = exception_enter();
1916 /* Undocumented exception, will trigger on certain
1917 * also-undocumented instructions accessible from userspace.
1918 * Processor state is not otherwise corrupted, but currently
1919 * we don't know how to proceed. Maybe there is some
1920 * undocumented control flag to enable the instructions?
1926 /* None of the other exceptions, documented or not, have
1927 * further details given; none are encountered in the wild
1928 * either. Panic in case some of them turn out to be fatal.
1931 panic("Unhandled Loongson exception - GSCause = %08x", diag1);
1934 exception_exit(prev_state);
1938 * SDBBP EJTAG debug exception handler.
1939 * We skip the instruction and return to the next instruction.
1941 void ejtag_exception_handler(struct pt_regs *regs)
1943 const int field = 2 * sizeof(unsigned long);
1944 unsigned long depc, old_epc, old_ra;
1947 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1948 depc = read_c0_depc();
1949 debug = read_c0_debug();
1950 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1951 if (debug & 0x80000000) {
1953 * In branch delay slot.
1954 * We cheat a little bit here and use EPC to calculate the
1955 * debug return address (DEPC). EPC is restored after the
1958 old_epc = regs->cp0_epc;
1959 old_ra = regs->regs[31];
1960 regs->cp0_epc = depc;
1961 compute_return_epc(regs);
1962 depc = regs->cp0_epc;
1963 regs->cp0_epc = old_epc;
1964 regs->regs[31] = old_ra;
1967 write_c0_depc(depc);
1970 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1971 write_c0_debug(debug | 0x100);
1976 * NMI exception handler.
1977 * No lock; only written during early bootup by CPU 0.
1979 static RAW_NOTIFIER_HEAD(nmi_chain);
1981 int register_nmi_notifier(struct notifier_block *nb)
1983 return raw_notifier_chain_register(&nmi_chain, nb);
1986 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1991 raw_notifier_call_chain(&nmi_chain, 0, regs);
1993 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1994 smp_processor_id(), regs->cp0_epc);
1995 regs->cp0_epc = read_c0_errorepc();
2000 #define VECTORSPACING 0x100 /* for EI/VI mode */
2002 unsigned long ebase;
2003 EXPORT_SYMBOL_GPL(ebase);
2004 unsigned long exception_handlers[32];
2005 unsigned long vi_handlers[64];
2007 void __init *set_except_vector(int n, void *addr)
2009 unsigned long handler = (unsigned long) addr;
2010 unsigned long old_handler;
2012 #ifdef CONFIG_CPU_MICROMIPS
2014 * Only the TLB handlers are cache aligned with an even
2015 * address. All other handlers are on an odd address and
2016 * require no modification. Otherwise, MIPS32 mode will
2017 * be entered when handling any TLB exceptions. That
2018 * would be bad...since we must stay in microMIPS mode.
2020 if (!(handler & 0x1))
2023 old_handler = xchg(&exception_handlers[n], handler);
2025 if (n == 0 && cpu_has_divec) {
2026 #ifdef CONFIG_CPU_MICROMIPS
2027 unsigned long jump_mask = ~((1 << 27) - 1);
2029 unsigned long jump_mask = ~((1 << 28) - 1);
2031 u32 *buf = (u32 *)(ebase + 0x200);
2032 unsigned int k0 = 26;
2033 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
2034 uasm_i_j(&buf, handler & ~jump_mask);
2037 UASM_i_LA(&buf, k0, handler);
2038 uasm_i_jr(&buf, k0);
2041 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
2043 return (void *)old_handler;
2046 static void do_default_vi(void)
2048 show_regs(get_irq_regs());
2049 panic("Caught unexpected vectored interrupt.");
2052 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
2054 unsigned long handler;
2055 unsigned long old_handler = vi_handlers[n];
2056 int srssets = current_cpu_data.srsets;
2060 BUG_ON(!cpu_has_veic && !cpu_has_vint);
2063 handler = (unsigned long) do_default_vi;
2066 handler = (unsigned long) addr;
2067 vi_handlers[n] = handler;
2069 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2072 panic("Shadow register set %d not supported", srs);
2075 if (board_bind_eic_interrupt)
2076 board_bind_eic_interrupt(n, srs);
2077 } else if (cpu_has_vint) {
2078 /* SRSMap is only defined if shadow sets are implemented */
2080 change_c0_srsmap(0xf << n*4, srs << n*4);
2085 * If no shadow set is selected then use the default handler
2086 * that does normal register saving and standard interrupt exit
2088 extern char except_vec_vi, except_vec_vi_lui;
2089 extern char except_vec_vi_ori, except_vec_vi_end;
2090 extern char rollback_except_vec_vi;
2091 char *vec_start = using_rollback_handler() ?
2092 &rollback_except_vec_vi : &except_vec_vi;
2093 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
2094 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
2095 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
2097 const int lui_offset = &except_vec_vi_lui - vec_start;
2098 const int ori_offset = &except_vec_vi_ori - vec_start;
2100 const int handler_len = &except_vec_vi_end - vec_start;
2102 if (handler_len > VECTORSPACING) {
2104 * Sigh... panicing won't help as the console
2105 * is probably not configured :(
2107 panic("VECTORSPACING too small");
2110 set_handler(((unsigned long)b - ebase), vec_start,
2111 #ifdef CONFIG_CPU_MICROMIPS
2116 h = (u16 *)(b + lui_offset);
2117 *h = (handler >> 16) & 0xffff;
2118 h = (u16 *)(b + ori_offset);
2119 *h = (handler & 0xffff);
2120 local_flush_icache_range((unsigned long)b,
2121 (unsigned long)(b+handler_len));
2125 * In other cases jump directly to the interrupt handler. It
2126 * is the handler's responsibility to save registers if required
2127 * (eg hi/lo) and return from the exception using "eret".
2133 #ifdef CONFIG_CPU_MICROMIPS
2134 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2136 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2138 h[0] = (insn >> 16) & 0xffff;
2139 h[1] = insn & 0xffff;
2142 local_flush_icache_range((unsigned long)b,
2143 (unsigned long)(b+8));
2146 return (void *)old_handler;
2149 void *set_vi_handler(int n, vi_handler_t addr)
2151 return set_vi_srs_handler(n, addr, 0);
2154 extern void tlb_init(void);
2159 int cp0_compare_irq;
2160 EXPORT_SYMBOL_GPL(cp0_compare_irq);
2161 int cp0_compare_irq_shift;
2164 * Performance counter IRQ or -1 if shared with timer
2166 int cp0_perfcount_irq;
2167 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2170 * Fast debug channel IRQ or -1 if not present
2173 EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2177 static int __init ulri_disable(char *s)
2179 pr_info("Disabling ulri\n");
2184 __setup("noulri", ulri_disable);
2186 /* configure STATUS register */
2187 static void configure_status(void)
2190 * Disable coprocessors and select 32-bit or 64-bit addressing
2191 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2192 * flag that some firmware may have left set and the TS bit (for
2193 * IP27). Set XX for ISA IV code to work.
2195 unsigned int status_set = ST0_CU0;
2197 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2199 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
2200 status_set |= ST0_XX;
2202 status_set |= ST0_MX;
2204 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
2206 back_to_back_c0_hazard();
2209 unsigned int hwrena;
2210 EXPORT_SYMBOL_GPL(hwrena);
2212 /* configure HWRENA register */
2213 static void configure_hwrena(void)
2215 hwrena = cpu_hwrena_impl_bits;
2217 if (cpu_has_mips_r2_r6)
2218 hwrena |= MIPS_HWRENA_CPUNUM |
2219 MIPS_HWRENA_SYNCISTEP |
2223 if (!noulri && cpu_has_userlocal)
2224 hwrena |= MIPS_HWRENA_ULR;
2227 write_c0_hwrena(hwrena);
2230 static void configure_exception_vector(void)
2232 if (cpu_has_mips_r2_r6) {
2233 unsigned long sr = set_c0_status(ST0_BEV);
2234 /* If available, use WG to set top bits of EBASE */
2235 if (cpu_has_ebase_wg) {
2237 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2239 write_c0_ebase(ebase | MIPS_EBASE_WG);
2242 write_c0_ebase(ebase);
2243 write_c0_status(sr);
2245 if (cpu_has_veic || cpu_has_vint) {
2246 /* Setting vector spacing enables EI/VI mode */
2247 change_c0_intctl(0x3e0, VECTORSPACING);
2249 if (cpu_has_divec) {
2250 if (cpu_has_mipsmt) {
2251 unsigned int vpflags = dvpe();
2252 set_c0_cause(CAUSEF_IV);
2255 set_c0_cause(CAUSEF_IV);
2259 void per_cpu_trap_init(bool is_boot_cpu)
2261 unsigned int cpu = smp_processor_id();
2266 configure_exception_vector();
2269 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2271 * o read IntCtl.IPTI to determine the timer interrupt
2272 * o read IntCtl.IPPCI to determine the performance counter interrupt
2273 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
2275 if (cpu_has_mips_r2_r6) {
2276 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2277 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2278 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2279 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2284 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2285 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2286 cp0_perfcount_irq = -1;
2291 cpu_data[cpu].asid_cache = 0;
2292 else if (!cpu_data[cpu].asid_cache)
2293 cpu_data[cpu].asid_cache = asid_first_version(cpu);
2296 current->active_mm = &init_mm;
2297 BUG_ON(current->mm);
2298 enter_lazy_tlb(&init_mm, current);
2300 /* Boot CPU's cache setup in setup_arch(). */
2304 TLBMISS_HANDLER_SETUP();
2307 /* Install CPU exception handler */
2308 void set_handler(unsigned long offset, void *addr, unsigned long size)
2310 #ifdef CONFIG_CPU_MICROMIPS
2311 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2313 memcpy((void *)(ebase + offset), addr, size);
2315 local_flush_icache_range(ebase + offset, ebase + offset + size);
2318 static const char panic_null_cerr[] =
2319 "Trying to set NULL cache error exception handler\n";
2322 * Install uncached CPU exception handler.
2323 * This is suitable only for the cache error exception which is the only
2324 * exception handler that is being run uncached.
2326 void set_uncached_handler(unsigned long offset, void *addr,
2329 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2332 panic(panic_null_cerr);
2334 memcpy((void *)(uncached_ebase + offset), addr, size);
2337 static int __initdata rdhwr_noopt;
2338 static int __init set_rdhwr_noopt(char *str)
2344 __setup("rdhwr_noopt", set_rdhwr_noopt);
2346 void __init trap_init(void)
2348 extern char except_vec3_generic;
2349 extern char except_vec4;
2350 extern char except_vec3_r4000;
2351 unsigned long i, vec_size;
2352 phys_addr_t ebase_pa;
2356 if (!cpu_has_mips_r2_r6) {
2358 ebase_pa = virt_to_phys((void *)ebase);
2361 memblock_reserve(ebase_pa, vec_size);
2363 if (cpu_has_veic || cpu_has_vint)
2364 vec_size = 0x200 + VECTORSPACING*64;
2366 vec_size = PAGE_SIZE;
2368 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
2370 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
2371 __func__, vec_size, 1 << fls(vec_size));
2374 * Try to ensure ebase resides in KSeg0 if possible.
2376 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2377 * hitting a poorly defined exception base for Cache Errors.
2378 * The allocation is likely to be in the low 512MB of physical,
2379 * in which case we should be able to convert to KSeg0.
2381 * EVA is special though as it allows segments to be rearranged
2382 * and to become uncached during cache error handling.
2384 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2385 ebase = CKSEG0ADDR(ebase_pa);
2387 ebase = (unsigned long)phys_to_virt(ebase_pa);
2390 if (cpu_has_mmips) {
2391 unsigned int config3 = read_c0_config3();
2393 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2394 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2396 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2399 if (board_ebase_setup)
2400 board_ebase_setup();
2401 per_cpu_trap_init(true);
2402 memblock_set_bottom_up(false);
2405 * Copy the generic exception handlers to their final destination.
2406 * This will be overridden later as suitable for a particular
2409 set_handler(0x180, &except_vec3_generic, 0x80);
2412 * Setup default vectors
2414 for (i = 0; i <= 31; i++)
2415 set_except_vector(i, handle_reserved);
2418 * Copy the EJTAG debug exception vector handler code to it's final
2421 if (cpu_has_ejtag && board_ejtag_handler_setup)
2422 board_ejtag_handler_setup();
2425 * Only some CPUs have the watch exceptions.
2428 set_except_vector(EXCCODE_WATCH, handle_watch);
2431 * Initialise interrupt handlers
2433 if (cpu_has_veic || cpu_has_vint) {
2434 int nvec = cpu_has_veic ? 64 : 8;
2435 for (i = 0; i < nvec; i++)
2436 set_vi_handler(i, NULL);
2438 else if (cpu_has_divec)
2439 set_handler(0x200, &except_vec4, 0x8);
2442 * Some CPUs can enable/disable for cache parity detection, but does
2443 * it different ways.
2445 parity_protection_init();
2448 * The Data Bus Errors / Instruction Bus Errors are signaled
2449 * by external hardware. Therefore these two exceptions
2450 * may have board specific handlers.
2455 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2456 rollback_handle_int : handle_int);
2457 set_except_vector(EXCCODE_MOD, handle_tlbm);
2458 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2459 set_except_vector(EXCCODE_TLBS, handle_tlbs);
2461 set_except_vector(EXCCODE_ADEL, handle_adel);
2462 set_except_vector(EXCCODE_ADES, handle_ades);
2464 set_except_vector(EXCCODE_IBE, handle_ibe);
2465 set_except_vector(EXCCODE_DBE, handle_dbe);
2467 set_except_vector(EXCCODE_SYS, handle_sys);
2468 set_except_vector(EXCCODE_BP, handle_bp);
2471 set_except_vector(EXCCODE_RI, handle_ri);
2473 if (cpu_has_vtag_icache)
2474 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2475 else if (current_cpu_type() == CPU_LOONGSON64)
2476 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2478 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2481 set_except_vector(EXCCODE_CPU, handle_cpu);
2482 set_except_vector(EXCCODE_OV, handle_ov);
2483 set_except_vector(EXCCODE_TR, handle_tr);
2484 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
2486 if (board_nmi_handler_setup)
2487 board_nmi_handler_setup();
2489 if (cpu_has_fpu && !cpu_has_nofpuex)
2490 set_except_vector(EXCCODE_FPE, handle_fpe);
2492 if (cpu_has_ftlbparex)
2493 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
2495 if (cpu_has_gsexcex)
2496 set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
2498 if (cpu_has_rixiex) {
2499 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2500 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
2503 set_except_vector(EXCCODE_MSADIS, handle_msa);
2504 set_except_vector(EXCCODE_MDMX, handle_mdmx);
2507 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
2510 set_except_vector(EXCCODE_THREAD, handle_mt);
2512 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
2514 if (board_cache_error_setup)
2515 board_cache_error_setup();
2518 /* Special exception: R4[04]00 uses also the divec space. */
2519 set_handler(0x180, &except_vec3_r4000, 0x100);
2520 else if (cpu_has_4kex)
2521 set_handler(0x180, &except_vec3_generic, 0x80);
2523 set_handler(0x080, &except_vec3_generic, 0x80);
2525 local_flush_icache_range(ebase, ebase + vec_size);
2527 sort_extable(__start___dbe_table, __stop___dbe_table);
2529 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2532 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2536 case CPU_PM_ENTER_FAILED:
2540 configure_exception_vector();
2542 /* Restore register with CPU number for TLB handlers */
2543 TLBMISS_HANDLER_RESTORE();
2551 static struct notifier_block trap_pm_notifier_block = {
2552 .notifier_call = trap_pm_notifier,
2555 static int __init trap_pm_init(void)
2557 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2559 arch_initcall(trap_pm_init);