2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2004 Mips Technologies, Inc
17 * Copyright (C) 2008 Kevin D. Kissell
20 #include <linux/clockchips.h>
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/smp.h>
24 #include <linux/cpumask.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/module.h>
28 #include <linux/ftrace.h>
29 #include <linux/slab.h>
32 #include <asm/processor.h>
33 #include <linux/atomic.h>
34 #include <asm/hardirq.h>
35 #include <asm/hazards.h>
37 #include <asm/mmu_context.h>
38 #include <asm/mipsregs.h>
39 #include <asm/cacheflush.h>
41 #include <asm/addrspace.h>
43 #include <asm/smtc_proc.h>
44 #include <asm/setup.h>
47 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
48 * in do_IRQ. These are passed in setup_irq_smtc() and stored
51 unsigned long irq_hwmask[NR_IRQS];
53 #define LOCK_MT_PRA() \
54 local_irq_save(flags); \
57 #define UNLOCK_MT_PRA() \
59 local_irq_restore(flags)
61 #define LOCK_CORE_PRA() \
62 local_irq_save(flags); \
65 #define UNLOCK_CORE_PRA() \
67 local_irq_restore(flags)
70 * Data structures purely associated with SMTC parallelism
75 * Table for tracking ASIDs whose lifetime is prolonged.
78 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
81 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
84 #define IPIBUF_PER_CPU 4
86 struct smtc_ipi_q IPIQ[NR_CPUS];
87 static struct smtc_ipi_q freeIPIq;
91 * Number of FPU contexts for each VPE
94 static int smtc_nconf1[MAX_SMTC_VPES];
97 /* Forward declarations */
99 void ipi_decode(struct smtc_ipi *);
100 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
101 static void setup_cross_vpe_interrupts(unsigned int nvpe);
102 void init_smtc_stats(void);
104 /* Global SMTC Status */
106 unsigned int smtc_status;
108 /* Boot command line configuration overrides */
110 static int vpe0limit;
111 static int ipibuffers;
114 unsigned long smtc_asid_mask = 0xff;
116 static int __init vpe0tcs(char *str)
118 get_option(&str, &vpe0limit);
123 static int __init ipibufs(char *str)
125 get_option(&str, &ipibuffers);
129 static int __init stlb_disable(char *s)
135 static int __init asidmask_set(char *str)
137 get_option(&str, &asidmask);
147 smtc_asid_mask = (unsigned long)asidmask;
150 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
155 __setup("vpe0tcs=", vpe0tcs);
156 __setup("ipibufs=", ipibufs);
157 __setup("nostlb", stlb_disable);
158 __setup("asidmask=", asidmask_set);
160 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
162 static int hang_trig;
164 static int __init hangtrig_enable(char *s)
171 __setup("hangtrig", hangtrig_enable);
173 #define DEFAULT_BLOCKED_IPI_LIMIT 32
175 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
177 static int __init tintq(char *str)
179 get_option(&str, &timerq_limit);
183 __setup("tintq=", tintq);
185 static int imstuckcount[MAX_SMTC_VPES][8];
186 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
187 static int vpemask[MAX_SMTC_VPES][8] = {
188 {0, 0, 1, 0, 0, 0, 0, 1},
189 {0, 0, 0, 0, 0, 0, 0, 1}
191 int tcnoprog[NR_CPUS];
192 static atomic_t idle_hook_initialized = ATOMIC_INIT(0);
193 static int clock_hang_reported[NR_CPUS];
195 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
198 * Configure shared TLB - VPC configuration bit must be set by caller
201 static void smtc_configure_tlb(void)
204 unsigned long mvpconf0;
205 unsigned long config1val;
207 /* Set up ASID preservation table */
208 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
209 for(i = 0; i < MAX_SMTC_ASIDS; i++) {
210 smtc_live_asid[vpes][i] = 0;
213 mvpconf0 = read_c0_mvpconf0();
215 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
216 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
217 /* If we have multiple VPEs, try to share the TLB */
218 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
220 * If TLB sizing is programmable, shared TLB
221 * size is the total available complement.
222 * Otherwise, we have to take the sum of all
223 * static VPE TLB entries.
225 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
226 >> MVPCONF0_PTLBE_SHIFT)) == 0) {
228 * If there's more than one VPE, there had better
229 * be more than one TC, because we need one to bind
230 * to each VPE in turn to be able to read
231 * its configuration state!
234 /* Stop the TC from doing anything foolish */
235 write_tc_c0_tchalt(TCHALT_H);
237 /* No need to un-Halt - that happens later anyway */
238 for (i=0; i < vpes; i++) {
239 write_tc_c0_tcbind(i);
241 * To be 100% sure we're really getting the right
242 * information, we exit the configuration state
243 * and do an IHB after each rebinding.
246 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
249 * Only count if the MMU Type indicated is TLB
251 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
252 config1val = read_vpe_c0_config1();
253 tlbsiz += ((config1val >> 25) & 0x3f) + 1;
256 /* Put core back in configuration state */
258 read_c0_mvpcontrol() | MVPCONTROL_VPC );
262 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
266 * Setup kernel data structures to use software total,
267 * rather than read the per-VPE Config1 value. The values
268 * for "CPU 0" gets copied to all the other CPUs as part
269 * of their initialization in smtc_cpu_setup().
272 /* MIPS32 limits TLB indices to 64 */
275 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
276 smtc_status |= SMTC_TLB_SHARED;
277 local_flush_tlb_all();
279 printk("TLB of %d entry pairs shared by %d VPEs\n",
282 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
289 * Incrementally build the CPU map out of constituent MIPS MT cores,
290 * using the specified available VPEs and TCs. Plaform code needs
291 * to ensure that each MIPS MT core invokes this routine on reset,
294 * This version of the build_cpu_map and prepare_cpus routines assumes
295 * that *all* TCs of a MIPS MT core will be used for Linux, and that
296 * they will be spread across *all* available VPEs (to minimise the
297 * loss of efficiency due to exception service serialization).
298 * An improved version would pick up configuration information and
299 * possibly leave some TCs/VPEs as "slave" processors.
301 * Use c0_MVPConf0 to find out how many TCs are available, setting up
302 * cpu_possible_mask and the logical/physical mappings.
305 int __init smtc_build_cpu_map(int start_cpu_slot)
310 * The CPU map isn't actually used for anything at this point,
311 * so it's not clear what else we should do apart from set
312 * everything up so that "logical" = "physical".
314 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
315 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
316 set_cpu_possible(i, true);
317 __cpu_number_map[i] = i;
318 __cpu_logical_map[i] = i;
320 #ifdef CONFIG_MIPS_MT_FPAFF
321 /* Initialize map of CPUs with FPUs */
322 cpus_clear(mt_fpu_cpumask);
325 /* One of those TC's is the one booting, and not a secondary... */
326 printk("%i available secondary CPU TC(s)\n", i - 1);
332 * Common setup before any secondaries are started
333 * Make sure all CPUs are in a sensible state before we boot any of the
336 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
337 * as possible across the available VPEs.
340 static void smtc_tc_setup(int vpe, int tc, int cpu)
342 static int cp1contexts[MAX_SMTC_VPES];
345 * Make a local copy of the available FPU contexts in order
346 * to keep track of TCs that can have one.
351 * FIXME: Multi-core SMTC hasn't been tested and the
352 * maximum number of VPEs may change.
354 cp1contexts[0] = smtc_nconf1[0] - 1;
355 cp1contexts[1] = smtc_nconf1[1];
359 write_tc_c0_tchalt(TCHALT_H);
361 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
362 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
365 * TCContext gets an offset from the base of the IPIQ array
366 * to be used in low-level code to detect the presence of
367 * an active IPI queue.
369 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
371 /* Bind TC to VPE. */
372 write_tc_c0_tcbind(vpe);
374 /* In general, all TCs should have the same cpu_data indications. */
375 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
377 /* Check to see if there is a FPU context available for this TC. */
378 if (!cp1contexts[vpe])
379 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
383 /* Store the TC and VPE into the cpu_data structure. */
384 cpu_data[cpu].vpe_id = vpe;
385 cpu_data[cpu].tc_id = tc;
387 /* FIXME: Multi-core SMTC hasn't been tested, but be prepared. */
388 cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
392 * Tweak to get Count registers synced as closely as possible. The
393 * value seems good for 34K-class cores.
398 void smtc_prepare_cpus(int cpus)
400 int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
404 struct smtc_ipi *pipi;
406 /* disable interrupts so we can disable MT */
407 local_irq_save(flags);
408 /* disable MT so we can configure */
412 spin_lock_init(&freeIPIq.lock);
415 * We probably don't have as many VPEs as we do SMP "CPUs",
416 * but it's possible - and in any case we'll never use more!
418 for (i=0; i<NR_CPUS; i++) {
419 IPIQ[i].head = IPIQ[i].tail = NULL;
420 spin_lock_init(&IPIQ[i].lock);
422 IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
425 /* cpu_data index starts at zero */
427 cpu_data[cpu].vpe_id = 0;
428 cpu_data[cpu].tc_id = 0;
429 cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
432 /* Report on boot-time options */
433 mips_mt_set_cpuoptions();
435 printk("Limit of %d VPEs set\n", vpelimit);
437 printk("Limit of %d TCs set\n", tclimit);
439 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
442 printk("ASID mask value override to 0x%x\n", asidmask);
445 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
447 printk("Logic Analyser Trigger on suspected TC hang\n");
448 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
450 /* Put MVPE's into 'configuration state' */
451 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
453 val = read_c0_mvpconf0();
454 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
455 if (vpelimit > 0 && nvpe > vpelimit)
457 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
460 if (tclimit > 0 && ntc > tclimit)
463 for (i = 0; i < nvpe; i++) {
464 tcpervpe[i] = ntc / nvpe;
466 if((slop - i) > 0) tcpervpe[i]++;
469 /* Handle command line override for VPE0 */
470 if (vpe0limit > ntc) vpe0limit = ntc;
473 if (vpe0limit < tcpervpe[0]) {
474 /* Reducing TC count - distribute to others */
475 slop = tcpervpe[0] - vpe0limit;
476 slopslop = slop % (nvpe - 1);
477 tcpervpe[0] = vpe0limit;
478 for (i = 1; i < nvpe; i++) {
479 tcpervpe[i] += slop / (nvpe - 1);
480 if(slopslop && ((slopslop - (i - 1) > 0)))
483 } else if (vpe0limit > tcpervpe[0]) {
484 /* Increasing TC count - steal from others */
485 slop = vpe0limit - tcpervpe[0];
486 slopslop = slop % (nvpe - 1);
487 tcpervpe[0] = vpe0limit;
488 for (i = 1; i < nvpe; i++) {
489 tcpervpe[i] -= slop / (nvpe - 1);
490 if(slopslop && ((slopslop - (i - 1) > 0)))
496 /* Set up shared TLB */
497 smtc_configure_tlb();
499 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
500 /* Get number of CP1 contexts for each VPE. */
504 * Do not call settc() for TC0 or the FPU context
505 * value will be incorrect. Besides, we know that
508 smtc_nconf1[0] = ((read_vpe_c0_vpeconf1() &
509 VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
513 smtc_nconf1[1] = ((read_vpe_c0_vpeconf1() &
514 VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
518 if (tcpervpe[vpe] == 0)
522 printk("VPE %d: TC", vpe);
523 for (i = 0; i < tcpervpe[vpe]; i++) {
525 * TC 0 is bound to VPE 0 at reset,
526 * and is presumably executing this
527 * code. Leave it alone!
530 smtc_tc_setup(vpe, tc, cpu);
533 * Set MVP bit (possibly again). Do it
534 * here to catch CPUs that have no TCs
535 * bound to the VPE at reset. In that
536 * case, a TC must be bound to the VPE
537 * before we can set VPEControl[MVP]
539 write_vpe_c0_vpeconf0(
540 read_vpe_c0_vpeconf0() |
550 * Allow this VPE to control others.
552 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
556 * Clear any stale software interrupts from VPE's Cause
558 write_vpe_c0_cause(0);
561 * Clear ERL/EXL of VPEs other than 0
562 * and set restricted interrupt enable/mask.
564 write_vpe_c0_status((read_vpe_c0_status()
565 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
566 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
569 * set config to be the same as vpe0,
570 * particularly kseg0 coherency alg
572 write_vpe_c0_config(read_c0_config());
573 /* Clear any pending timer interrupt */
574 write_vpe_c0_compare(0);
575 /* Propagate Config7 */
576 write_vpe_c0_config7(read_c0_config7());
577 write_vpe_c0_count(read_c0_count() + CP0_SKEW);
580 /* enable multi-threading within VPE */
581 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
583 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
587 * Pull any physically present but unused TCs out of circulation.
589 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
590 set_cpu_possible(tc, false);
591 set_cpu_present(tc, false);
595 /* release config state */
596 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
600 /* Set up coprocessor affinity CPU mask(s) */
602 #ifdef CONFIG_MIPS_MT_FPAFF
603 for (tc = 0; tc < ntc; tc++) {
604 if (cpu_data[tc].options & MIPS_CPU_FPU)
605 cpu_set(tc, mt_fpu_cpumask);
609 /* set up ipi interrupts... */
611 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
613 setup_cross_vpe_interrupts(nvpe);
615 /* Set up queue of free IPI "messages". */
616 nipi = NR_CPUS * IPIBUF_PER_CPU;
620 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
622 panic("kmalloc of IPI message buffers failed");
624 printk("IPI buffer pool of %d buffers\n", nipi);
625 for (i = 0; i < nipi; i++) {
626 smtc_ipi_nq(&freeIPIq, pipi);
630 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
633 local_irq_restore(flags);
634 /* Initialize SMTC /proc statistics/diagnostics */
640 * Setup the PC, SP, and GP of a secondary processor and start it
642 * smp_bootstrap is the place to resume from
643 * __KSTK_TOS(idle) is apparently the stack pointer
644 * (unsigned long)idle->thread_info the gp
647 void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
649 extern u32 kernelsp[NR_CPUS];
654 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
657 settc(cpu_data[cpu].tc_id);
660 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
663 kernelsp[cpu] = __KSTK_TOS(idle);
664 write_tc_gpr_sp(__KSTK_TOS(idle));
667 write_tc_gpr_gp((unsigned long)task_thread_info(idle));
669 smtc_status |= SMTC_MTC_ACTIVE;
670 write_tc_c0_tchalt(0);
671 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
677 void smtc_init_secondary(void)
681 void smtc_smp_finish(void)
683 int cpu = smp_processor_id();
686 * Lowest-numbered CPU per VPE starts a clock tick.
687 * Like per_cpu_trap_init() hack, this assumes that
688 * SMTC init code assigns TCs consdecutively and
689 * in ascending order across available VPEs.
691 if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
692 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
696 printk("TC %d going on-line as CPU %d\n",
697 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
700 void smtc_cpus_done(void)
705 * Support for SMTC-optimized driver IRQ registration
709 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
710 * in do_IRQ. These are passed in setup_irq_smtc() and stored
714 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
715 unsigned long hwmask)
717 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
718 unsigned int vpe = current_cpu_data.vpe_id;
720 vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1;
722 irq_hwmask[irq] = hwmask;
724 return setup_irq(irq, new);
727 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
729 * Support for IRQ affinity to TCs
732 void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
735 * If a "fast path" cache of quickly decodable affinity state
736 * is maintained, this is where it gets done, on a call up
737 * from the platform affinity code.
741 void smtc_forward_irq(struct irq_data *d)
743 unsigned int irq = d->irq;
747 * OK wise guy, now figure out how to get the IRQ
748 * to be serviced on an authorized "CPU".
750 * Ideally, to handle the situation where an IRQ has multiple
751 * eligible CPUS, we would maintain state per IRQ that would
752 * allow a fair distribution of service requests. Since the
753 * expected use model is any-or-only-one, for simplicity
754 * and efficiency, we just pick the easiest one to find.
757 target = cpumask_first(d->affinity);
760 * We depend on the platform code to have correctly processed
761 * IRQ affinity change requests to ensure that the IRQ affinity
762 * mask has been purged of bits corresponding to nonexistent and
763 * offline "CPUs", and to TCs bound to VPEs other than the VPE
764 * connected to the physical interrupt input for the interrupt
765 * in question. Otherwise we have a nasty problem with interrupt
766 * mask management. This is best handled in non-performance-critical
767 * platform IRQ affinity setting code, to minimize interrupt-time
771 /* If no one is eligible, service locally */
772 if (target >= NR_CPUS)
773 do_IRQ_no_affinity(irq);
775 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
778 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
781 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
782 * Within a VPE one TC can interrupt another by different approaches.
783 * The easiest to get right would probably be to make all TCs except
784 * the target IXMT and set a software interrupt, but an IXMT-based
785 * scheme requires that a handler must run before a new IPI could
786 * be sent, which would break the "broadcast" loops in MIPS MT.
787 * A more gonzo approach within a VPE is to halt the TC, extract
788 * its Restart, Status, and a couple of GPRs, and program the Restart
789 * address to emulate an interrupt.
791 * Within a VPE, one can be confident that the target TC isn't in
792 * a critical EXL state when halted, since the write to the Halt
793 * register could not have issued on the writing thread if the
794 * halting thread had EXL set. So k0 and k1 of the target TC
795 * can be used by the injection code. Across VPEs, one can't
796 * be certain that the target TC isn't in a critical exception
797 * state. So we try a two-step process of sending a software
798 * interrupt to the target VPE, which either handles the event
799 * itself (if it was the target) or injects the event within
803 static void smtc_ipi_qdump(void)
806 struct smtc_ipi *temp;
808 for (i = 0; i < NR_CPUS ;i++) {
809 pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
810 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
814 while (temp != IPIQ[i].tail) {
815 pr_debug("%d %d %d: ", temp->type, temp->dest,
817 #ifdef SMTC_IPI_DEBUG
818 pr_debug("%u %lu\n", temp->sender, temp->stamp);
828 * The standard atomic.h primitives don't quite do what we want
829 * here: We need an atomic add-and-return-previous-value (which
830 * could be done with atomic_add_return and a decrement) and an
831 * atomic set/zero-and-return-previous-value (which can't really
832 * be done with the atomic.h primitives). And since this is
833 * MIPS MT, we can assume that we have LL/SC.
835 static inline int atomic_postincrement(atomic_t *v)
837 unsigned long result;
841 __asm__ __volatile__(
847 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
854 void smtc_send_ipi(int cpu, int type, unsigned int action)
857 struct smtc_ipi *pipi;
860 unsigned long tcrestart;
861 extern void r4k_wait_irqoff(void), __pastwait(void);
862 int set_resched_flag = (type == LINUX_SMP_IPI &&
863 action == SMP_RESCHEDULE_YOURSELF);
865 if (cpu == smp_processor_id()) {
866 printk("Cannot Send IPI to self!\n");
869 if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
870 return; /* There is a reschedule queued already */
872 /* Set up a descriptor, to be delivered either promptly or queued */
873 pipi = smtc_ipi_dq(&freeIPIq);
876 mips_mt_regdump(dvpe());
877 panic("IPI Msg. Buffers Depleted");
880 pipi->arg = (void *)action;
882 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
883 /* If not on same VPE, enqueue and send cross-VPE interrupt */
884 IPIQ[cpu].resched_flag |= set_resched_flag;
885 smtc_ipi_nq(&IPIQ[cpu], pipi);
887 settc(cpu_data[cpu].tc_id);
888 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
892 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
893 * since ASID shootdown on the other VPE may
894 * collide with this operation.
897 settc(cpu_data[cpu].tc_id);
898 /* Halt the targeted TC */
899 write_tc_c0_tchalt(TCHALT_H);
903 * Inspect TCStatus - if IXMT is set, we have to queue
904 * a message. Otherwise, we set up the "interrupt"
907 tcstatus = read_tc_c0_tcstatus();
909 if ((tcstatus & TCSTATUS_IXMT) != 0) {
911 * If we're in the the irq-off version of the wait
912 * loop, we need to force exit from the wait and
913 * do a direct post of the IPI.
915 if (cpu_wait == r4k_wait_irqoff) {
916 tcrestart = read_tc_c0_tcrestart();
917 if (tcrestart >= (unsigned long)r4k_wait_irqoff
918 && tcrestart < (unsigned long)__pastwait) {
919 write_tc_c0_tcrestart(__pastwait);
920 tcstatus &= ~TCSTATUS_IXMT;
921 write_tc_c0_tcstatus(tcstatus);
926 * Otherwise we queue the message for the target TC
927 * to pick up when he does a local_irq_restore()
929 write_tc_c0_tchalt(0);
931 IPIQ[cpu].resched_flag |= set_resched_flag;
932 smtc_ipi_nq(&IPIQ[cpu], pipi);
935 post_direct_ipi(cpu, pipi);
936 write_tc_c0_tchalt(0);
943 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
945 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
947 struct pt_regs *kstack;
948 unsigned long tcstatus;
949 unsigned long tcrestart;
950 extern u32 kernelsp[NR_CPUS];
951 extern void __smtc_ipi_vector(void);
952 //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
954 /* Extract Status, EPC from halted TC */
955 tcstatus = read_tc_c0_tcstatus();
956 tcrestart = read_tc_c0_tcrestart();
957 /* If TCRestart indicates a WAIT instruction, advance the PC */
958 if ((tcrestart & 0x80000000)
959 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
963 * Save on TC's future kernel stack
965 * CU bit of Status is indicator that TC was
966 * already running on a kernel stack...
968 if (tcstatus & ST0_CU0) {
969 /* Note that this "- 1" is pointer arithmetic */
970 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
972 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
975 kstack->cp0_epc = (long)tcrestart;
977 kstack->cp0_tcstatus = tcstatus;
978 /* Pass token of operation to be performed kernel stack pad area */
979 kstack->pad0[4] = (unsigned long)pipi;
980 /* Pass address of function to be called likewise */
981 kstack->pad0[5] = (unsigned long)&ipi_decode;
982 /* Set interrupt exempt and kernel mode */
983 tcstatus |= TCSTATUS_IXMT;
984 tcstatus &= ~TCSTATUS_TKSU;
985 write_tc_c0_tcstatus(tcstatus);
987 /* Set TC Restart address to be SMTC IPI vector */
988 write_tc_c0_tcrestart(__smtc_ipi_vector);
991 static void ipi_resched_interrupt(void)
996 static void ipi_call_interrupt(void)
998 /* Invoke generic function invocation code in smp.c */
999 smp_call_function_interrupt();
1002 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
1004 static void __irq_entry smtc_clock_tick_interrupt(void)
1006 unsigned int cpu = smp_processor_id();
1007 struct clock_event_device *cd;
1008 int irq = MIPS_CPU_IRQ_BASE + 1;
1011 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
1012 cd = &per_cpu(mips_clockevent_device, cpu);
1013 cd->event_handler(cd);
1017 void ipi_decode(struct smtc_ipi *pipi)
1019 void *arg_copy = pipi->arg;
1020 int type_copy = pipi->type;
1022 smtc_ipi_nq(&freeIPIq, pipi);
1024 switch (type_copy) {
1025 case SMTC_CLOCK_TICK:
1026 smtc_clock_tick_interrupt();
1030 switch ((int)arg_copy) {
1031 case SMP_RESCHEDULE_YOURSELF:
1032 ipi_resched_interrupt();
1034 case SMP_CALL_FUNCTION:
1035 ipi_call_interrupt();
1038 printk("Impossible SMTC IPI Argument %p\n", arg_copy);
1042 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
1043 case IRQ_AFFINITY_IPI:
1045 * Accept a "forwarded" interrupt that was initially
1046 * taken by a TC who doesn't have affinity for the IRQ.
1048 do_IRQ_no_affinity((int)arg_copy);
1050 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
1052 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
1058 * Similar to smtc_ipi_replay(), but invoked from context restore,
1059 * so it reuses the current exception frame rather than set up a
1060 * new one with self_ipi.
1063 void deferred_smtc_ipi(void)
1065 int cpu = smp_processor_id();
1068 * Test is not atomic, but much faster than a dequeue,
1069 * and the vast majority of invocations will have a null queue.
1070 * If irq_disabled when this was called, then any IPIs queued
1071 * after we test last will be taken on the next irq_enable/restore.
1072 * If interrupts were enabled, then any IPIs added after the
1073 * last test will be taken directly.
1076 while (IPIQ[cpu].head != NULL) {
1077 struct smtc_ipi_q *q = &IPIQ[cpu];
1078 struct smtc_ipi *pipi;
1079 unsigned long flags;
1082 * It may be possible we'll come in with interrupts
1085 local_irq_save(flags);
1086 spin_lock(&q->lock);
1087 pipi = __smtc_ipi_dq(q);
1088 spin_unlock(&q->lock);
1090 if (pipi->type == LINUX_SMP_IPI &&
1091 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1092 IPIQ[cpu].resched_flag = 0;
1096 * The use of the __raw_local restore isn't
1097 * as obviously necessary here as in smtc_ipi_replay(),
1098 * but it's more efficient, given that we're already
1099 * running down the IPI queue.
1101 __arch_local_irq_restore(flags);
1106 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
1107 * set via cross-VPE MTTR manipulation of the Cause register. It would be
1108 * in some regards preferable to have external logic for "doorbell" hardware
1112 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
1114 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1116 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
1117 int my_tc = cpu_data[smp_processor_id()].tc_id;
1119 struct smtc_ipi *pipi;
1120 unsigned long tcstatus;
1122 unsigned long flags;
1123 unsigned int mtflags;
1124 unsigned int vpflags;
1127 * So long as cross-VPE interrupts are done via
1128 * MFTR/MTTR read-modify-writes of Cause, we need
1129 * to stop other VPEs whenever the local VPE does
1132 local_irq_save(flags);
1134 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
1135 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
1136 irq_enable_hazard();
1138 local_irq_restore(flags);
1141 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
1142 * queued for TCs on this VPE other than the current one.
1143 * Return-from-interrupt should cause us to drain the queue
1144 * for the current TC, so we ought not to have to do it explicitly here.
1147 for_each_online_cpu(cpu) {
1148 if (cpu_data[cpu].vpe_id != my_vpe)
1151 pipi = smtc_ipi_dq(&IPIQ[cpu]);
1153 if (cpu_data[cpu].tc_id != my_tc) {
1156 settc(cpu_data[cpu].tc_id);
1157 write_tc_c0_tchalt(TCHALT_H);
1159 tcstatus = read_tc_c0_tcstatus();
1160 if ((tcstatus & TCSTATUS_IXMT) == 0) {
1161 post_direct_ipi(cpu, pipi);
1164 write_tc_c0_tchalt(0);
1167 smtc_ipi_req(&IPIQ[cpu], pipi);
1171 * ipi_decode() should be called
1172 * with interrupts off
1174 local_irq_save(flags);
1175 if (pipi->type == LINUX_SMP_IPI &&
1176 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1177 IPIQ[cpu].resched_flag = 0;
1179 local_irq_restore(flags);
1187 static void ipi_irq_dispatch(void)
1189 do_IRQ(cpu_ipi_irq);
1192 static struct irqaction irq_ipi = {
1193 .handler = ipi_interrupt,
1194 .flags = IRQF_PERCPU,
1198 static void setup_cross_vpe_interrupts(unsigned int nvpe)
1204 panic("SMTC Kernel requires Vectored Interrupt support");
1206 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
1208 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1210 irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
1214 * SMTC-specific hacks invoked from elsewhere in the kernel.
1218 * smtc_ipi_replay is called from raw_local_irq_restore
1221 void smtc_ipi_replay(void)
1223 unsigned int cpu = smp_processor_id();
1226 * To the extent that we've ever turned interrupts off,
1227 * we may have accumulated deferred IPIs. This is subtle.
1228 * we should be OK: If we pick up something and dispatch
1229 * it here, that's great. If we see nothing, but concurrent
1230 * with this operation, another TC sends us an IPI, IXMT
1231 * is clear, and we'll handle it as a real pseudo-interrupt
1232 * and not a pseudo-pseudo interrupt. The important thing
1233 * is to do the last check for queued message *after* the
1234 * re-enabling of interrupts.
1236 while (IPIQ[cpu].head != NULL) {
1237 struct smtc_ipi_q *q = &IPIQ[cpu];
1238 struct smtc_ipi *pipi;
1239 unsigned long flags;
1242 * It's just possible we'll come in with interrupts
1245 local_irq_save(flags);
1247 spin_lock(&q->lock);
1248 pipi = __smtc_ipi_dq(q);
1249 spin_unlock(&q->lock);
1251 ** But use a raw restore here to avoid recursion.
1253 __arch_local_irq_restore(flags);
1257 smtc_cpu_stats[cpu].selfipis++;
1262 EXPORT_SYMBOL(smtc_ipi_replay);
1264 void smtc_idle_loop_hook(void)
1266 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1275 * printk within DMT-protected regions can deadlock,
1276 * so buffer diagnostic messages for later output.
1279 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1281 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1282 if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1284 /* Tedious stuff to just do once */
1285 mvpconf0 = read_c0_mvpconf0();
1286 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1287 if (hook_ntcs > NR_CPUS)
1288 hook_ntcs = NR_CPUS;
1289 for (tc = 0; tc < hook_ntcs; tc++) {
1291 clock_hang_reported[tc] = 0;
1293 for (vpe = 0; vpe < 2; vpe++)
1294 for (im = 0; im < 8; im++)
1295 imstuckcount[vpe][im] = 0;
1296 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1297 atomic_set(&idle_hook_initialized, 1000);
1299 /* Someone else is initializing in parallel - let 'em finish */
1300 while (atomic_read(&idle_hook_initialized) < 1000)
1305 /* Have we stupidly left IXMT set somewhere? */
1306 if (read_c0_tcstatus() & 0x400) {
1307 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1309 printk("Dangling IXMT in cpu_idle()\n");
1312 /* Have we stupidly left an IM bit turned off? */
1313 #define IM_LIMIT 2000
1314 local_irq_save(flags);
1316 pdb_msg = &id_ho_db_msg[0];
1317 im = read_c0_status();
1318 vpe = current_cpu_data.vpe_id;
1319 for (bit = 0; bit < 8; bit++) {
1321 * In current prototype, I/O interrupts
1322 * are masked for VPE > 0
1324 if (vpemask[vpe][bit]) {
1325 if (!(im & (0x100 << bit)))
1326 imstuckcount[vpe][bit]++;
1328 imstuckcount[vpe][bit] = 0;
1329 if (imstuckcount[vpe][bit] > IM_LIMIT) {
1330 set_c0_status(0x100 << bit);
1332 imstuckcount[vpe][bit] = 0;
1333 pdb_msg += sprintf(pdb_msg,
1334 "Dangling IM %d fixed for VPE %d\n", bit,
1341 local_irq_restore(flags);
1342 if (pdb_msg != &id_ho_db_msg[0])
1343 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1344 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1349 void smtc_soft_dump(void)
1353 printk("Counter Interrupts taken per CPU (TC)\n");
1354 for (i=0; i < NR_CPUS; i++) {
1355 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1357 printk("Self-IPI invocations:\n");
1358 for (i=0; i < NR_CPUS; i++) {
1359 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1362 printk("%d Recoveries of \"stolen\" FPU\n",
1363 atomic_read(&smtc_fpu_recoveries));
1368 * TLB management routines special to SMTC
1371 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1373 unsigned long flags, mtflags, tcstat, prevhalt, asid;
1377 * It would be nice to be able to use a spinlock here,
1378 * but this is invoked from within TLB flush routines
1379 * that protect themselves with DVPE, so if a lock is
1380 * held by another TC, it'll never be freed.
1382 * DVPE/DMT must not be done with interrupts enabled,
1383 * so even so most callers will already have disabled
1384 * them, let's be really careful...
1387 local_irq_save(flags);
1388 if (smtc_status & SMTC_TLB_SHARED) {
1393 tlb = cpu_data[cpu].vpe_id;
1395 asid = asid_cache(cpu);
1398 if (!((asid += ASID_INC) & ASID_MASK) ) {
1399 if (cpu_has_vtag_icache)
1401 /* Traverse all online CPUs (hack requires contiguous range) */
1402 for_each_online_cpu(i) {
1404 * We don't need to worry about our own CPU, nor those of
1405 * CPUs who don't share our TLB.
1407 if ((i != smp_processor_id()) &&
1408 ((smtc_status & SMTC_TLB_SHARED) ||
1409 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1410 settc(cpu_data[i].tc_id);
1411 prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1413 write_tc_c0_tchalt(TCHALT_H);
1416 tcstat = read_tc_c0_tcstatus();
1417 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1419 write_tc_c0_tchalt(0);
1422 if (!asid) /* fix version if needed */
1423 asid = ASID_FIRST_VERSION;
1424 local_flush_tlb_all(); /* start new asid cycle */
1426 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1429 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1431 for_each_online_cpu(i) {
1432 if ((smtc_status & SMTC_TLB_SHARED) ||
1433 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1434 cpu_context(i, mm) = asid_cache(i) = asid;
1437 if (smtc_status & SMTC_TLB_SHARED)
1441 local_irq_restore(flags);
1445 * Invoked from macros defined in mmu_context.h
1446 * which must already have disabled interrupts
1447 * and done a DVPE or DMT as appropriate.
1450 void smtc_flush_tlb_asid(unsigned long asid)
1455 entry = read_c0_wired();
1457 /* Traverse all non-wired entries */
1458 while (entry < current_cpu_data.tlbsize) {
1459 write_c0_index(entry);
1463 ehi = read_c0_entryhi();
1464 if ((ehi & ASID_MASK) == asid) {
1466 * Invalidate only entries with specified ASID,
1467 * makiing sure all entries differ.
1469 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1470 write_c0_entrylo0(0);
1471 write_c0_entrylo1(0);
1473 tlb_write_indexed();
1477 write_c0_index(PARKED_INDEX);
1482 * Support for single-threading cache flush operations.
1485 static int halt_state_save[NR_CPUS];
1488 * To really, really be sure that nothing is being done
1489 * by other TCs, halt them all. This code assumes that
1490 * a DVPE has already been done, so while their Halted
1491 * state is theoretically architecturally unstable, in
1492 * practice, it's not going to change while we're looking
1496 void smtc_cflush_lockdown(void)
1500 for_each_online_cpu(cpu) {
1501 if (cpu != smp_processor_id()) {
1502 settc(cpu_data[cpu].tc_id);
1503 halt_state_save[cpu] = read_tc_c0_tchalt();
1504 write_tc_c0_tchalt(TCHALT_H);
1510 /* It would be cheating to change the cpu_online states during a flush! */
1512 void smtc_cflush_release(void)
1517 * Start with a hazard barrier to ensure
1518 * that all CACHE ops have played through.
1522 for_each_online_cpu(cpu) {
1523 if (cpu != smp_processor_id()) {
1524 settc(cpu_data[cpu].tc_id);
1525 write_tc_c0_tchalt(halt_state_save[cpu]);