arch/mips/kernel/smp-bmips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
   7  *
   8  * SMP support for BMIPS
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/sched/hotplug.h>
  14 #include <linux/sched/task_stack.h>
  15 #include <linux/mm.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/reboot.h>
  23 #include <linux/io.h>
  24 #include <linux/compiler.h>
  25 #include <linux/linkage.h>
  26 #include <linux/bug.h>
  27 #include <linux/kernel.h>
  28 #include <linux/kexec.h>
  29
  30 #include <asm/time.h>
  31 #include <asm/processor.h>
  32 #include <asm/bootinfo.h>
  33 #include <asm/cacheflush.h>
  34 #include <asm/tlbflush.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/bmips.h>
  37 #include <asm/traps.h>
  38 #include <asm/barrier.h>
  39 #include <asm/cpu-features.h>
  40
  41 static int __maybe_unused max_cpus = 1;
  42
  43 /* these may be configured by the platform code */
  44 int bmips_smp_enabled = 1;
  45 int bmips_cpu_offset;
  46 cpumask_t bmips_booted_mask;
  47 unsigned long bmips_tp1_irqs = IE_IRQ1;
  48
  49 #define RESET_FROM_KSEG0                0x80080800
  50 #define RESET_FROM_KSEG1                0xa0080800
  51
  52 static void bmips_set_reset_vec(int cpu, u32 val);
  53
  54 #ifdef CONFIG_SMP
  55
  56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  57 unsigned long bmips_smp_boot_sp;
  58 unsigned long bmips_smp_boot_gp;
  59
  60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
  61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
  62 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
  63 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
  64
  65 /* SW interrupts 0,1 are used for interprocessor signaling */
  66 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
  67 #define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
  68
  69 #define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
  70 #define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  71 #define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  72 #define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
  73
  74 static void __init bmips_smp_setup(void)
  75 {
  76         int i, cpu = 1, boot_cpu = 0;
  77         int cpu_hw_intr;
  78
  79         switch (current_cpu_type()) {
  80         case CPU_BMIPS4350:
  81         case CPU_BMIPS4380:
  82                 /* arbitration priority */
  83                 clear_c0_brcm_cmt_ctrl(0x30);
  84
  85                 /* NBK and weak order flags */
  86                 set_c0_brcm_config_0(0x30000);
  87
  88                 /* Find out if we are running on TP0 or TP1 */
  89                 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  90
  91                 /*
  92                  * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
  93                  * thread
  94                  * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  95                  * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  96                  */
  97                 if (boot_cpu == 0)
  98                         cpu_hw_intr = 0x02;
  99                 else
 100                         cpu_hw_intr = 0x1d;
 101
 102                 change_c0_brcm_cmt_intr(0xf8018000,
 103                                         (cpu_hw_intr << 27) | (0x03 << 15));
 104
 105                 /* single core, 2 threads (2 pipelines) */
 106                 max_cpus = 2;
 107
 108                 break;
 109         case CPU_BMIPS5000:
 110                 /* enable raceless SW interrupts */
 111                 set_c0_brcm_config(0x03 << 22);
 112
 113                 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
 114                 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
 115
 116                 /* N cores, 2 threads per core */
 117                 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
 118
 119                 /* clear any pending SW interrupts */
 120                 for (i = 0; i < max_cpus; i++) {
 121                         write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
 122                         write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
 123                 }
 124
 125                 break;
 126         default:
 127                 max_cpus = 1;
 128         }
 129
 130         if (!bmips_smp_enabled)
 131                 max_cpus = 1;
 132
 133         /* this can be overridden by the BSP */
 134         if (!board_ebase_setup)
 135                 board_ebase_setup = &bmips_ebase_setup;
 136
 137         if (max_cpus > 1) {
 138                 __cpu_number_map[boot_cpu] = 0;
 139                 __cpu_logical_map[0] = boot_cpu;
 140
 141                 for (i = 0; i < max_cpus; i++) {
 142                         if (i != boot_cpu) {
 143                                 __cpu_number_map[i] = cpu;
 144                                 __cpu_logical_map[cpu] = i;
 145                                 cpu++;
 146                         }
 147                         set_cpu_possible(i, 1);
 148                         set_cpu_present(i, 1);
 149                 }
 150         } else {
 151                 __cpu_number_map[0] = boot_cpu;
 152                 __cpu_logical_map[0] = 0;
 153                 set_cpu_possible(0, 1);
 154                 set_cpu_present(0, 1);
 155         }
 156 }
 157
 158 /*
 159  * IPI IRQ setup - runs on CPU0
 160  */
 161 static void bmips_prepare_cpus(unsigned int max_cpus)
 162 {
 163         irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
 164
 165         switch (current_cpu_type()) {
 166         case CPU_BMIPS4350:
 167         case CPU_BMIPS4380:
 168                 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
 169                 break;
 170         case CPU_BMIPS5000:
 171                 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
 172                 break;
 173         default:
 174                 return;
 175         }
 176
 177         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
 178                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
 179                 panic("Can't request IPI0 interrupt");
 180         if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
 181                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
 182                 panic("Can't request IPI1 interrupt");
 183 }
 184
 185 /*
 186  * Tell the hardware to boot CPUx - runs on CPU0
 187  */
 188 static int bmips_boot_secondary(int cpu, struct task_struct *idle)
 189 {
 190         bmips_smp_boot_sp = __KSTK_TOS(idle);
 191         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
 192         mb();
 193
 194         /*
 195          * Initial boot sequence for secondary CPU:
 196          *   bmips_reset_nmi_vec @ a000_0000 ->
 197          *   bmips_smp_entry ->
 198          *   plat_wired_tlb_setup (cached function call; optional) ->
 199          *   start_secondary (cached jump)
 200          *
 201          * Warm restart sequence:
 202          *   play_dead WAIT loop ->
 203          *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
 204          *   eret to play_dead ->
 205          *   bmips_secondary_reentry ->
 206          *   start_secondary
 207          */
 208
 209         pr_info("SMP: Booting CPU%d...\n", cpu);
 210
 211         if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
 212                 /* kseg1 might not exist if this CPU enabled XKS01 */
 213                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 214
 215                 switch (current_cpu_type()) {
 216                 case CPU_BMIPS4350:
 217                 case CPU_BMIPS4380:
 218                         bmips43xx_send_ipi_single(cpu, 0);
 219                         break;
 220                 case CPU_BMIPS5000:
 221                         bmips5000_send_ipi_single(cpu, 0);
 222                         break;
 223                 }
 224         } else {
 225                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
 226
 227                 switch (current_cpu_type()) {
 228                 case CPU_BMIPS4350:
 229                 case CPU_BMIPS4380:
 230                         /* Reset slave TP1 if booting from TP0 */
 231                         if (cpu_logical_map(cpu) == 1)
 232                                 set_c0_brcm_cmt_ctrl(0x01);
 233                         break;
 234                 case CPU_BMIPS5000:
 235                         write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 236                         break;
 237                 }
 238                 cpumask_set_cpu(cpu, &bmips_booted_mask);
 239         }
 240
 241         return 0;
 242 }
 243
 244 /*
 245  * Early setup - runs on secondary CPU after cache probe
 246  */
 247 static void bmips_init_secondary(void)
 248 {
 249         bmips_cpu_setup();
 250
 251         switch (current_cpu_type()) {
 252         case CPU_BMIPS4350:
 253         case CPU_BMIPS4380:
 254                 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 255                 break;
 256         case CPU_BMIPS5000:
 257                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 258                 cpu_set_core(&current_cpu_data, (read_c0_brcm_config() >> 25) & 3);
 259                 break;
 260         }
 261 }
 262
 263 /*
 264  * Late setup - runs on secondary CPU before entering the idle loop
 265  */
 266 static void bmips_smp_finish(void)
 267 {
 268         pr_info("SMP: CPU%d is running\n", smp_processor_id());
 269
 270         /* make sure there won't be a timer interrupt for a little while */
 271         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 272
 273         irq_enable_hazard();
 274         set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
 275         irq_enable_hazard();
 276 }
 277
 278 /*
 279  * BMIPS5000 raceless IPIs
 280  *
 281  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 282  * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 283  * IPI1 is used for SMP_CALL_FUNCTION
 284  */
 285
 286 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 287 {
 288         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 289 }
 290
 291 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 292 {
 293         int action = irq - IPI0_IRQ;
 294
 295         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
 296
 297         if (action == 0)
 298                 scheduler_ipi();
 299         else
 300                 generic_smp_call_function_interrupt();
 301
 302         return IRQ_HANDLED;
 303 }
 304
 305 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
 306         unsigned int action)
 307 {
 308         unsigned int i;
 309
 310         for_each_cpu(i, mask)
 311                 bmips5000_send_ipi_single(i, action);
 312 }
 313
 314 /*
 315  * BMIPS43xx racey IPIs
 316  *
 317  * We use one inbound SW IRQ for each CPU.
 318  *
 319  * A spinlock must be held in order to keep CPUx from accidentally clearing
 320  * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 321  * same spinlock is used to protect the action masks.
 322  */
 323
 324 static DEFINE_SPINLOCK(ipi_lock);
 325 static DEFINE_PER_CPU(int, ipi_action_mask);
 326
 327 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 328 {
 329         unsigned long flags;
 330
 331         spin_lock_irqsave(&ipi_lock, flags);
 332         set_c0_cause(cpu ? C_SW1 : C_SW0);
 333         per_cpu(ipi_action_mask, cpu) |= action;
 334         irq_enable_hazard();
 335         spin_unlock_irqrestore(&ipi_lock, flags);
 336 }
 337
 338 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 339 {
 340         unsigned long flags;
 341         int action, cpu = irq - IPI0_IRQ;
 342
 343         spin_lock_irqsave(&ipi_lock, flags);
 344         action = __this_cpu_read(ipi_action_mask);
 345         per_cpu(ipi_action_mask, cpu) = 0;
 346         clear_c0_cause(cpu ? C_SW1 : C_SW0);
 347         spin_unlock_irqrestore(&ipi_lock, flags);
 348
 349         if (action & SMP_RESCHEDULE_YOURSELF)
 350                 scheduler_ipi();
 351         if (action & SMP_CALL_FUNCTION)
 352                 generic_smp_call_function_interrupt();
 353
 354         return IRQ_HANDLED;
 355 }
 356
 357 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
 358         unsigned int action)
 359 {
 360         unsigned int i;
 361
 362         for_each_cpu(i, mask)
 363                 bmips43xx_send_ipi_single(i, action);
 364 }
 365
 366 #ifdef CONFIG_HOTPLUG_CPU
 367
 368 static int bmips_cpu_disable(void)
 369 {
 370         unsigned int cpu = smp_processor_id();
 371
 372         pr_info("SMP: CPU%d is offline\n", cpu);
 373
 374         set_cpu_online(cpu, false);
 375         calculate_cpu_foreign_map();
 376         irq_cpu_offline();
 377         clear_c0_status(IE_IRQ5);
 378
 379         local_flush_tlb_all();
 380         local_flush_icache_range(0, ~0);
 381
 382         return 0;
 383 }
 384
 385 static void bmips_cpu_die(unsigned int cpu)
 386 {
 387 }
 388
 389 void __ref play_dead(void)
 390 {
 391         idle_task_exit();
 392
 393         /* flush data cache */
 394         _dma_cache_wback_inv(0, ~0);
 395
 396         /*
 397          * Wakeup is on SW0 or SW1; disable everything else
 398          * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
 399          * IRQ handlers; this clears ST0_IE and returns immediately.
 400          */
 401         clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
 402         change_c0_status(
 403                 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 404                 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 405         irq_disable_hazard();
 406
 407         /*
 408          * wait for SW interrupt from bmips_boot_secondary(), then jump
 409          * back to start_secondary()
 410          */
 411         __asm__ __volatile__(
 412         "       wait\n"
 413         "       j       bmips_secondary_reentry\n"
 414         : : : "memory");
 415 }
 416
 417 #endif /* CONFIG_HOTPLUG_CPU */
 418
 419 const struct plat_smp_ops bmips43xx_smp_ops = {
 420         .smp_setup              = bmips_smp_setup,
 421         .prepare_cpus           = bmips_prepare_cpus,
 422         .boot_secondary         = bmips_boot_secondary,
 423         .smp_finish             = bmips_smp_finish,
 424         .init_secondary         = bmips_init_secondary,
 425         .send_ipi_single        = bmips43xx_send_ipi_single,
 426         .send_ipi_mask          = bmips43xx_send_ipi_mask,
 427 #ifdef CONFIG_HOTPLUG_CPU
 428         .cpu_disable            = bmips_cpu_disable,
 429         .cpu_die                = bmips_cpu_die,
 430 #endif
 431 #ifdef CONFIG_KEXEC
 432         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 433 #endif
 434 };
 435
 436 const struct plat_smp_ops bmips5000_smp_ops = {
 437         .smp_setup              = bmips_smp_setup,
 438         .prepare_cpus           = bmips_prepare_cpus,
 439         .boot_secondary         = bmips_boot_secondary,
 440         .smp_finish             = bmips_smp_finish,
 441         .init_secondary         = bmips_init_secondary,
 442         .send_ipi_single        = bmips5000_send_ipi_single,
 443         .send_ipi_mask          = bmips5000_send_ipi_mask,
 444 #ifdef CONFIG_HOTPLUG_CPU
 445         .cpu_disable            = bmips_cpu_disable,
 446         .cpu_die                = bmips_cpu_die,
 447 #endif
 448 #ifdef CONFIG_KEXEC
 449         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 450 #endif
 451 };
 452
 453 #endif /* CONFIG_SMP */
 454
 455 /***********************************************************************
 456  * BMIPS vector relocation
 457  * This is primarily used for SMP boot, but it is applicable to some
 458  * UP BMIPS systems as well.
 459  ***********************************************************************/
 460
 461 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 462 {
 463         memcpy((void *)dst, start, end - start);
 464         dma_cache_wback(dst, end - start);
 465         local_flush_icache_range(dst, dst + (end - start));
 466         instruction_hazard();
 467 }
 468
 469 static inline void bmips_nmi_handler_setup(void)
 470 {
 471         bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
 472                 bmips_reset_nmi_vec_end);
 473         bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
 474                 bmips_smp_int_vec_end);
 475 }
 476
 477 struct reset_vec_info {
 478         int cpu;
 479         u32 val;
 480 };
 481
 482 static void bmips_set_reset_vec_remote(void *vinfo)
 483 {
 484         struct reset_vec_info *info = vinfo;
 485         int shift = info->cpu & 0x01 ? 16 : 0;
 486         u32 mask = ~(0xffff << shift), val = info->val >> 16;
 487
 488         preempt_disable();
 489         if (smp_processor_id() > 0) {
 490                 smp_call_function_single(0, &bmips_set_reset_vec_remote,
 491                                          info, 1);
 492         } else {
 493                 if (info->cpu & 0x02) {
 494                         /* BMIPS5200 "should" use mask/shift, but it's buggy */
 495                         bmips_write_zscm_reg(0xa0, (val << 16) | val);
 496                         bmips_read_zscm_reg(0xa0);
 497                 } else {
 498                         write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
 499                                               (val << shift));
 500                 }
 501         }
 502         preempt_enable();
 503 }
 504
 505 static void bmips_set_reset_vec(int cpu, u32 val)
 506 {
 507         struct reset_vec_info info;
 508
 509         if (current_cpu_type() == CPU_BMIPS5000) {
 510                 /* this needs to run from CPU0 (which is always online) */
 511                 info.cpu = cpu;
 512                 info.val = val;
 513                 bmips_set_reset_vec_remote(&info);
 514         } else {
 515                 void __iomem *cbr = BMIPS_GET_CBR();
 516
 517                 if (cpu == 0)
 518                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
 519                 else {
 520                         if (current_cpu_type() != CPU_BMIPS4380)
 521                                 return;
 522                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
 523                 }
 524         }
 525         __sync();
 526         back_to_back_c0_hazard();
 527 }
 528
 529 void bmips_ebase_setup(void)
 530 {
 531         unsigned long new_ebase = ebase;
 532
 533         BUG_ON(ebase != CKSEG0);
 534
 535         switch (current_cpu_type()) {
 536         case CPU_BMIPS4350:
 537                 /*
 538                  * BMIPS4350 cannot relocate the normal vectors, but it
 539                  * can relocate the BEV=1 vectors.  So CPU1 starts up at
 540                  * the relocated BEV=1, IV=0 general exception vector @
 541                  * 0xa000_0380.
 542                  *
 543                  * set_uncached_handler() is used here because:
 544                  *  - CPU1 will run this from uncached space
 545                  *  - None of the cacheflush functions are set up yet
 546                  */
 547                 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
 548                         &bmips_smp_int_vec, 0x80);
 549                 __sync();
 550                 return;
 551         case CPU_BMIPS3300:
 552         case CPU_BMIPS4380:
 553                 /*
 554                  * 0x8000_0000: reset/NMI (initially in kseg1)
 555                  * 0x8000_0400: normal vectors
 556                  */
 557                 new_ebase = 0x80000400;
 558                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 559                 break;
 560         case CPU_BMIPS5000:
 561                 /*
 562                  * 0x8000_0000: reset/NMI (initially in kseg1)
 563                  * 0x8000_1000: normal vectors
 564                  */
 565                 new_ebase = 0x80001000;
 566                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 567                 write_c0_ebase(new_ebase);
 568                 break;
 569         default:
 570                 return;
 571         }
 572
 573         board_nmi_handler_setup = &bmips_nmi_handler_setup;
 574         ebase = new_ebase;
 575 }
 576
 577 asmlinkage void __weak plat_wired_tlb_setup(void)
 578 {
 579         /*
 580          * Called when starting/restarting a secondary CPU.
 581          * Kernel stacks and other important data might only be accessible
 582          * once the wired entries are present.
 583          */
 584 }
 585
 586 void bmips_cpu_setup(void)
 587 {
 588         void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
 589         u32 __maybe_unused cfg;
 590
 591         switch (current_cpu_type()) {
 592         case CPU_BMIPS3300:
 593                 /* Set BIU to async mode */
 594                 set_c0_brcm_bus_pll(BIT(22));
 595                 __sync();
 596
 597                 /* put the BIU back in sync mode */
 598                 clear_c0_brcm_bus_pll(BIT(22));
 599
 600                 /* clear BHTD to enable branch history table */
 601                 clear_c0_brcm_reset(BIT(16));
 602
 603                 /* Flush and enable RAC */
 604                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 605                 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
 606                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 607
 608                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 609                 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
 610                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 611
 612                 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 613                 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
 614                 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 615                 break;
 616
 617         case CPU_BMIPS4380:
 618                 /* CBG workaround for early BMIPS4380 CPUs */
 619                 switch (read_c0_prid()) {
 620                 case 0x2a040:
 621                 case 0x2a042:
 622                 case 0x2a044:
 623                 case 0x2a060:
 624                         cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
 625                         __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
 626                         __raw_readl(cbr + BMIPS_L2_CONFIG);
 627                 }
 628
 629                 /* clear BHTD to enable branch history table */
 630                 clear_c0_brcm_config_0(BIT(21));
 631
 632                 /* XI/ROTR enable */
 633                 set_c0_brcm_config_0(BIT(23));
 634                 set_c0_brcm_cmt_ctrl(BIT(15));
 635                 break;
 636
 637         case CPU_BMIPS5000:
 638                 /* enable RDHWR, BRDHWR */
 639                 set_c0_brcm_config(BIT(17) | BIT(21));
 640
 641                 /* Disable JTB */
 642                 __asm__ __volatile__(
 643                 "       .set    noreorder\n"
 644                 "       li      $8, 0x5a455048\n"
 645                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 646                 "       .word   0x4008b008\n"   /* mfc0 t0, $22, 8 */
 647                 "       li      $9, 0x00008000\n"
 648                 "       or      $8, $8, $9\n"
 649                 "       .word   0x4088b008\n"   /* mtc0 t0, $22, 8 */
 650                 "       sync\n"
 651                 "       li      $8, 0x0\n"
 652                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 653                 "       .set    reorder\n"
 654                 : : : "$8", "$9");
 655
 656                 /* XI enable */
 657                 set_c0_brcm_config(BIT(27));
 658
 659                 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
 660                 __asm__ __volatile__(
 661                 "       li      $8, 0x5a455048\n"
 662                 "       .word   0x4088b00f\n"   /* mtc0 $8, $22, 15 */
 663                 "       nop; nop; nop\n"
 664                 "       .word   0x4008b008\n"   /* mfc0 $8, $22, 8 */
 665                 "       lui     $9, 0x0100\n"
 666                 "       or      $8, $9\n"
 667                 "       .word   0x4088b008\n"   /* mtc0 $8, $22, 8 */
 668                 : : : "$8", "$9");
 669                 break;
 670         }
 671 }