arch/mips/kernel/ptrace.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Ross Biro
   7  * Copyright (C) Linus Torvalds
   8  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
   9  * Copyright (C) 1996 David S. Miller
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 1999 MIPS Technologies, Inc.
  12  * Copyright (C) 2000 Ulf Carlsson
  13  *
  14  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
  15  * binaries.
  16  */
  17 #include <linux/compiler.h>
  18 #include <linux/context_tracking.h>
  19 #include <linux/elf.h>
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/sched/task_stack.h>
  23 #include <linux/mm.h>
  24 #include <linux/errno.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/regset.h>
  27 #include <linux/smp.h>
  28 #include <linux/security.h>
  29 #include <linux/stddef.h>
  30 #include <linux/tracehook.h>
  31 #include <linux/audit.h>
  32 #include <linux/seccomp.h>
  33 #include <linux/ftrace.h>
  34
  35 #include <asm/byteorder.h>
  36 #include <asm/cpu.h>
  37 #include <asm/cpu-info.h>
  38 #include <asm/dsp.h>
  39 #include <asm/fpu.h>
  40 #include <asm/mipsregs.h>
  41 #include <asm/mipsmtregs.h>
  42 #include <asm/page.h>
  43 #include <asm/processor.h>
  44 #include <asm/syscall.h>
  45 #include <linux/uaccess.h>
  46 #include <asm/bootinfo.h>
  47 #include <asm/reg.h>
  48 #include <asm/branch.h>
  49
  50 #define CREATE_TRACE_POINTS
  51 #include <trace/events/syscalls.h>
  52
  53 #include "probes-common.h"
  54
  55 #define BREAKINST       0x0000000d
  56
  57 /*
  58  * Called by kernel/ptrace.c when detaching..
  59  *
  60  * Make sure single step bits etc are not set.
  61  */
  62 void ptrace_disable(struct task_struct *child)
  63 {
  64         /* Don't load the watchpoint registers for the ex-child. */
  65         clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
  66         user_disable_single_step(child);
  67 }
  68
  69 /*
  70  * Read a general register set.  We always use the 64-bit format, even
  71  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
  72  * Registers are sign extended to fill the available space.
  73  */
  74 int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
  75 {
  76         struct pt_regs *regs;
  77         int i;
  78
  79         if (!access_ok(data, 38 * 8))
  80                 return -EIO;
  81
  82         regs = task_pt_regs(child);
  83
  84         for (i = 0; i < 32; i++)
  85                 __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
  86         __put_user((long)regs->lo, (__s64 __user *)&data->lo);
  87         __put_user((long)regs->hi, (__s64 __user *)&data->hi);
  88         __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
  89         __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
  90         __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
  91         __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
  92
  93         return 0;
  94 }
  95
  96 /*
  97  * Write a general register set.  As for PTRACE_GETREGS, we always use
  98  * the 64-bit format.  On a 32-bit kernel only the lower order half
  99  * (according to endianness) will be used.
 100  */
 101 int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
 102 {
 103         struct pt_regs *regs;
 104         int i;
 105
 106         if (!access_ok(data, 38 * 8))
 107                 return -EIO;
 108
 109         regs = task_pt_regs(child);
 110
 111         for (i = 0; i < 32; i++)
 112                 __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
 113         __get_user(regs->lo, (__s64 __user *)&data->lo);
 114         __get_user(regs->hi, (__s64 __user *)&data->hi);
 115         __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
 116
 117         /* badvaddr, status, and cause may not be written.  */
 118
 119         /* System call number may have been changed */
 120         mips_syscall_update_nr(child, regs);
 121
 122         return 0;
 123 }
 124
 125 int ptrace_get_watch_regs(struct task_struct *child,
 126                           struct pt_watch_regs __user *addr)
 127 {
 128         enum pt_watch_style style;
 129         int i;
 130
 131         if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
 132                 return -EIO;
 133         if (!access_ok(addr, sizeof(struct pt_watch_regs)))
 134                 return -EIO;
 135
 136 #ifdef CONFIG_32BIT
 137         style = pt_watch_style_mips32;
 138 #define WATCH_STYLE mips32
 139 #else
 140         style = pt_watch_style_mips64;
 141 #define WATCH_STYLE mips64
 142 #endif
 143
 144         __put_user(style, &addr->style);
 145         __put_user(boot_cpu_data.watch_reg_use_cnt,
 146                    &addr->WATCH_STYLE.num_valid);
 147         for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
 148                 __put_user(child->thread.watch.mips3264.watchlo[i],
 149                            &addr->WATCH_STYLE.watchlo[i]);
 150                 __put_user(child->thread.watch.mips3264.watchhi[i] &
 151                                 (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW),
 152                            &addr->WATCH_STYLE.watchhi[i]);
 153                 __put_user(boot_cpu_data.watch_reg_masks[i],
 154                            &addr->WATCH_STYLE.watch_masks[i]);
 155         }
 156         for (; i < 8; i++) {
 157                 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
 158                 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
 159                 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
 160         }
 161
 162         return 0;
 163 }
 164
 165 int ptrace_set_watch_regs(struct task_struct *child,
 166                           struct pt_watch_regs __user *addr)
 167 {
 168         int i;
 169         int watch_active = 0;
 170         unsigned long lt[NUM_WATCH_REGS];
 171         u16 ht[NUM_WATCH_REGS];
 172
 173         if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
 174                 return -EIO;
 175         if (!access_ok(addr, sizeof(struct pt_watch_regs)))
 176                 return -EIO;
 177         /* Check the values. */
 178         for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
 179                 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
 180 #ifdef CONFIG_32BIT
 181                 if (lt[i] & __UA_LIMIT)
 182                         return -EINVAL;
 183 #else
 184                 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
 185                         if (lt[i] & 0xffffffff80000000UL)
 186                                 return -EINVAL;
 187                 } else {
 188                         if (lt[i] & __UA_LIMIT)
 189                                 return -EINVAL;
 190                 }
 191 #endif
 192                 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
 193                 if (ht[i] & ~MIPS_WATCHHI_MASK)
 194                         return -EINVAL;
 195         }
 196         /* Install them. */
 197         for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
 198                 if (lt[i] & MIPS_WATCHLO_IRW)
 199                         watch_active = 1;
 200                 child->thread.watch.mips3264.watchlo[i] = lt[i];
 201                 /* Set the G bit. */
 202                 child->thread.watch.mips3264.watchhi[i] = ht[i];
 203         }
 204
 205         if (watch_active)
 206                 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
 207         else
 208                 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
 209
 210         return 0;
 211 }
 212
 213 /* regset get/set implementations */
 214
 215 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
 216
 217 static int gpr32_get(struct task_struct *target,
 218                      const struct user_regset *regset,
 219                      struct membuf to)
 220 {
 221         struct pt_regs *regs = task_pt_regs(target);
 222         u32 uregs[ELF_NGREG] = {};
 223
 224         mips_dump_regs32(uregs, regs);
 225         return membuf_write(&to, uregs, sizeof(uregs));
 226 }
 227
 228 static int gpr32_set(struct task_struct *target,
 229                      const struct user_regset *regset,
 230                      unsigned int pos, unsigned int count,
 231                      const void *kbuf, const void __user *ubuf)
 232 {
 233         struct pt_regs *regs = task_pt_regs(target);
 234         u32 uregs[ELF_NGREG];
 235         unsigned start, num_regs, i;
 236         int err;
 237
 238         start = pos / sizeof(u32);
 239         num_regs = count / sizeof(u32);
 240
 241         if (start + num_regs > ELF_NGREG)
 242                 return -EIO;
 243
 244         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
 245                                  sizeof(uregs));
 246         if (err)
 247                 return err;
 248
 249         for (i = start; i < num_regs; i++) {
 250                 /*
 251                  * Cast all values to signed here so that if this is a 64-bit
 252                  * kernel, the supplied 32-bit values will be sign extended.
 253                  */
 254                 switch (i) {
 255                 case MIPS32_EF_R1 ... MIPS32_EF_R25:
 256                         /* k0/k1 are ignored. */
 257                 case MIPS32_EF_R28 ... MIPS32_EF_R31:
 258                         regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
 259                         break;
 260                 case MIPS32_EF_LO:
 261                         regs->lo = (s32)uregs[i];
 262                         break;
 263                 case MIPS32_EF_HI:
 264                         regs->hi = (s32)uregs[i];
 265                         break;
 266                 case MIPS32_EF_CP0_EPC:
 267                         regs->cp0_epc = (s32)uregs[i];
 268                         break;
 269                 }
 270         }
 271
 272         /* System call number may have been changed */
 273         mips_syscall_update_nr(target, regs);
 274
 275         return 0;
 276 }
 277
 278 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
 279
 280 #ifdef CONFIG_64BIT
 281
 282 static int gpr64_get(struct task_struct *target,
 283                      const struct user_regset *regset,
 284                      struct membuf to)
 285 {
 286         struct pt_regs *regs = task_pt_regs(target);
 287         u64 uregs[ELF_NGREG] = {};
 288
 289         mips_dump_regs64(uregs, regs);
 290         return membuf_write(&to, uregs, sizeof(uregs));
 291 }
 292
 293 static int gpr64_set(struct task_struct *target,
 294                      const struct user_regset *regset,
 295                      unsigned int pos, unsigned int count,
 296                      const void *kbuf, const void __user *ubuf)
 297 {
 298         struct pt_regs *regs = task_pt_regs(target);
 299         u64 uregs[ELF_NGREG];
 300         unsigned start, num_regs, i;
 301         int err;
 302
 303         start = pos / sizeof(u64);
 304         num_regs = count / sizeof(u64);
 305
 306         if (start + num_regs > ELF_NGREG)
 307                 return -EIO;
 308
 309         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
 310                                  sizeof(uregs));
 311         if (err)
 312                 return err;
 313
 314         for (i = start; i < num_regs; i++) {
 315                 switch (i) {
 316                 case MIPS64_EF_R1 ... MIPS64_EF_R25:
 317                         /* k0/k1 are ignored. */
 318                 case MIPS64_EF_R28 ... MIPS64_EF_R31:
 319                         regs->regs[i - MIPS64_EF_R0] = uregs[i];
 320                         break;
 321                 case MIPS64_EF_LO:
 322                         regs->lo = uregs[i];
 323                         break;
 324                 case MIPS64_EF_HI:
 325                         regs->hi = uregs[i];
 326                         break;
 327                 case MIPS64_EF_CP0_EPC:
 328                         regs->cp0_epc = uregs[i];
 329                         break;
 330                 }
 331         }
 332
 333         /* System call number may have been changed */
 334         mips_syscall_update_nr(target, regs);
 335
 336         return 0;
 337 }
 338
 339 #endif /* CONFIG_64BIT */
 340
 341
 342 #ifdef CONFIG_MIPS_FP_SUPPORT
 343
 344 /*
 345  * Poke at FCSR according to its mask.  Set the Cause bits even
 346  * if a corresponding Enable bit is set.  This will be noticed at
 347  * the time the thread is switched to and SIGFPE thrown accordingly.
 348  */
 349 static void ptrace_setfcr31(struct task_struct *child, u32 value)
 350 {
 351         u32 fcr31;
 352         u32 mask;
 353
 354         fcr31 = child->thread.fpu.fcr31;
 355         mask = boot_cpu_data.fpu_msk31;
 356         child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
 357 }
 358
 359 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
 360 {
 361         int i;
 362
 363         if (!access_ok(data, 33 * 8))
 364                 return -EIO;
 365
 366         if (tsk_used_math(child)) {
 367                 union fpureg *fregs = get_fpu_regs(child);
 368                 for (i = 0; i < 32; i++)
 369                         __put_user(get_fpr64(&fregs[i], 0),
 370                                    i + (__u64 __user *)data);
 371         } else {
 372                 for (i = 0; i < 32; i++)
 373                         __put_user((__u64) -1, i + (__u64 __user *) data);
 374         }
 375
 376         __put_user(child->thread.fpu.fcr31, data + 64);
 377         __put_user(boot_cpu_data.fpu_id, data + 65);
 378
 379         return 0;
 380 }
 381
 382 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 383 {
 384         union fpureg *fregs;
 385         u64 fpr_val;
 386         u32 value;
 387         int i;
 388
 389         if (!access_ok(data, 33 * 8))
 390                 return -EIO;
 391
 392         init_fp_ctx(child);
 393         fregs = get_fpu_regs(child);
 394
 395         for (i = 0; i < 32; i++) {
 396                 __get_user(fpr_val, i + (__u64 __user *)data);
 397                 set_fpr64(&fregs[i], 0, fpr_val);
 398         }
 399
 400         __get_user(value, data + 64);
 401         ptrace_setfcr31(child, value);
 402
 403         /* FIR may not be written.  */
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Copy the floating-point context to the supplied NT_PRFPREG buffer,
 410  * !CONFIG_CPU_HAS_MSA variant.  FP context's general register slots
 411  * correspond 1:1 to buffer slots.  Only general registers are copied.
 412  */
 413 static void fpr_get_fpa(struct task_struct *target,
 414                        struct membuf *to)
 415 {
 416         membuf_write(to, &target->thread.fpu,
 417                         NUM_FPU_REGS * sizeof(elf_fpreg_t));
 418 }
 419
 420 /*
 421  * Copy the floating-point context to the supplied NT_PRFPREG buffer,
 422  * CONFIG_CPU_HAS_MSA variant.  Only lower 64 bits of FP context's
 423  * general register slots are copied to buffer slots.  Only general
 424  * registers are copied.
 425  */
 426 static void fpr_get_msa(struct task_struct *target, struct membuf *to)
 427 {
 428         unsigned int i;
 429
 430         BUILD_BUG_ON(sizeof(u64) != sizeof(elf_fpreg_t));
 431         for (i = 0; i < NUM_FPU_REGS; i++)
 432                 membuf_store(to, get_fpr64(&target->thread.fpu.fpr[i], 0));
 433 }
 434
 435 /*
 436  * Copy the floating-point context to the supplied NT_PRFPREG buffer.
 437  * Choose the appropriate helper for general registers, and then copy
 438  * the FCSR and FIR registers separately.
 439  */
 440 static int fpr_get(struct task_struct *target,
 441                    const struct user_regset *regset,
 442                    struct membuf to)
 443 {
 444         if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
 445                 fpr_get_fpa(target, &to);
 446         else
 447                 fpr_get_msa(target, &to);
 448
 449         membuf_write(&to, &target->thread.fpu.fcr31, sizeof(u32));
 450         membuf_write(&to, &boot_cpu_data.fpu_id, sizeof(u32));
 451         return 0;
 452 }
 453
 454 /*
 455  * Copy the supplied NT_PRFPREG buffer to the floating-point context,
 456  * !CONFIG_CPU_HAS_MSA variant.   Buffer slots correspond 1:1 to FP
 457  * context's general register slots.  Only general registers are copied.
 458  */
 459 static int fpr_set_fpa(struct task_struct *target,
 460                        unsigned int *pos, unsigned int *count,
 461                        const void **kbuf, const void __user **ubuf)
 462 {
 463         return user_regset_copyin(pos, count, kbuf, ubuf,
 464                                   &target->thread.fpu,
 465                                   0, NUM_FPU_REGS * sizeof(elf_fpreg_t));
 466 }
 467
 468 /*
 469  * Copy the supplied NT_PRFPREG buffer to the floating-point context,
 470  * CONFIG_CPU_HAS_MSA variant.  Buffer slots are copied to lower 64
 471  * bits only of FP context's general register slots.  Only general
 472  * registers are copied.
 473  */
 474 static int fpr_set_msa(struct task_struct *target,
 475                        unsigned int *pos, unsigned int *count,
 476                        const void **kbuf, const void __user **ubuf)
 477 {
 478         unsigned int i;
 479         u64 fpr_val;
 480         int err;
 481
 482         BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
 483         for (i = 0; i < NUM_FPU_REGS && *count > 0; i++) {
 484                 err = user_regset_copyin(pos, count, kbuf, ubuf,
 485                                          &fpr_val, i * sizeof(elf_fpreg_t),
 486                                          (i + 1) * sizeof(elf_fpreg_t));
 487                 if (err)
 488                         return err;
 489                 set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
 490         }
 491
 492         return 0;
 493 }
 494
 495 /*
 496  * Copy the supplied NT_PRFPREG buffer to the floating-point context.
 497  * Choose the appropriate helper for general registers, and then copy
 498  * the FCSR register separately.  Ignore the incoming FIR register
 499  * contents though, as the register is read-only.
 500  *
 501  * We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
 502  * which is supposed to have been guaranteed by the kernel before
 503  * calling us, e.g. in `ptrace_regset'.  We enforce that requirement,
 504  * so that we can safely avoid preinitializing temporaries for
 505  * partial register writes.
 506  */
 507 static int fpr_set(struct task_struct *target,
 508                    const struct user_regset *regset,
 509                    unsigned int pos, unsigned int count,
 510                    const void *kbuf, const void __user *ubuf)
 511 {
 512         const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
 513         const int fir_pos = fcr31_pos + sizeof(u32);
 514         u32 fcr31;
 515         int err;
 516
 517         BUG_ON(count % sizeof(elf_fpreg_t));
 518
 519         if (pos + count > sizeof(elf_fpregset_t))
 520                 return -EIO;
 521
 522         init_fp_ctx(target);
 523
 524         if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
 525                 err = fpr_set_fpa(target, &pos, &count, &kbuf, &ubuf);
 526         else
 527                 err = fpr_set_msa(target, &pos, &count, &kbuf, &ubuf);
 528         if (err)
 529                 return err;
 530
 531         if (count > 0) {
 532                 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 533                                          &fcr31,
 534                                          fcr31_pos, fcr31_pos + sizeof(u32));
 535                 if (err)
 536                         return err;
 537
 538                 ptrace_setfcr31(target, fcr31);
 539         }
 540
 541         if (count > 0)
 542                 err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
 543                                                 fir_pos,
 544                                                 fir_pos + sizeof(u32));
 545
 546         return err;
 547 }
 548
 549 /* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer.  */
 550 static int fp_mode_get(struct task_struct *target,
 551                        const struct user_regset *regset,
 552                        struct membuf to)
 553 {
 554         return membuf_store(&to, (int)mips_get_process_fp_mode(target));
 555 }
 556
 557 /*
 558  * Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting.
 559  *
 560  * We optimize for the case where `count % sizeof(int) == 0', which
 561  * is supposed to have been guaranteed by the kernel before calling
 562  * us, e.g. in `ptrace_regset'.  We enforce that requirement, so
 563  * that we can safely avoid preinitializing temporaries for partial
 564  * mode writes.
 565  */
 566 static int fp_mode_set(struct task_struct *target,
 567                        const struct user_regset *regset,
 568                        unsigned int pos, unsigned int count,
 569                        const void *kbuf, const void __user *ubuf)
 570 {
 571         int fp_mode;
 572         int err;
 573
 574         BUG_ON(count % sizeof(int));
 575
 576         if (pos + count > sizeof(fp_mode))
 577                 return -EIO;
 578
 579         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
 580                                  sizeof(fp_mode));
 581         if (err)
 582                 return err;
 583
 584         if (count > 0)
 585                 err = mips_set_process_fp_mode(target, fp_mode);
 586
 587         return err;
 588 }
 589
 590 #endif /* CONFIG_MIPS_FP_SUPPORT */
 591
 592 #ifdef CONFIG_CPU_HAS_MSA
 593
 594 struct msa_control_regs {
 595         unsigned int fir;
 596         unsigned int fcsr;
 597         unsigned int msair;
 598         unsigned int msacsr;
 599 };
 600
 601 static void copy_pad_fprs(struct task_struct *target,
 602                          const struct user_regset *regset,
 603                          struct membuf *to,
 604                          unsigned int live_sz)
 605 {
 606         int i, j;
 607         unsigned long long fill = ~0ull;
 608         unsigned int cp_sz, pad_sz;
 609
 610         cp_sz = min(regset->size, live_sz);
 611         pad_sz = regset->size - cp_sz;
 612         WARN_ON(pad_sz % sizeof(fill));
 613
 614         for (i = 0; i < NUM_FPU_REGS; i++) {
 615                 membuf_write(to, &target->thread.fpu.fpr[i], cp_sz);
 616                 for (j = 0; j < (pad_sz / sizeof(fill)); j++)
 617                         membuf_store(to, fill);
 618         }
 619 }
 620
 621 static int msa_get(struct task_struct *target,
 622                    const struct user_regset *regset,
 623                    struct membuf to)
 624 {
 625         const unsigned int wr_size = NUM_FPU_REGS * regset->size;
 626         const struct msa_control_regs ctrl_regs = {
 627                 .fir = boot_cpu_data.fpu_id,
 628                 .fcsr = target->thread.fpu.fcr31,
 629                 .msair = boot_cpu_data.msa_id,
 630                 .msacsr = target->thread.fpu.msacsr,
 631         };
 632
 633         if (!tsk_used_math(target)) {
 634                 /* The task hasn't used FP or MSA, fill with 0xff */
 635                 copy_pad_fprs(target, regset, &to, 0);
 636         } else if (!test_tsk_thread_flag(target, TIF_MSA_CTX_LIVE)) {
 637                 /* Copy scalar FP context, fill the rest with 0xff */
 638                 copy_pad_fprs(target, regset, &to, 8);
 639         } else if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
 640                 /* Trivially copy the vector registers */
 641                 membuf_write(&to, &target->thread.fpu.fpr, wr_size);
 642         } else {
 643                 /* Copy as much context as possible, fill the rest with 0xff */
 644                 copy_pad_fprs(target, regset, &to,
 645                                 sizeof(target->thread.fpu.fpr[0]));
 646         }
 647
 648         return membuf_write(&to, &ctrl_regs, sizeof(ctrl_regs));
 649 }
 650
 651 static int msa_set(struct task_struct *target,
 652                    const struct user_regset *regset,
 653                    unsigned int pos, unsigned int count,
 654                    const void *kbuf, const void __user *ubuf)
 655 {
 656         const unsigned int wr_size = NUM_FPU_REGS * regset->size;
 657         struct msa_control_regs ctrl_regs;
 658         unsigned int cp_sz;
 659         int i, err, start;
 660
 661         init_fp_ctx(target);
 662
 663         if (sizeof(target->thread.fpu.fpr[0]) == regset->size) {
 664                 /* Trivially copy the vector registers */
 665                 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 666                                          &target->thread.fpu.fpr,
 667                                          0, wr_size);
 668         } else {
 669                 /* Copy as much context as possible */
 670                 cp_sz = min_t(unsigned int, regset->size,
 671                               sizeof(target->thread.fpu.fpr[0]));
 672
 673                 i = start = err = 0;
 674                 for (; i < NUM_FPU_REGS; i++, start += regset->size) {
 675                         err |= user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 676                                                   &target->thread.fpu.fpr[i],
 677                                                   start, start + cp_sz);
 678                 }
 679         }
 680
 681         if (!err)
 682                 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl_regs,
 683                                          wr_size, wr_size + sizeof(ctrl_regs));
 684         if (!err) {
 685                 target->thread.fpu.fcr31 = ctrl_regs.fcsr & ~FPU_CSR_ALL_X;
 686                 target->thread.fpu.msacsr = ctrl_regs.msacsr & ~MSA_CSR_CAUSEF;
 687         }
 688
 689         return err;
 690 }
 691
 692 #endif /* CONFIG_CPU_HAS_MSA */
 693
 694 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
 695
 696 /*
 697  * Copy the DSP context to the supplied 32-bit NT_MIPS_DSP buffer.
 698  */
 699 static int dsp32_get(struct task_struct *target,
 700                      const struct user_regset *regset,
 701                      struct membuf to)
 702 {
 703         u32 dspregs[NUM_DSP_REGS + 1];
 704         unsigned int i;
 705
 706         BUG_ON(to.left % sizeof(u32));
 707
 708         if (!cpu_has_dsp)
 709                 return -EIO;
 710
 711         for (i = 0; i < NUM_DSP_REGS; i++)
 712                 dspregs[i] = target->thread.dsp.dspr[i];
 713         dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
 714         return membuf_write(&to, dspregs, sizeof(dspregs));
 715 }
 716
 717 /*
 718  * Copy the supplied 32-bit NT_MIPS_DSP buffer to the DSP context.
 719  */
 720 static int dsp32_set(struct task_struct *target,
 721                      const struct user_regset *regset,
 722                      unsigned int pos, unsigned int count,
 723                      const void *kbuf, const void __user *ubuf)
 724 {
 725         unsigned int start, num_regs, i;
 726         u32 dspregs[NUM_DSP_REGS + 1];
 727         int err;
 728
 729         BUG_ON(count % sizeof(u32));
 730
 731         if (!cpu_has_dsp)
 732                 return -EIO;
 733
 734         start = pos / sizeof(u32);
 735         num_regs = count / sizeof(u32);
 736
 737         if (start + num_regs > NUM_DSP_REGS + 1)
 738                 return -EIO;
 739
 740         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
 741                                  sizeof(dspregs));
 742         if (err)
 743                 return err;
 744
 745         for (i = start; i < num_regs; i++)
 746                 switch (i) {
 747                 case 0 ... NUM_DSP_REGS - 1:
 748                         target->thread.dsp.dspr[i] = (s32)dspregs[i];
 749                         break;
 750                 case NUM_DSP_REGS:
 751                         target->thread.dsp.dspcontrol = (s32)dspregs[i];
 752                         break;
 753                 }
 754
 755         return 0;
 756 }
 757
 758 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
 759
 760 #ifdef CONFIG_64BIT
 761
 762 /*
 763  * Copy the DSP context to the supplied 64-bit NT_MIPS_DSP buffer.
 764  */
 765 static int dsp64_get(struct task_struct *target,
 766                      const struct user_regset *regset,
 767                      struct membuf to)
 768 {
 769         u64 dspregs[NUM_DSP_REGS + 1];
 770         unsigned int i;
 771
 772         BUG_ON(to.left % sizeof(u64));
 773
 774         if (!cpu_has_dsp)
 775                 return -EIO;
 776
 777         for (i = 0; i < NUM_DSP_REGS; i++)
 778                 dspregs[i] = target->thread.dsp.dspr[i];
 779         dspregs[NUM_DSP_REGS] = target->thread.dsp.dspcontrol;
 780         return membuf_write(&to, dspregs, sizeof(dspregs));
 781 }
 782
 783 /*
 784  * Copy the supplied 64-bit NT_MIPS_DSP buffer to the DSP context.
 785  */
 786 static int dsp64_set(struct task_struct *target,
 787                      const struct user_regset *regset,
 788                      unsigned int pos, unsigned int count,
 789                      const void *kbuf, const void __user *ubuf)
 790 {
 791         unsigned int start, num_regs, i;
 792         u64 dspregs[NUM_DSP_REGS + 1];
 793         int err;
 794
 795         BUG_ON(count % sizeof(u64));
 796
 797         if (!cpu_has_dsp)
 798                 return -EIO;
 799
 800         start = pos / sizeof(u64);
 801         num_regs = count / sizeof(u64);
 802
 803         if (start + num_regs > NUM_DSP_REGS + 1)
 804                 return -EIO;
 805
 806         err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, dspregs, 0,
 807                                  sizeof(dspregs));
 808         if (err)
 809                 return err;
 810
 811         for (i = start; i < num_regs; i++)
 812                 switch (i) {
 813                 case 0 ... NUM_DSP_REGS - 1:
 814                         target->thread.dsp.dspr[i] = dspregs[i];
 815                         break;
 816                 case NUM_DSP_REGS:
 817                         target->thread.dsp.dspcontrol = dspregs[i];
 818                         break;
 819                 }
 820
 821         return 0;
 822 }
 823
 824 #endif /* CONFIG_64BIT */
 825
 826 /*
 827  * Determine whether the DSP context is present.
 828  */
 829 static int dsp_active(struct task_struct *target,
 830                       const struct user_regset *regset)
 831 {
 832         return cpu_has_dsp ? NUM_DSP_REGS + 1 : -ENODEV;
 833 }
 834
 835 enum mips_regset {
 836         REGSET_GPR,
 837         REGSET_DSP,
 838 #ifdef CONFIG_MIPS_FP_SUPPORT
 839         REGSET_FPR,
 840         REGSET_FP_MODE,
 841 #endif
 842 #ifdef CONFIG_CPU_HAS_MSA
 843         REGSET_MSA,
 844 #endif
 845 };
 846
 847 struct pt_regs_offset {
 848         const char *name;
 849         int offset;
 850 };
 851
 852 #define REG_OFFSET_NAME(reg, r) {                                       \
 853         .name = #reg,                                                   \
 854         .offset = offsetof(struct pt_regs, r)                           \
 855 }
 856
 857 #define REG_OFFSET_END {                                                \
 858         .name = NULL,                                                   \
 859         .offset = 0                                                     \
 860 }
 861
 862 static const struct pt_regs_offset regoffset_table[] = {
 863         REG_OFFSET_NAME(r0, regs[0]),
 864         REG_OFFSET_NAME(r1, regs[1]),
 865         REG_OFFSET_NAME(r2, regs[2]),
 866         REG_OFFSET_NAME(r3, regs[3]),
 867         REG_OFFSET_NAME(r4, regs[4]),
 868         REG_OFFSET_NAME(r5, regs[5]),
 869         REG_OFFSET_NAME(r6, regs[6]),
 870         REG_OFFSET_NAME(r7, regs[7]),
 871         REG_OFFSET_NAME(r8, regs[8]),
 872         REG_OFFSET_NAME(r9, regs[9]),
 873         REG_OFFSET_NAME(r10, regs[10]),
 874         REG_OFFSET_NAME(r11, regs[11]),
 875         REG_OFFSET_NAME(r12, regs[12]),
 876         REG_OFFSET_NAME(r13, regs[13]),
 877         REG_OFFSET_NAME(r14, regs[14]),
 878         REG_OFFSET_NAME(r15, regs[15]),
 879         REG_OFFSET_NAME(r16, regs[16]),
 880         REG_OFFSET_NAME(r17, regs[17]),
 881         REG_OFFSET_NAME(r18, regs[18]),
 882         REG_OFFSET_NAME(r19, regs[19]),
 883         REG_OFFSET_NAME(r20, regs[20]),
 884         REG_OFFSET_NAME(r21, regs[21]),
 885         REG_OFFSET_NAME(r22, regs[22]),
 886         REG_OFFSET_NAME(r23, regs[23]),
 887         REG_OFFSET_NAME(r24, regs[24]),
 888         REG_OFFSET_NAME(r25, regs[25]),
 889         REG_OFFSET_NAME(r26, regs[26]),
 890         REG_OFFSET_NAME(r27, regs[27]),
 891         REG_OFFSET_NAME(r28, regs[28]),
 892         REG_OFFSET_NAME(r29, regs[29]),
 893         REG_OFFSET_NAME(r30, regs[30]),
 894         REG_OFFSET_NAME(r31, regs[31]),
 895         REG_OFFSET_NAME(c0_status, cp0_status),
 896         REG_OFFSET_NAME(hi, hi),
 897         REG_OFFSET_NAME(lo, lo),
 898 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 899         REG_OFFSET_NAME(acx, acx),
 900 #endif
 901         REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
 902         REG_OFFSET_NAME(c0_cause, cp0_cause),
 903         REG_OFFSET_NAME(c0_epc, cp0_epc),
 904 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 905         REG_OFFSET_NAME(mpl0, mpl[0]),
 906         REG_OFFSET_NAME(mpl1, mpl[1]),
 907         REG_OFFSET_NAME(mpl2, mpl[2]),
 908         REG_OFFSET_NAME(mtp0, mtp[0]),
 909         REG_OFFSET_NAME(mtp1, mtp[1]),
 910         REG_OFFSET_NAME(mtp2, mtp[2]),
 911 #endif
 912         REG_OFFSET_END,
 913 };
 914
 915 /**
 916  * regs_query_register_offset() - query register offset from its name
 917  * @name:       the name of a register
 918  *
 919  * regs_query_register_offset() returns the offset of a register in struct
 920  * pt_regs from its name. If the name is invalid, this returns -EINVAL;
 921  */
 922 int regs_query_register_offset(const char *name)
 923 {
 924         const struct pt_regs_offset *roff;
 925         for (roff = regoffset_table; roff->name != NULL; roff++)
 926                 if (!strcmp(roff->name, name))
 927                         return roff->offset;
 928         return -EINVAL;
 929 }
 930
 931 #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
 932
 933 static const struct user_regset mips_regsets[] = {
 934         [REGSET_GPR] = {
 935                 .core_note_type = NT_PRSTATUS,
 936                 .n              = ELF_NGREG,
 937                 .size           = sizeof(unsigned int),
 938                 .align          = sizeof(unsigned int),
 939                 .regset_get             = gpr32_get,
 940                 .set            = gpr32_set,
 941         },
 942         [REGSET_DSP] = {
 943                 .core_note_type = NT_MIPS_DSP,
 944                 .n              = NUM_DSP_REGS + 1,
 945                 .size           = sizeof(u32),
 946                 .align          = sizeof(u32),
 947                 .regset_get             = dsp32_get,
 948                 .set            = dsp32_set,
 949                 .active         = dsp_active,
 950         },
 951 #ifdef CONFIG_MIPS_FP_SUPPORT
 952         [REGSET_FPR] = {
 953                 .core_note_type = NT_PRFPREG,
 954                 .n              = ELF_NFPREG,
 955                 .size           = sizeof(elf_fpreg_t),
 956                 .align          = sizeof(elf_fpreg_t),
 957                 .regset_get             = fpr_get,
 958                 .set            = fpr_set,
 959         },
 960         [REGSET_FP_MODE] = {
 961                 .core_note_type = NT_MIPS_FP_MODE,
 962                 .n              = 1,
 963                 .size           = sizeof(int),
 964                 .align          = sizeof(int),
 965                 .regset_get             = fp_mode_get,
 966                 .set            = fp_mode_set,
 967         },
 968 #endif
 969 #ifdef CONFIG_CPU_HAS_MSA
 970         [REGSET_MSA] = {
 971                 .core_note_type = NT_MIPS_MSA,
 972                 .n              = NUM_FPU_REGS + 1,
 973                 .size           = 16,
 974                 .align          = 16,
 975                 .regset_get             = msa_get,
 976                 .set            = msa_set,
 977         },
 978 #endif
 979 };
 980
 981 static const struct user_regset_view user_mips_view = {
 982         .name           = "mips",
 983         .e_machine      = ELF_ARCH,
 984         .ei_osabi       = ELF_OSABI,
 985         .regsets        = mips_regsets,
 986         .n              = ARRAY_SIZE(mips_regsets),
 987 };
 988
 989 #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
 990
 991 #ifdef CONFIG_64BIT
 992
 993 static const struct user_regset mips64_regsets[] = {
 994         [REGSET_GPR] = {
 995                 .core_note_type = NT_PRSTATUS,
 996                 .n              = ELF_NGREG,
 997                 .size           = sizeof(unsigned long),
 998                 .align          = sizeof(unsigned long),
 999                 .regset_get             = gpr64_get,
1000                 .set            = gpr64_set,
1001         },
1002         [REGSET_DSP] = {
1003                 .core_note_type = NT_MIPS_DSP,
1004                 .n              = NUM_DSP_REGS + 1,
1005                 .size           = sizeof(u64),
1006                 .align          = sizeof(u64),
1007                 .regset_get             = dsp64_get,
1008                 .set            = dsp64_set,
1009                 .active         = dsp_active,
1010         },
1011 #ifdef CONFIG_MIPS_FP_SUPPORT
1012         [REGSET_FP_MODE] = {
1013                 .core_note_type = NT_MIPS_FP_MODE,
1014                 .n              = 1,
1015                 .size           = sizeof(int),
1016                 .align          = sizeof(int),
1017                 .regset_get             = fp_mode_get,
1018                 .set            = fp_mode_set,
1019         },
1020         [REGSET_FPR] = {
1021                 .core_note_type = NT_PRFPREG,
1022                 .n              = ELF_NFPREG,
1023                 .size           = sizeof(elf_fpreg_t),
1024                 .align          = sizeof(elf_fpreg_t),
1025                 .regset_get             = fpr_get,
1026                 .set            = fpr_set,
1027         },
1028 #endif
1029 #ifdef CONFIG_CPU_HAS_MSA
1030         [REGSET_MSA] = {
1031                 .core_note_type = NT_MIPS_MSA,
1032                 .n              = NUM_FPU_REGS + 1,
1033                 .size           = 16,
1034                 .align          = 16,
1035                 .regset_get             = msa_get,
1036                 .set            = msa_set,
1037         },
1038 #endif
1039 };
1040
1041 static const struct user_regset_view user_mips64_view = {
1042         .name           = "mips64",
1043         .e_machine      = ELF_ARCH,
1044         .ei_osabi       = ELF_OSABI,
1045         .regsets        = mips64_regsets,
1046         .n              = ARRAY_SIZE(mips64_regsets),
1047 };
1048
1049 #ifdef CONFIG_MIPS32_N32
1050
1051 static const struct user_regset_view user_mipsn32_view = {
1052         .name           = "mipsn32",
1053         .e_flags        = EF_MIPS_ABI2,
1054         .e_machine      = ELF_ARCH,
1055         .ei_osabi       = ELF_OSABI,
1056         .regsets        = mips64_regsets,
1057         .n              = ARRAY_SIZE(mips64_regsets),
1058 };
1059
1060 #endif /* CONFIG_MIPS32_N32 */
1061
1062 #endif /* CONFIG_64BIT */
1063
1064 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
1065 {
1066 #ifdef CONFIG_32BIT
1067         return &user_mips_view;
1068 #else
1069 #ifdef CONFIG_MIPS32_O32
1070         if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
1071                 return &user_mips_view;
1072 #endif
1073 #ifdef CONFIG_MIPS32_N32
1074         if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
1075                 return &user_mipsn32_view;
1076 #endif
1077         return &user_mips64_view;
1078 #endif
1079 }
1080
1081 static int read_insn(struct task_struct *task, unsigned long addr, unsigned int *insn)
1082 {
1083         int copied = access_process_vm(task, addr, insn,
1084                                        sizeof(unsigned int), FOLL_FORCE);
1085
1086         if (copied != sizeof(unsigned int)) {
1087                 pr_err("failed to read instruction from 0x%lx\n", addr);
1088                 return -EIO;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static int write_insn(struct task_struct *task, unsigned long addr, unsigned int insn)
1095 {
1096         int copied = access_process_vm(task, addr, &insn,
1097                                        sizeof(unsigned int), FOLL_FORCE | FOLL_WRITE);
1098
1099         if (copied != sizeof(unsigned int)) {
1100                 pr_err("failed to write instruction to 0x%lx\n", addr);
1101                 return -EIO;
1102         }
1103
1104         return 0;
1105 }
1106
1107 static int insn_has_delayslot(union mips_instruction insn)
1108 {
1109         return __insn_has_delay_slot(insn);
1110 }
1111
1112 static void ptrace_set_bpt(struct task_struct *child)
1113 {
1114         union mips_instruction mips_insn = { 0 };
1115         struct pt_regs *regs;
1116         unsigned long pc;
1117         unsigned int insn;
1118         int i, ret, nsaved = 0;
1119
1120         regs = task_pt_regs(child);
1121         pc = regs->cp0_epc;
1122
1123         ret = read_insn(child, pc, &insn);
1124         if (ret < 0)
1125                 return;
1126
1127         if (insn_has_delayslot(mips_insn)) {
1128                 pr_info("executing branch insn\n");
1129                 ret = __compute_return_epc(regs);
1130                 if (ret < 0)
1131                         return;
1132                 task_thread_info(child)->bpt_addr[nsaved++] = regs->cp0_epc;
1133         } else {
1134                 pr_info("executing normal insn\n");
1135                 task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
1136         }
1137
1138         /* install breakpoints */
1139         for (i = 0; i < nsaved; i++) {
1140                 ret = read_insn(child, task_thread_info(child)->bpt_addr[i], &insn);
1141                 if (ret < 0)
1142                         return;
1143
1144                 task_thread_info(child)->bpt_insn[i] = insn;
1145
1146                 ret = write_insn(child, task_thread_info(child)->bpt_addr[i], BREAKINST);
1147                 if (ret < 0)
1148                         return;
1149         }
1150
1151         task_thread_info(child)->bpt_nsaved = nsaved;
1152 }
1153
1154 static void ptrace_cancel_bpt(struct task_struct *child)
1155 {
1156         int i, nsaved = task_thread_info(child)->bpt_nsaved;
1157
1158         task_thread_info(child)->bpt_nsaved = 0;
1159
1160         if (nsaved > 1) {
1161                 pr_info("%s: bogus nsaved: %d!\n", __func__, nsaved);
1162                 nsaved = 1;
1163         }
1164
1165         for (i = 0; i < nsaved; i++) {
1166                 write_insn(child, task_thread_info(child)->bpt_addr[i],
1167                           task_thread_info(child)->bpt_insn[i]);
1168         }
1169 }
1170
1171 void user_enable_single_step(struct task_struct *child)
1172 {
1173         set_tsk_thread_flag(child, TIF_SINGLESTEP);
1174         ptrace_set_bpt(child);
1175 }
1176
1177 void user_disable_single_step(struct task_struct *child)
1178 {
1179         clear_tsk_thread_flag(child, TIF_SINGLESTEP);
1180         ptrace_cancel_bpt(child);
1181 }
1182
1183 long arch_ptrace(struct task_struct *child, long request,
1184                  unsigned long addr, unsigned long data)
1185 {
1186         int ret;
1187         void __user *addrp = (void __user *) addr;
1188         void __user *datavp = (void __user *) data;
1189         unsigned long __user *datalp = (void __user *) data;
1190
1191         switch (request) {
1192         /* when I and D space are separate, these will need to be fixed. */
1193         case PTRACE_PEEKTEXT: /* read word at location addr. */
1194         case PTRACE_PEEKDATA:
1195                 ret = generic_ptrace_peekdata(child, addr, data);
1196                 break;
1197
1198         /* Read the word at location addr in the USER area. */
1199         case PTRACE_PEEKUSR: {
1200                 struct pt_regs *regs;
1201                 unsigned long tmp = 0;
1202
1203                 regs = task_pt_regs(child);
1204                 ret = 0;  /* Default return value. */
1205
1206                 switch (addr) {
1207                 case 0 ... 31:
1208                         tmp = regs->regs[addr];
1209                         break;
1210 #ifdef CONFIG_MIPS_FP_SUPPORT
1211                 case FPR_BASE ... FPR_BASE + 31: {
1212                         union fpureg *fregs;
1213
1214                         if (!tsk_used_math(child)) {
1215                                 /* FP not yet used */
1216                                 tmp = -1;
1217                                 break;
1218                         }
1219                         fregs = get_fpu_regs(child);
1220
1221 #ifdef CONFIG_32BIT
1222                         if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1223                                 /*
1224                                  * The odd registers are actually the high
1225                                  * order bits of the values stored in the even
1226                                  * registers.
1227                                  */
1228                                 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
1229                                                 addr & 1);
1230                                 break;
1231                         }
1232 #endif
1233                         tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
1234                         break;
1235                 }
1236                 case FPC_CSR:
1237                         tmp = child->thread.fpu.fcr31;
1238                         break;
1239                 case FPC_EIR:
1240                         /* implementation / version register */
1241                         tmp = boot_cpu_data.fpu_id;
1242                         break;
1243 #endif
1244                 case PC:
1245                         tmp = regs->cp0_epc;
1246                         break;
1247                 case CAUSE:
1248                         tmp = regs->cp0_cause;
1249                         break;
1250                 case BADVADDR:
1251                         tmp = regs->cp0_badvaddr;
1252                         break;
1253                 case MMHI:
1254                         tmp = regs->hi;
1255                         break;
1256                 case MMLO:
1257                         tmp = regs->lo;
1258                         break;
1259 #ifdef CONFIG_CPU_HAS_SMARTMIPS
1260                 case ACX:
1261                         tmp = regs->acx;
1262                         break;
1263 #endif
1264                 case DSP_BASE ... DSP_BASE + 5: {
1265                         dspreg_t *dregs;
1266
1267                         if (!cpu_has_dsp) {
1268                                 tmp = 0;
1269                                 ret = -EIO;
1270                                 goto out;
1271                         }
1272                         dregs = __get_dsp_regs(child);
1273                         tmp = dregs[addr - DSP_BASE];
1274                         break;
1275                 }
1276                 case DSP_CONTROL:
1277                         if (!cpu_has_dsp) {
1278                                 tmp = 0;
1279                                 ret = -EIO;
1280                                 goto out;
1281                         }
1282                         tmp = child->thread.dsp.dspcontrol;
1283                         break;
1284                 default:
1285                         tmp = 0;
1286                         ret = -EIO;
1287                         goto out;
1288                 }
1289                 ret = put_user(tmp, datalp);
1290                 break;
1291         }
1292
1293         /* when I and D space are separate, this will have to be fixed. */
1294         case PTRACE_POKETEXT: /* write the word at location addr. */
1295         case PTRACE_POKEDATA:
1296                 ret = generic_ptrace_pokedata(child, addr, data);
1297                 break;
1298
1299         case PTRACE_POKEUSR: {
1300                 struct pt_regs *regs;
1301                 ret = 0;
1302                 regs = task_pt_regs(child);
1303
1304                 switch (addr) {
1305                 case 0 ... 31:
1306                         regs->regs[addr] = data;
1307                         /* System call number may have been changed */
1308                         if (addr == 2)
1309                                 mips_syscall_update_nr(child, regs);
1310                         else if (addr == 4 &&
1311                                  mips_syscall_is_indirect(child, regs))
1312                                 mips_syscall_update_nr(child, regs);
1313                         break;
1314 #ifdef CONFIG_MIPS_FP_SUPPORT
1315                 case FPR_BASE ... FPR_BASE + 31: {
1316                         union fpureg *fregs = get_fpu_regs(child);
1317
1318                         init_fp_ctx(child);
1319 #ifdef CONFIG_32BIT
1320                         if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1321                                 /*
1322                                  * The odd registers are actually the high
1323                                  * order bits of the values stored in the even
1324                                  * registers.
1325                                  */
1326                                 set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
1327                                           addr & 1, data);
1328                                 break;
1329                         }
1330 #endif
1331                         set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1332                         break;
1333                 }
1334                 case FPC_CSR:
1335                         init_fp_ctx(child);
1336                         ptrace_setfcr31(child, data);
1337                         break;
1338 #endif
1339                 case PC:
1340                         regs->cp0_epc = data;
1341                         break;
1342                 case MMHI:
1343                         regs->hi = data;
1344                         break;
1345                 case MMLO:
1346                         regs->lo = data;
1347                         break;
1348 #ifdef CONFIG_CPU_HAS_SMARTMIPS
1349                 case ACX:
1350                         regs->acx = data;
1351                         break;
1352 #endif
1353                 case DSP_BASE ... DSP_BASE + 5: {
1354                         dspreg_t *dregs;
1355
1356                         if (!cpu_has_dsp) {
1357                                 ret = -EIO;
1358                                 break;
1359                         }
1360
1361                         dregs = __get_dsp_regs(child);
1362                         dregs[addr - DSP_BASE] = data;
1363                         break;
1364                 }
1365                 case DSP_CONTROL:
1366                         if (!cpu_has_dsp) {
1367                                 ret = -EIO;
1368                                 break;
1369                         }
1370                         child->thread.dsp.dspcontrol = data;
1371                         break;
1372                 default:
1373                         /* The rest are not allowed. */
1374                         ret = -EIO;
1375                         break;
1376                 }
1377                 break;
1378                 }
1379
1380         case PTRACE_GETREGS:
1381                 ret = ptrace_getregs(child, datavp);
1382                 break;
1383
1384         case PTRACE_SETREGS:
1385                 ret = ptrace_setregs(child, datavp);
1386                 break;
1387
1388 #ifdef CONFIG_MIPS_FP_SUPPORT
1389         case PTRACE_GETFPREGS:
1390                 ret = ptrace_getfpregs(child, datavp);
1391                 break;
1392
1393         case PTRACE_SETFPREGS:
1394                 ret = ptrace_setfpregs(child, datavp);
1395                 break;
1396 #endif
1397         case PTRACE_GET_THREAD_AREA:
1398                 ret = put_user(task_thread_info(child)->tp_value, datalp);
1399                 break;
1400
1401         case PTRACE_GET_WATCH_REGS:
1402                 ret = ptrace_get_watch_regs(child, addrp);
1403                 break;
1404
1405         case PTRACE_SET_WATCH_REGS:
1406                 ret = ptrace_set_watch_regs(child, addrp);
1407                 break;
1408
1409         default:
1410                 ret = ptrace_request(child, request, addr, data);
1411                 break;
1412         }
1413  out:
1414         return ret;
1415 }
1416
1417 /*
1418  * Notification of system call entry/exit
1419  * - triggered by current->work.syscall_trace
1420  */
1421 asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
1422 {
1423         user_exit();
1424
1425         current_thread_info()->syscall = syscall;
1426
1427         if (test_thread_flag(TIF_SYSCALL_TRACE)) {
1428                 if (tracehook_report_syscall_entry(regs))
1429                         return -1;
1430                 syscall = current_thread_info()->syscall;
1431         }
1432
1433 #ifdef CONFIG_SECCOMP
1434         if (unlikely(test_thread_flag(TIF_SECCOMP))) {
1435                 int ret, i;
1436                 struct seccomp_data sd;
1437                 unsigned long args[6];
1438
1439                 sd.nr = syscall;
1440                 sd.arch = syscall_get_arch(current);
1441                 syscall_get_arguments(current, regs, args);
1442                 for (i = 0; i < 6; i++)
1443                         sd.args[i] = args[i];
1444                 sd.instruction_pointer = KSTK_EIP(current);
1445
1446                 ret = __secure_computing(&sd);
1447                 if (ret == -1)
1448                         return ret;
1449                 syscall = current_thread_info()->syscall;
1450         }
1451 #endif
1452
1453         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1454                 trace_sys_enter(regs, regs->regs[2]);
1455
1456         audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
1457                             regs->regs[6], regs->regs[7]);
1458
1459         /*
1460          * Negative syscall numbers are mistaken for rejected syscalls, but
1461          * won't have had the return value set appropriately, so we do so now.
1462          */
1463         if (syscall < 0)
1464                 syscall_set_return_value(current, regs, -ENOSYS, 0);
1465         return syscall;
1466 }
1467
1468 /*
1469  * Notification of system call entry/exit
1470  * - triggered by current->work.syscall_trace
1471  */
1472 asmlinkage void syscall_trace_leave(struct pt_regs *regs)
1473 {
1474         /*
1475          * We may come here right after calling schedule_user()
1476          * or do_notify_resume(), in which case we can be in RCU
1477          * user mode.
1478          */
1479         user_exit();
1480
1481         audit_syscall_exit(regs);
1482
1483         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1484                 trace_sys_exit(regs, regs_return_value(regs));
1485
1486         if (test_thread_flag(TIF_SYSCALL_TRACE))
1487                 tracehook_report_syscall_exit(regs, 0);
1488
1489         user_enter();
1490 }