2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2002, 2007 Maciej W. Rozycki
9 * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
22 #include <asm/thread_info.h>
27 * General exception vector for all other CPUs.
29 * Be careful when changing this, it has to be at most 128 bytes
30 * to fit into space reserved for the exception handler.
32 NESTED(except_vec3_generic, 0, sp)
35 #if R5432_CP0_INTERRUPT_WAR
43 PTR_L k0, exception_handlers(k1)
46 END(except_vec3_generic)
49 * General exception handler for CPUs with virtual coherency exception.
51 * Be careful when changing this, it has to be at most 256 (as a special
52 * exception) bytes to fit into space reserved for the exception handler.
54 NESTED(except_vec3_r4000, 0, sp)
64 beq k1, k0, handle_vced
66 beq k1, k0, handle_vcei
71 PTR_L k0, exception_handlers(k1)
75 * Big shit, we now may have two dirty primary cache lines for the same
76 * physical address. We can safely invalidate the line pointed to by
77 * c0_badvaddr because after return from this exception handler the
78 * load / store will be re-executed.
82 li k1, -4 # Is this ...
83 and k0, k1 # ... really needed?
85 cache Index_Store_Tag_D, (k0)
86 cache Hit_Writeback_Inv_SD, (k0)
97 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
106 END(except_vec3_r4000)
110 .align 5 /* 32 byte rollback region */
114 /* start of rollback region */
115 LONG_L t0, TI_FLAGS($28)
117 andi t0, _TIF_NEED_RESCHED
122 #ifdef CONFIG_CPU_MICROMIPS
128 .set MIPS_ISA_ARCH_LEVEL_RAW
130 /* end of rollback region (the region size must be power of two) */
137 .macro BUILD_ROLLBACK_PROLOGUE handler
138 FEXPORT(rollback_\handler)
142 PTR_LA k1, __r4k_wait
143 ori k0, 0x1f /* 32 byte rollback region */
151 BUILD_ROLLBACK_PROLOGUE handle_int
152 NESTED(handle_int, PT_SIZE, sp)
153 #ifdef CONFIG_TRACE_IRQFLAGS
155 * Check to see if the interrupted code has just disabled
156 * interrupts and ignore this interrupt for now if so.
158 * local_irq_disable() disables interrupts and then calls
159 * trace_hardirqs_off() to track the state. If an interrupt is taken
160 * after interrupts are disabled but before the state is updated
161 * it will appear to restore_all that it is incorrectly returning with
162 * interrupts disabled
167 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
188 LONG_L s0, TI_REGS($28)
189 LONG_S sp, TI_REGS($28)
190 PTR_LA ra, ret_from_irq
191 PTR_LA v0, plat_irq_dispatch
193 #ifdef CONFIG_CPU_MICROMIPS
201 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
202 * This is a dedicated interrupt exception vector which reduces the
203 * interrupt processing overhead. The jump instruction will be replaced
204 * at the initialization time.
206 * Be careful when changing this, it has to be at most 128 bytes
207 * to fit into space reserved for the exception handler.
209 NESTED(except_vec4, 0, sp)
210 1: j 1b /* Dummy, will be replaced */
214 * EJTAG debug exception handler.
215 * The EJTAG debug exception entry point is 0xbfc00480, which
216 * normally is in the boot PROM, so the boot PROM must do an
217 * unconditional jump to this vector.
219 NESTED(except_vec_ejtag_debug, 0, sp)
220 j ejtag_debug_handler
221 #ifdef CONFIG_CPU_MICROMIPS
224 END(except_vec_ejtag_debug)
229 * Vectored interrupt handler.
230 * This prototype is copied to ebase + n*IntCtl.VS and patched
231 * to invoke the handler
233 BUILD_ROLLBACK_PROLOGUE except_vec_vi
234 NESTED(except_vec_vi, 0, sp)
239 PTR_LA v1, except_vec_vi_handler
240 FEXPORT(except_vec_vi_lui)
241 lui v0, 0 /* Patched */
243 FEXPORT(except_vec_vi_ori)
244 ori v0, 0 /* Patched */
247 EXPORT(except_vec_vi_end)
250 * Common Vectored Interrupt code
251 * Complete the register saves and invoke the handler which is passed in $v0
253 NESTED(except_vec_vi_handler, 0, sp)
257 #ifdef CONFIG_TRACE_IRQFLAGS
263 LONG_L s0, TI_REGS($28)
264 LONG_S sp, TI_REGS($28)
265 PTR_LA ra, ret_from_irq
267 END(except_vec_vi_handler)
270 * EJTAG debug exception handler.
272 NESTED(ejtag_debug_handler, PT_SIZE, sp)
278 sll k0, k0, 30 # Check for SDBBP.
279 bgez k0, ejtag_return
281 PTR_LA k0, ejtag_debug_buffer
285 jal ejtag_exception_handler
287 PTR_LA k0, ejtag_debug_buffer
295 END(ejtag_debug_handler)
298 * This buffer is reserved for the use of the EJTAG debug
302 EXPORT(ejtag_debug_buffer)
309 * NMI debug exception handler for MIPS reference boards.
310 * The NMI debug exception entry point is 0xbfc00000, which
311 * normally is in the boot PROM, so the boot PROM must do a
312 * unconditional jump to this vector.
314 NESTED(except_vec_nmi, 0, sp)
316 #ifdef CONFIG_CPU_MICROMIPS
323 NESTED(nmi_handler, PT_SIZE, sp)
327 * Clear ERL - restore segment mapping
328 * Clear BEV - required for page fault exception handler to work
332 li k1, ~(ST0_BEV | ST0_ERL)
338 jal nmi_exception_handler
339 /* nmi_exception_handler never returns */
343 .macro __build_clear_none
346 .macro __build_clear_sti
351 .macro __build_clear_cli
356 .macro __build_clear_fpe
358 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
367 .macro __build_clear_msa_fpe
373 .macro __build_clear_ade
374 MFC0 t0, CP0_BADVADDR
375 PTR_S t0, PT_BVADDR(sp)
379 .macro __BUILD_silent exception
382 /* Gas tries to parse the PRINT argument as a string containing
383 string escapes and emits bogus warnings if it believes to
384 recognize an unknown escape code. So make the arguments
385 start with an n and gas will believe \n is ok ... */
386 .macro __BUILD_verbose nexception
387 LONG_L a1, PT_EPC(sp)
389 PRINT("Got \nexception at %08lx\012")
392 PRINT("Got \nexception at %016lx\012")
396 .macro __BUILD_count exception
397 LONG_L t0,exception_count_\exception
399 LONG_S t0,exception_count_\exception
400 .comm exception_count\exception, 8, 8
403 .macro __BUILD_HANDLER exception handler clear verbose ext
405 NESTED(handle_\exception, PT_SIZE, sp)
408 FEXPORT(handle_\exception\ext)
411 __BUILD_\verbose \exception
413 PTR_LA ra, ret_from_exception
415 END(handle_\exception)
418 .macro BUILD_HANDLER exception handler clear verbose
419 __BUILD_HANDLER \exception \handler \clear \verbose _int
422 BUILD_HANDLER adel ade ade silent /* #4 */
423 BUILD_HANDLER ades ade ade silent /* #5 */
424 BUILD_HANDLER ibe be cli silent /* #6 */
425 BUILD_HANDLER dbe be cli silent /* #7 */
426 BUILD_HANDLER bp bp sti silent /* #9 */
427 BUILD_HANDLER ri ri sti silent /* #10 */
428 BUILD_HANDLER cpu cpu sti silent /* #11 */
429 BUILD_HANDLER ov ov sti silent /* #12 */
430 BUILD_HANDLER tr tr sti silent /* #13 */
431 BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */
432 BUILD_HANDLER fpe fpe fpe silent /* #15 */
433 BUILD_HANDLER ftlb ftlb none silent /* #16 */
434 BUILD_HANDLER msa msa sti silent /* #21 */
435 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
436 #ifdef CONFIG_HARDWARE_WATCHPOINTS
438 * For watch, interrupts will be enabled after the watch
439 * registers are read.
441 BUILD_HANDLER watch watch cli silent /* #23 */
443 BUILD_HANDLER watch watch sti verbose /* #23 */
445 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
446 BUILD_HANDLER mt mt sti silent /* #25 */
447 BUILD_HANDLER dsp dsp sti silent /* #26 */
448 BUILD_HANDLER reserved reserved sti verbose /* others */
451 LEAF(handle_ri_rdhwr_vivt)
455 /* check if TLB contains a entry for EPC */
457 andi k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX
459 PTR_SRL k0, _PAGE_SHIFT + 1
460 PTR_SLL k0, _PAGE_SHIFT + 1
468 bltz k1, handle_ri /* slow path */
470 END(handle_ri_rdhwr_vivt)
472 LEAF(handle_ri_rdhwr)
476 /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */
477 /* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
479 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
502 bne k0, k1, handle_ri /* if not ours */
505 /* The insn is rdhwr. No need to check CAUSE.BD here. */
506 get_saved_sp /* k1 := current_thread_info */
509 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
511 xori k1, _THREAD_MASK
512 LONG_L v1, TI_TP_VALUE(k1)
517 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
518 LONG_ADDIU k0, 4 /* stall on $k0 */
525 /* I hope three instructions between MTC0 and ERET are enough... */
527 xori k1, _THREAD_MASK
528 LONG_L v1, TI_TP_VALUE(k1)
537 /* A temporary overflow handler used by check_daddi(). */
541 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */