2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <linux/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37 EXPORT_SYMBOL_GPL(elf_hwcap);
39 #ifdef CONFIG_MIPS_FP_SUPPORT
42 * Get the FPU Implementation/Revision.
44 static inline unsigned long cpu_get_fpu_id(void)
46 unsigned long tmp, fpu_id;
48 tmp = read_c0_status();
49 __enable_fpu(FPU_AS_IS);
50 fpu_id = read_32bit_cp1_register(CP1_REVISION);
56 * Check if the CPU has an external FPU.
58 static inline int __cpu_has_fpu(void)
60 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
64 * Determine the FCSR mask for FPU hardware.
66 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
68 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
71 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
73 sr = read_c0_status();
74 __enable_fpu(FPU_AS_IS);
77 write_32bit_cp1_register(CP1_STATUS, fcsr0);
78 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
81 write_32bit_cp1_register(CP1_STATUS, fcsr1);
82 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
84 write_32bit_cp1_register(CP1_STATUS, fcsr);
88 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
92 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
93 * supported by FPU hardware.
95 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
97 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
98 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
99 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
100 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
102 sr = read_c0_status();
103 __enable_fpu(FPU_AS_IS);
105 fir = read_32bit_cp1_register(CP1_REVISION);
106 if (fir & MIPS_FPIR_HAS2008) {
107 fcsr = read_32bit_cp1_register(CP1_STATUS);
109 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
110 write_32bit_cp1_register(CP1_STATUS, fcsr0);
111 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
113 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
114 write_32bit_cp1_register(CP1_STATUS, fcsr1);
115 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
117 write_32bit_cp1_register(CP1_STATUS, fcsr);
119 if (!(fcsr0 & FPU_CSR_NAN2008))
120 c->options |= MIPS_CPU_NAN_LEGACY;
121 if (fcsr1 & FPU_CSR_NAN2008)
122 c->options |= MIPS_CPU_NAN_2008;
124 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
125 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
127 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
129 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
130 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
132 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
134 c->options |= MIPS_CPU_NAN_LEGACY;
139 c->options |= MIPS_CPU_NAN_LEGACY;
144 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
145 * ABS.fmt/NEG.fmt execution mode.
147 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
150 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
151 * to support by the FPU emulator according to the IEEE 754 conformance
152 * mode selected. Note that "relaxed" straps the emulator so that it
153 * allows 2008-NaN binaries even for legacy processors.
155 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
157 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
158 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
159 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
163 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
164 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
165 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
166 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
168 c->options |= MIPS_CPU_NAN_LEGACY;
169 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
173 c->options |= MIPS_CPU_NAN_LEGACY;
174 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
177 c->options |= MIPS_CPU_NAN_2008;
178 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
182 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
188 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
189 * according to the "ieee754=" parameter.
191 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
195 mips_use_nan_legacy = !!cpu_has_nan_legacy;
196 mips_use_nan_2008 = !!cpu_has_nan_2008;
199 mips_use_nan_legacy = !!cpu_has_nan_legacy;
200 mips_use_nan_2008 = !cpu_has_nan_legacy;
203 mips_use_nan_legacy = !cpu_has_nan_2008;
204 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 mips_use_nan_legacy = true;
208 mips_use_nan_2008 = true;
214 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
217 * strict: accept binaries that request a NaN encoding supported by the FPU
218 * legacy: only accept legacy-NaN binaries
219 * 2008: only accept 2008-NaN binaries
220 * relaxed: accept any binaries regardless of whether supported by the FPU
222 static int __init ieee754_setup(char *s)
226 else if (!strcmp(s, "strict"))
228 else if (!strcmp(s, "legacy"))
230 else if (!strcmp(s, "2008"))
232 else if (!strcmp(s, "relaxed"))
237 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
238 cpu_set_nofpu_2008(&boot_cpu_data);
239 cpu_set_nan_2008(&boot_cpu_data);
244 early_param("ieee754", ieee754_setup);
247 * Set the FIR feature flags for the FPU emulator.
249 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
254 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
255 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
256 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
257 value |= MIPS_FPIR_D | MIPS_FPIR_S;
258 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
259 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
260 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
261 if (c->options & MIPS_CPU_NAN_2008)
262 value |= MIPS_FPIR_HAS2008;
266 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
267 static unsigned int mips_nofpu_msk31;
270 * Set options for FPU hardware.
272 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
274 c->fpu_id = cpu_get_fpu_id();
275 mips_nofpu_msk31 = c->fpu_msk31;
277 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
278 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
279 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
280 if (c->fpu_id & MIPS_FPIR_3D)
281 c->ases |= MIPS_ASE_MIPS3D;
282 if (c->fpu_id & MIPS_FPIR_UFRP)
283 c->options |= MIPS_CPU_UFR;
284 if (c->fpu_id & MIPS_FPIR_FREP)
285 c->options |= MIPS_CPU_FRE;
288 cpu_set_fpu_fcsr_mask(c);
294 * Set options for the FPU emulator.
296 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
298 c->options &= ~MIPS_CPU_FPU;
299 c->fpu_msk31 = mips_nofpu_msk31;
301 cpu_set_nofpu_2008(c);
306 static int mips_fpu_disabled;
308 static int __init fpu_disable(char *s)
310 cpu_set_nofpu_opts(&boot_cpu_data);
311 mips_fpu_disabled = 1;
316 __setup("nofpu", fpu_disable);
318 #else /* !CONFIG_MIPS_FP_SUPPORT */
320 #define mips_fpu_disabled 1
322 static inline unsigned long cpu_get_fpu_id(void)
324 return FPIR_IMP_NONE;
327 static inline int __cpu_has_fpu(void)
332 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
337 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
342 #endif /* CONFIG_MIPS_FP_SUPPORT */
344 static inline unsigned long cpu_get_msa_id(void)
346 unsigned long status, msa_id;
348 status = read_c0_status();
349 __enable_fpu(FPU_64BIT);
351 msa_id = read_msa_ir();
353 write_c0_status(status);
357 static int mips_dsp_disabled;
359 static int __init dsp_disable(char *s)
361 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
362 mips_dsp_disabled = 1;
367 __setup("nodsp", dsp_disable);
369 static int mips_htw_disabled;
371 static int __init htw_disable(char *s)
373 mips_htw_disabled = 1;
374 cpu_data[0].options &= ~MIPS_CPU_HTW;
375 write_c0_pwctl(read_c0_pwctl() &
376 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
381 __setup("nohtw", htw_disable);
383 static int mips_ftlb_disabled;
384 static int mips_has_ftlb_configured;
388 FTLB_SET_PROB = 1 << 1,
391 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
393 static int __init ftlb_disable(char *s)
395 unsigned int config4, mmuextdef;
398 * If the core hasn't done any FTLB configuration, there is nothing
401 if (!mips_has_ftlb_configured)
404 /* Disable it in the boot cpu */
405 if (set_ftlb_enable(&cpu_data[0], 0)) {
406 pr_warn("Can't turn FTLB off\n");
410 config4 = read_c0_config4();
412 /* Check that FTLB has been disabled */
413 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
414 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
415 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
416 /* This should never happen */
417 pr_warn("FTLB could not be disabled!\n");
421 mips_ftlb_disabled = 1;
422 mips_has_ftlb_configured = 0;
425 * noftlb is mainly used for debug purposes so print
426 * an informative message instead of using pr_debug()
428 pr_info("FTLB has been disabled\n");
431 * Some of these bits are duplicated in the decode_config4.
432 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
433 * once FTLB has been disabled so undo what decode_config4 did.
435 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
436 cpu_data[0].tlbsizeftlbsets;
437 cpu_data[0].tlbsizeftlbsets = 0;
438 cpu_data[0].tlbsizeftlbways = 0;
443 __setup("noftlb", ftlb_disable);
446 * Check if the CPU has per tc perf counters
448 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
450 if (read_c0_config7() & MTI_CONF7_PTC)
451 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
454 static inline void check_errata(void)
456 struct cpuinfo_mips *c = ¤t_cpu_data;
458 switch (current_cpu_type()) {
461 * Erratum "RPS May Cause Incorrect Instruction Execution"
462 * This code only handles VPE0, any SMP/RTOS code
463 * making use of VPE1 will be responsable for that VPE.
465 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
466 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
473 void __init check_bugs32(void)
479 * Probe whether cpu has config register by trying to play with
480 * alternate cache bit and see whether it matters.
481 * It's used by cpu_probe to distinguish between R3000A and R3081.
483 static inline int cpu_has_confreg(void)
485 #ifdef CONFIG_CPU_R3000
486 extern unsigned long r3k_cache_size(unsigned long);
487 unsigned long size1, size2;
488 unsigned long cfg = read_c0_conf();
490 size1 = r3k_cache_size(ST0_ISC);
491 write_c0_conf(cfg ^ R30XX_CONF_AC);
492 size2 = r3k_cache_size(ST0_ISC);
494 return size1 != size2;
500 static inline void set_elf_platform(int cpu, const char *plat)
503 __elf_platform = plat;
506 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
508 #ifdef __NEED_VMBITS_PROBE
509 write_c0_entryhi(0x3fffffffffffe000ULL);
510 back_to_back_c0_hazard();
511 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
515 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
518 case MIPS_CPU_ISA_M64R2:
519 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
521 case MIPS_CPU_ISA_M64R1:
522 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
525 c->isa_level |= MIPS_CPU_ISA_V;
527 case MIPS_CPU_ISA_IV:
528 c->isa_level |= MIPS_CPU_ISA_IV;
530 case MIPS_CPU_ISA_III:
531 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
534 /* R6 incompatible with everything else */
535 case MIPS_CPU_ISA_M64R6:
536 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
538 case MIPS_CPU_ISA_M32R6:
539 c->isa_level |= MIPS_CPU_ISA_M32R6;
540 /* Break here so we don't add incompatible ISAs */
542 case MIPS_CPU_ISA_M32R2:
543 c->isa_level |= MIPS_CPU_ISA_M32R2;
545 case MIPS_CPU_ISA_M32R1:
546 c->isa_level |= MIPS_CPU_ISA_M32R1;
548 case MIPS_CPU_ISA_II:
549 c->isa_level |= MIPS_CPU_ISA_II;
554 static char unknown_isa[] = KERN_ERR \
555 "Unsupported ISA type, c0.config0: %d.";
557 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
560 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
563 * 0 = All TLBWR instructions go to FTLB
564 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
565 * FTLB and 1 goes to the VTLB.
566 * 2 = 7:1: As above with 7:1 ratio.
567 * 3 = 3:1: As above with 3:1 ratio.
569 * Use the linear midpoint as the probability threshold.
571 if (probability >= 12)
573 else if (probability >= 6)
577 * So FTLB is less than 4 times bigger than VTLB.
578 * A 3:1 ratio can still be useful though.
583 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
587 /* It's implementation dependent how the FTLB can be enabled */
588 switch (c->cputype) {
592 /* proAptiv & related cores use Config6 to enable the FTLB */
593 config = read_c0_config6();
596 config |= MIPS_CONF6_FTLBEN;
598 config &= ~MIPS_CONF6_FTLBEN;
600 if (flags & FTLB_SET_PROB) {
601 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
602 config |= calculate_ftlb_probability(c)
603 << MIPS_CONF6_FTLBP_SHIFT;
606 write_c0_config6(config);
607 back_to_back_c0_hazard();
611 /* There's no way to disable the FTLB */
612 if (!(flags & FTLB_EN))
616 /* Flush ITLB, DTLB, VTLB and FTLB */
617 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
618 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
619 /* Loongson-3 cores use Config6 to enable the FTLB */
620 config = read_c0_config6();
623 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
626 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
635 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
637 unsigned int config0;
640 config0 = read_c0_config();
643 * Look for Standard TLB or Dual VTLB and FTLB
645 mt = config0 & MIPS_CONF_MT;
646 if (mt == MIPS_CONF_MT_TLB)
647 c->options |= MIPS_CPU_TLB;
648 else if (mt == MIPS_CONF_MT_FTLB)
649 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
651 isa = (config0 & MIPS_CONF_AT) >> 13;
654 switch ((config0 & MIPS_CONF_AR) >> 10) {
656 set_isa(c, MIPS_CPU_ISA_M32R1);
659 set_isa(c, MIPS_CPU_ISA_M32R2);
662 set_isa(c, MIPS_CPU_ISA_M32R6);
669 switch ((config0 & MIPS_CONF_AR) >> 10) {
671 set_isa(c, MIPS_CPU_ISA_M64R1);
674 set_isa(c, MIPS_CPU_ISA_M64R2);
677 set_isa(c, MIPS_CPU_ISA_M64R6);
687 return config0 & MIPS_CONF_M;
690 panic(unknown_isa, config0);
693 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
695 unsigned int config1;
697 config1 = read_c0_config1();
699 if (config1 & MIPS_CONF1_MD)
700 c->ases |= MIPS_ASE_MDMX;
701 if (config1 & MIPS_CONF1_PC)
702 c->options |= MIPS_CPU_PERF;
703 if (config1 & MIPS_CONF1_WR)
704 c->options |= MIPS_CPU_WATCH;
705 if (config1 & MIPS_CONF1_CA)
706 c->ases |= MIPS_ASE_MIPS16;
707 if (config1 & MIPS_CONF1_EP)
708 c->options |= MIPS_CPU_EJTAG;
709 if (config1 & MIPS_CONF1_FP) {
710 c->options |= MIPS_CPU_FPU;
711 c->options |= MIPS_CPU_32FPR;
714 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
715 c->tlbsizevtlb = c->tlbsize;
716 c->tlbsizeftlbsets = 0;
719 return config1 & MIPS_CONF_M;
722 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
724 unsigned int config2;
726 config2 = read_c0_config2();
728 if (config2 & MIPS_CONF2_SL)
729 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
731 return config2 & MIPS_CONF_M;
734 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
736 unsigned int config3;
738 config3 = read_c0_config3();
740 if (config3 & MIPS_CONF3_SM) {
741 c->ases |= MIPS_ASE_SMARTMIPS;
742 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
744 if (config3 & MIPS_CONF3_RXI)
745 c->options |= MIPS_CPU_RIXI;
746 if (config3 & MIPS_CONF3_CTXTC)
747 c->options |= MIPS_CPU_CTXTC;
748 if (config3 & MIPS_CONF3_DSP)
749 c->ases |= MIPS_ASE_DSP;
750 if (config3 & MIPS_CONF3_DSP2P) {
751 c->ases |= MIPS_ASE_DSP2P;
753 c->ases |= MIPS_ASE_DSP3;
755 if (config3 & MIPS_CONF3_VINT)
756 c->options |= MIPS_CPU_VINT;
757 if (config3 & MIPS_CONF3_VEIC)
758 c->options |= MIPS_CPU_VEIC;
759 if (config3 & MIPS_CONF3_LPA)
760 c->options |= MIPS_CPU_LPA;
761 if (config3 & MIPS_CONF3_MT)
762 c->ases |= MIPS_ASE_MIPSMT;
763 if (config3 & MIPS_CONF3_ULRI)
764 c->options |= MIPS_CPU_ULRI;
765 if (config3 & MIPS_CONF3_ISA)
766 c->options |= MIPS_CPU_MICROMIPS;
767 if (config3 & MIPS_CONF3_VZ)
768 c->ases |= MIPS_ASE_VZ;
769 if (config3 & MIPS_CONF3_SC)
770 c->options |= MIPS_CPU_SEGMENTS;
771 if (config3 & MIPS_CONF3_BI)
772 c->options |= MIPS_CPU_BADINSTR;
773 if (config3 & MIPS_CONF3_BP)
774 c->options |= MIPS_CPU_BADINSTRP;
775 if (config3 & MIPS_CONF3_MSA)
776 c->ases |= MIPS_ASE_MSA;
777 if (config3 & MIPS_CONF3_PW) {
779 c->options |= MIPS_CPU_HTW;
781 if (config3 & MIPS_CONF3_CDMM)
782 c->options |= MIPS_CPU_CDMM;
783 if (config3 & MIPS_CONF3_SP)
784 c->options |= MIPS_CPU_SP;
786 return config3 & MIPS_CONF_M;
789 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
791 unsigned int config4;
793 unsigned int mmuextdef;
794 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
795 unsigned long asid_mask;
797 config4 = read_c0_config4();
800 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
801 c->options |= MIPS_CPU_TLBINV;
804 * R6 has dropped the MMUExtDef field from config4.
805 * On R6 the fields always describe the FTLB, and only if it is
806 * present according to Config.MT.
808 if (!cpu_has_mips_r6)
809 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
810 else if (cpu_has_ftlb)
811 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
816 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
817 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
818 c->tlbsizevtlb = c->tlbsize;
820 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
822 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
823 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
824 c->tlbsize = c->tlbsizevtlb;
825 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
827 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
828 if (mips_ftlb_disabled)
830 newcf4 = (config4 & ~ftlb_page) |
831 (page_size_ftlb(mmuextdef) <<
832 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
833 write_c0_config4(newcf4);
834 back_to_back_c0_hazard();
835 config4 = read_c0_config4();
836 if (config4 != newcf4) {
837 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
839 /* Switch FTLB off */
840 set_ftlb_enable(c, 0);
841 mips_ftlb_disabled = 1;
844 c->tlbsizeftlbsets = 1 <<
845 ((config4 & MIPS_CONF4_FTLBSETS) >>
846 MIPS_CONF4_FTLBSETS_SHIFT);
847 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
848 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
849 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
850 mips_has_ftlb_configured = 1;
855 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
856 >> MIPS_CONF4_KSCREXIST_SHIFT;
858 asid_mask = MIPS_ENTRYHI_ASID;
859 if (config4 & MIPS_CONF4_AE)
860 asid_mask |= MIPS_ENTRYHI_ASIDX;
861 set_cpu_asid_mask(c, asid_mask);
864 * Warn if the computed ASID mask doesn't match the mask the kernel
865 * is built for. This may indicate either a serious problem or an
866 * easy optimisation opportunity, but either way should be addressed.
868 WARN_ON(asid_mask != cpu_asid_mask(c));
870 return config4 & MIPS_CONF_M;
873 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
875 unsigned int config5, max_mmid_width;
876 unsigned long asid_mask;
878 config5 = read_c0_config5();
879 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
881 if (cpu_has_mips_r6) {
882 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
883 config5 |= MIPS_CONF5_MI;
885 config5 &= ~MIPS_CONF5_MI;
888 write_c0_config5(config5);
890 if (config5 & MIPS_CONF5_EVA)
891 c->options |= MIPS_CPU_EVA;
892 if (config5 & MIPS_CONF5_MRP)
893 c->options |= MIPS_CPU_MAAR;
894 if (config5 & MIPS_CONF5_LLB)
895 c->options |= MIPS_CPU_RW_LLB;
896 if (config5 & MIPS_CONF5_MVH)
897 c->options |= MIPS_CPU_MVH;
898 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
899 c->options |= MIPS_CPU_VP;
900 if (config5 & MIPS_CONF5_CA2)
901 c->ases |= MIPS_ASE_MIPS16E2;
903 if (config5 & MIPS_CONF5_CRCP)
904 elf_hwcap |= HWCAP_MIPS_CRC32;
906 if (cpu_has_mips_r6) {
907 /* Ensure the write to config5 above takes effect */
908 back_to_back_c0_hazard();
910 /* Check whether we successfully enabled MMID support */
911 config5 = read_c0_config5();
912 if (config5 & MIPS_CONF5_MI)
913 c->options |= MIPS_CPU_MMID;
916 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
917 * for the CPU we're running on, or if CPUs in an SMP system
918 * have inconsistent MMID support.
920 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
923 write_c0_memorymapid(~0ul);
924 back_to_back_c0_hazard();
925 asid_mask = read_c0_memorymapid();
928 * We maintain a bitmap to track MMID allocation, and
929 * need a sensible upper bound on the size of that
930 * bitmap. The initial CPU with MMID support (I6500)
931 * supports 16 bit MMIDs, which gives us an 8KiB
932 * bitmap. The architecture recommends that hardware
933 * support 32 bit MMIDs, which would give us a 512MiB
934 * bitmap - that's too big in most cases.
936 * Cap MMID width at 16 bits for now & we can revisit
937 * this if & when hardware supports anything wider.
940 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
941 pr_info("Capping MMID width at %d bits",
943 asid_mask = GENMASK(max_mmid_width - 1, 0);
946 set_cpu_asid_mask(c, asid_mask);
950 return config5 & MIPS_CONF_M;
953 static void decode_configs(struct cpuinfo_mips *c)
957 /* MIPS32 or MIPS64 compliant CPU. */
958 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
959 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
961 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
963 /* Enable FTLB if present and not disabled */
964 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
966 ok = decode_config0(c); /* Read Config registers. */
967 BUG_ON(!ok); /* Arch spec violation! */
969 ok = decode_config1(c);
971 ok = decode_config2(c);
973 ok = decode_config3(c);
975 ok = decode_config4(c);
977 ok = decode_config5(c);
979 /* Probe the EBase.WG bit */
980 if (cpu_has_mips_r2_r6) {
984 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
985 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
986 : (s32)read_c0_ebase();
987 if (ebase & MIPS_EBASE_WG) {
988 /* WG bit already set, we can avoid the clumsy probe */
989 c->options |= MIPS_CPU_EBASE_WG;
991 /* Its UNDEFINED to change EBase while BEV=0 */
992 status = read_c0_status();
993 write_c0_status(status | ST0_BEV);
996 * On pre-r6 cores, this may well clobber the upper bits
997 * of EBase. This is hard to avoid without potentially
998 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
1000 if (cpu_has_mips64r6)
1001 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1003 write_c0_ebase(ebase | MIPS_EBASE_WG);
1004 back_to_back_c0_hazard();
1006 write_c0_status(status);
1007 if (read_c0_ebase() & MIPS_EBASE_WG) {
1008 c->options |= MIPS_CPU_EBASE_WG;
1009 write_c0_ebase(ebase);
1014 /* configure the FTLB write probability */
1015 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1017 mips_probe_watch_registers(c);
1019 #ifndef CONFIG_MIPS_CPS
1020 if (cpu_has_mips_r2_r6) {
1023 core = get_ebase_cpunum();
1025 core >>= fls(core_nvpes()) - 1;
1026 cpu_set_core(c, core);
1032 * Probe for certain guest capabilities by writing config bits and reading back.
1033 * Finally write back the original value.
1035 #define probe_gc0_config(name, maxconf, bits) \
1038 tmp = read_gc0_##name(); \
1039 write_gc0_##name(tmp | (bits)); \
1040 back_to_back_c0_hazard(); \
1041 maxconf = read_gc0_##name(); \
1042 write_gc0_##name(tmp); \
1046 * Probe for dynamic guest capabilities by changing certain config bits and
1047 * reading back to see if they change. Finally write back the original value.
1049 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1051 maxconf = read_gc0_##name(); \
1052 write_gc0_##name(maxconf ^ (bits)); \
1053 back_to_back_c0_hazard(); \
1054 dynconf = maxconf ^ read_gc0_##name(); \
1055 write_gc0_##name(maxconf); \
1056 maxconf |= dynconf; \
1059 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1061 unsigned int config0;
1063 probe_gc0_config(config, config0, MIPS_CONF_M);
1065 if (config0 & MIPS_CONF_M)
1066 c->guest.conf |= BIT(1);
1067 return config0 & MIPS_CONF_M;
1070 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1072 unsigned int config1, config1_dyn;
1074 probe_gc0_config_dyn(config1, config1, config1_dyn,
1075 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1078 if (config1 & MIPS_CONF1_FP)
1079 c->guest.options |= MIPS_CPU_FPU;
1080 if (config1_dyn & MIPS_CONF1_FP)
1081 c->guest.options_dyn |= MIPS_CPU_FPU;
1083 if (config1 & MIPS_CONF1_WR)
1084 c->guest.options |= MIPS_CPU_WATCH;
1085 if (config1_dyn & MIPS_CONF1_WR)
1086 c->guest.options_dyn |= MIPS_CPU_WATCH;
1088 if (config1 & MIPS_CONF1_PC)
1089 c->guest.options |= MIPS_CPU_PERF;
1090 if (config1_dyn & MIPS_CONF1_PC)
1091 c->guest.options_dyn |= MIPS_CPU_PERF;
1093 if (config1 & MIPS_CONF_M)
1094 c->guest.conf |= BIT(2);
1095 return config1 & MIPS_CONF_M;
1098 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1100 unsigned int config2;
1102 probe_gc0_config(config2, config2, MIPS_CONF_M);
1104 if (config2 & MIPS_CONF_M)
1105 c->guest.conf |= BIT(3);
1106 return config2 & MIPS_CONF_M;
1109 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1111 unsigned int config3, config3_dyn;
1113 probe_gc0_config_dyn(config3, config3, config3_dyn,
1114 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1117 if (config3 & MIPS_CONF3_CTXTC)
1118 c->guest.options |= MIPS_CPU_CTXTC;
1119 if (config3_dyn & MIPS_CONF3_CTXTC)
1120 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1122 if (config3 & MIPS_CONF3_PW)
1123 c->guest.options |= MIPS_CPU_HTW;
1125 if (config3 & MIPS_CONF3_ULRI)
1126 c->guest.options |= MIPS_CPU_ULRI;
1128 if (config3 & MIPS_CONF3_SC)
1129 c->guest.options |= MIPS_CPU_SEGMENTS;
1131 if (config3 & MIPS_CONF3_BI)
1132 c->guest.options |= MIPS_CPU_BADINSTR;
1133 if (config3 & MIPS_CONF3_BP)
1134 c->guest.options |= MIPS_CPU_BADINSTRP;
1136 if (config3 & MIPS_CONF3_MSA)
1137 c->guest.ases |= MIPS_ASE_MSA;
1138 if (config3_dyn & MIPS_CONF3_MSA)
1139 c->guest.ases_dyn |= MIPS_ASE_MSA;
1141 if (config3 & MIPS_CONF_M)
1142 c->guest.conf |= BIT(4);
1143 return config3 & MIPS_CONF_M;
1146 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1148 unsigned int config4;
1150 probe_gc0_config(config4, config4,
1151 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1153 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1154 >> MIPS_CONF4_KSCREXIST_SHIFT;
1156 if (config4 & MIPS_CONF_M)
1157 c->guest.conf |= BIT(5);
1158 return config4 & MIPS_CONF_M;
1161 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1163 unsigned int config5, config5_dyn;
1165 probe_gc0_config_dyn(config5, config5, config5_dyn,
1166 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1168 if (config5 & MIPS_CONF5_MRP)
1169 c->guest.options |= MIPS_CPU_MAAR;
1170 if (config5_dyn & MIPS_CONF5_MRP)
1171 c->guest.options_dyn |= MIPS_CPU_MAAR;
1173 if (config5 & MIPS_CONF5_LLB)
1174 c->guest.options |= MIPS_CPU_RW_LLB;
1176 if (config5 & MIPS_CONF5_MVH)
1177 c->guest.options |= MIPS_CPU_MVH;
1179 if (config5 & MIPS_CONF_M)
1180 c->guest.conf |= BIT(6);
1181 return config5 & MIPS_CONF_M;
1184 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1188 ok = decode_guest_config0(c);
1190 ok = decode_guest_config1(c);
1192 ok = decode_guest_config2(c);
1194 ok = decode_guest_config3(c);
1196 ok = decode_guest_config4(c);
1198 decode_guest_config5(c);
1201 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1203 unsigned int guestctl0, temp;
1205 guestctl0 = read_c0_guestctl0();
1207 if (guestctl0 & MIPS_GCTL0_G0E)
1208 c->options |= MIPS_CPU_GUESTCTL0EXT;
1209 if (guestctl0 & MIPS_GCTL0_G1)
1210 c->options |= MIPS_CPU_GUESTCTL1;
1211 if (guestctl0 & MIPS_GCTL0_G2)
1212 c->options |= MIPS_CPU_GUESTCTL2;
1213 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1214 c->options |= MIPS_CPU_GUESTID;
1217 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1218 * first, otherwise all data accesses will be fully virtualised
1219 * as if they were performed by guest mode.
1221 write_c0_guestctl1(0);
1224 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1225 back_to_back_c0_hazard();
1226 temp = read_c0_guestctl0();
1228 if (temp & MIPS_GCTL0_DRG) {
1229 write_c0_guestctl0(guestctl0);
1230 c->options |= MIPS_CPU_DRG;
1235 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1237 if (cpu_has_guestid) {
1238 /* determine the number of bits of GuestID available */
1239 write_c0_guestctl1(MIPS_GCTL1_ID);
1240 back_to_back_c0_hazard();
1241 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1242 >> MIPS_GCTL1_ID_SHIFT;
1243 write_c0_guestctl1(0);
1247 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1249 /* determine the number of bits of GTOffset available */
1250 write_c0_gtoffset(0xffffffff);
1251 back_to_back_c0_hazard();
1252 c->gtoffset_mask = read_c0_gtoffset();
1253 write_c0_gtoffset(0);
1256 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1258 cpu_probe_guestctl0(c);
1259 if (cpu_has_guestctl1)
1260 cpu_probe_guestctl1(c);
1262 cpu_probe_gtoffset(c);
1264 decode_guest_configs(c);
1267 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1270 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1272 switch (c->processor_id & PRID_IMP_MASK) {
1273 case PRID_IMP_R2000:
1274 c->cputype = CPU_R2000;
1275 __cpu_name[cpu] = "R2000";
1276 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1277 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1279 if (__cpu_has_fpu())
1280 c->options |= MIPS_CPU_FPU;
1283 case PRID_IMP_R3000:
1284 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1285 if (cpu_has_confreg()) {
1286 c->cputype = CPU_R3081E;
1287 __cpu_name[cpu] = "R3081";
1289 c->cputype = CPU_R3000A;
1290 __cpu_name[cpu] = "R3000A";
1293 c->cputype = CPU_R3000;
1294 __cpu_name[cpu] = "R3000";
1296 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1297 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1299 if (__cpu_has_fpu())
1300 c->options |= MIPS_CPU_FPU;
1303 case PRID_IMP_R4000:
1304 if (read_c0_config() & CONF_SC) {
1305 if ((c->processor_id & PRID_REV_MASK) >=
1307 c->cputype = CPU_R4400PC;
1308 __cpu_name[cpu] = "R4400PC";
1310 c->cputype = CPU_R4000PC;
1311 __cpu_name[cpu] = "R4000PC";
1314 int cca = read_c0_config() & CONF_CM_CMASK;
1318 * SC and MC versions can't be reliably told apart,
1319 * but only the latter support coherent caching
1320 * modes so assume the firmware has set the KSEG0
1321 * coherency attribute reasonably (if uncached, we
1325 case CONF_CM_CACHABLE_CE:
1326 case CONF_CM_CACHABLE_COW:
1327 case CONF_CM_CACHABLE_CUW:
1334 if ((c->processor_id & PRID_REV_MASK) >=
1336 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1337 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1339 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1340 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1344 set_isa(c, MIPS_CPU_ISA_III);
1345 c->fpu_msk31 |= FPU_CSR_CONDX;
1346 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1347 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1351 case PRID_IMP_VR41XX:
1352 set_isa(c, MIPS_CPU_ISA_III);
1353 c->fpu_msk31 |= FPU_CSR_CONDX;
1354 c->options = R4K_OPTS;
1356 switch (c->processor_id & 0xf0) {
1357 case PRID_REV_VR4111:
1358 c->cputype = CPU_VR4111;
1359 __cpu_name[cpu] = "NEC VR4111";
1361 case PRID_REV_VR4121:
1362 c->cputype = CPU_VR4121;
1363 __cpu_name[cpu] = "NEC VR4121";
1365 case PRID_REV_VR4122:
1366 if ((c->processor_id & 0xf) < 0x3) {
1367 c->cputype = CPU_VR4122;
1368 __cpu_name[cpu] = "NEC VR4122";
1370 c->cputype = CPU_VR4181A;
1371 __cpu_name[cpu] = "NEC VR4181A";
1374 case PRID_REV_VR4130:
1375 if ((c->processor_id & 0xf) < 0x4) {
1376 c->cputype = CPU_VR4131;
1377 __cpu_name[cpu] = "NEC VR4131";
1379 c->cputype = CPU_VR4133;
1380 c->options |= MIPS_CPU_LLSC;
1381 __cpu_name[cpu] = "NEC VR4133";
1385 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1386 c->cputype = CPU_VR41XX;
1387 __cpu_name[cpu] = "NEC Vr41xx";
1391 case PRID_IMP_R4300:
1392 c->cputype = CPU_R4300;
1393 __cpu_name[cpu] = "R4300";
1394 set_isa(c, MIPS_CPU_ISA_III);
1395 c->fpu_msk31 |= FPU_CSR_CONDX;
1396 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1400 case PRID_IMP_R4600:
1401 c->cputype = CPU_R4600;
1402 __cpu_name[cpu] = "R4600";
1403 set_isa(c, MIPS_CPU_ISA_III);
1404 c->fpu_msk31 |= FPU_CSR_CONDX;
1405 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1410 case PRID_IMP_R4650:
1412 * This processor doesn't have an MMU, so it's not
1413 * "real easy" to run Linux on it. It is left purely
1414 * for documentation. Commented out because it shares
1415 * it's c0_prid id number with the TX3900.
1417 c->cputype = CPU_R4650;
1418 __cpu_name[cpu] = "R4650";
1419 set_isa(c, MIPS_CPU_ISA_III);
1420 c->fpu_msk31 |= FPU_CSR_CONDX;
1421 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1426 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1427 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1429 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1430 c->cputype = CPU_TX3927;
1431 __cpu_name[cpu] = "TX3927";
1434 switch (c->processor_id & PRID_REV_MASK) {
1435 case PRID_REV_TX3912:
1436 c->cputype = CPU_TX3912;
1437 __cpu_name[cpu] = "TX3912";
1440 case PRID_REV_TX3922:
1441 c->cputype = CPU_TX3922;
1442 __cpu_name[cpu] = "TX3922";
1448 case PRID_IMP_R4700:
1449 c->cputype = CPU_R4700;
1450 __cpu_name[cpu] = "R4700";
1451 set_isa(c, MIPS_CPU_ISA_III);
1452 c->fpu_msk31 |= FPU_CSR_CONDX;
1453 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1458 c->cputype = CPU_TX49XX;
1459 __cpu_name[cpu] = "R49XX";
1460 set_isa(c, MIPS_CPU_ISA_III);
1461 c->fpu_msk31 |= FPU_CSR_CONDX;
1462 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1463 if (!(c->processor_id & 0x08))
1464 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1467 case PRID_IMP_R5000:
1468 c->cputype = CPU_R5000;
1469 __cpu_name[cpu] = "R5000";
1470 set_isa(c, MIPS_CPU_ISA_IV);
1471 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1475 case PRID_IMP_R5432:
1476 c->cputype = CPU_R5432;
1477 __cpu_name[cpu] = "R5432";
1478 set_isa(c, MIPS_CPU_ISA_IV);
1479 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1480 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1483 case PRID_IMP_R5500:
1484 c->cputype = CPU_R5500;
1485 __cpu_name[cpu] = "R5500";
1486 set_isa(c, MIPS_CPU_ISA_IV);
1487 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1488 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1491 case PRID_IMP_NEVADA:
1492 c->cputype = CPU_NEVADA;
1493 __cpu_name[cpu] = "Nevada";
1494 set_isa(c, MIPS_CPU_ISA_IV);
1495 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1496 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1499 case PRID_IMP_RM7000:
1500 c->cputype = CPU_RM7000;
1501 __cpu_name[cpu] = "RM7000";
1502 set_isa(c, MIPS_CPU_ISA_IV);
1503 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1506 * Undocumented RM7000: Bit 29 in the info register of
1507 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1510 * 29 1 => 64 entry JTLB
1511 * 0 => 48 entry JTLB
1513 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1515 case PRID_IMP_R8000:
1516 c->cputype = CPU_R8000;
1517 __cpu_name[cpu] = "RM8000";
1518 set_isa(c, MIPS_CPU_ISA_IV);
1519 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1520 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1522 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1524 case PRID_IMP_R10000:
1525 c->cputype = CPU_R10000;
1526 __cpu_name[cpu] = "R10000";
1527 set_isa(c, MIPS_CPU_ISA_IV);
1528 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1529 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1530 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1534 case PRID_IMP_R12000:
1535 c->cputype = CPU_R12000;
1536 __cpu_name[cpu] = "R12000";
1537 set_isa(c, MIPS_CPU_ISA_IV);
1538 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1539 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1540 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1541 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1544 case PRID_IMP_R14000:
1545 if (((c->processor_id >> 4) & 0x0f) > 2) {
1546 c->cputype = CPU_R16000;
1547 __cpu_name[cpu] = "R16000";
1549 c->cputype = CPU_R14000;
1550 __cpu_name[cpu] = "R14000";
1552 set_isa(c, MIPS_CPU_ISA_IV);
1553 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1554 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1555 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1556 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1559 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1560 switch (c->processor_id & PRID_REV_MASK) {
1561 case PRID_REV_LOONGSON2E:
1562 c->cputype = CPU_LOONGSON2;
1563 __cpu_name[cpu] = "ICT Loongson-2";
1564 set_elf_platform(cpu, "loongson2e");
1565 set_isa(c, MIPS_CPU_ISA_III);
1566 c->fpu_msk31 |= FPU_CSR_CONDX;
1568 case PRID_REV_LOONGSON2F:
1569 c->cputype = CPU_LOONGSON2;
1570 __cpu_name[cpu] = "ICT Loongson-2";
1571 set_elf_platform(cpu, "loongson2f");
1572 set_isa(c, MIPS_CPU_ISA_III);
1573 c->fpu_msk31 |= FPU_CSR_CONDX;
1575 case PRID_REV_LOONGSON3A_R1:
1576 c->cputype = CPU_LOONGSON3;
1577 __cpu_name[cpu] = "ICT Loongson-3";
1578 set_elf_platform(cpu, "loongson3a");
1579 set_isa(c, MIPS_CPU_ISA_M64R1);
1581 case PRID_REV_LOONGSON3B_R1:
1582 case PRID_REV_LOONGSON3B_R2:
1583 c->cputype = CPU_LOONGSON3;
1584 __cpu_name[cpu] = "ICT Loongson-3";
1585 set_elf_platform(cpu, "loongson3b");
1586 set_isa(c, MIPS_CPU_ISA_M64R1);
1590 c->options = R4K_OPTS |
1591 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1594 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1596 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1599 c->cputype = CPU_LOONGSON1;
1601 switch (c->processor_id & PRID_REV_MASK) {
1602 case PRID_REV_LOONGSON1B:
1603 __cpu_name[cpu] = "Loongson 1B";
1611 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1613 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1614 switch (c->processor_id & PRID_IMP_MASK) {
1615 case PRID_IMP_QEMU_GENERIC:
1616 c->writecombine = _CACHE_UNCACHED;
1617 c->cputype = CPU_QEMU_GENERIC;
1618 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1621 c->cputype = CPU_4KC;
1622 c->writecombine = _CACHE_UNCACHED;
1623 __cpu_name[cpu] = "MIPS 4Kc";
1626 case PRID_IMP_4KECR2:
1627 c->cputype = CPU_4KEC;
1628 c->writecombine = _CACHE_UNCACHED;
1629 __cpu_name[cpu] = "MIPS 4KEc";
1633 c->cputype = CPU_4KSC;
1634 c->writecombine = _CACHE_UNCACHED;
1635 __cpu_name[cpu] = "MIPS 4KSc";
1638 c->cputype = CPU_5KC;
1639 c->writecombine = _CACHE_UNCACHED;
1640 __cpu_name[cpu] = "MIPS 5Kc";
1643 c->cputype = CPU_5KE;
1644 c->writecombine = _CACHE_UNCACHED;
1645 __cpu_name[cpu] = "MIPS 5KE";
1648 c->cputype = CPU_20KC;
1649 c->writecombine = _CACHE_UNCACHED;
1650 __cpu_name[cpu] = "MIPS 20Kc";
1653 c->cputype = CPU_24K;
1654 c->writecombine = _CACHE_UNCACHED;
1655 __cpu_name[cpu] = "MIPS 24Kc";
1658 c->cputype = CPU_24K;
1659 c->writecombine = _CACHE_UNCACHED;
1660 __cpu_name[cpu] = "MIPS 24KEc";
1663 c->cputype = CPU_25KF;
1664 c->writecombine = _CACHE_UNCACHED;
1665 __cpu_name[cpu] = "MIPS 25Kc";
1668 c->cputype = CPU_34K;
1669 c->writecombine = _CACHE_UNCACHED;
1670 __cpu_name[cpu] = "MIPS 34Kc";
1671 cpu_set_mt_per_tc_perf(c);
1674 c->cputype = CPU_74K;
1675 c->writecombine = _CACHE_UNCACHED;
1676 __cpu_name[cpu] = "MIPS 74Kc";
1678 case PRID_IMP_M14KC:
1679 c->cputype = CPU_M14KC;
1680 c->writecombine = _CACHE_UNCACHED;
1681 __cpu_name[cpu] = "MIPS M14Kc";
1683 case PRID_IMP_M14KEC:
1684 c->cputype = CPU_M14KEC;
1685 c->writecombine = _CACHE_UNCACHED;
1686 __cpu_name[cpu] = "MIPS M14KEc";
1688 case PRID_IMP_1004K:
1689 c->cputype = CPU_1004K;
1690 c->writecombine = _CACHE_UNCACHED;
1691 __cpu_name[cpu] = "MIPS 1004Kc";
1692 cpu_set_mt_per_tc_perf(c);
1694 case PRID_IMP_1074K:
1695 c->cputype = CPU_1074K;
1696 c->writecombine = _CACHE_UNCACHED;
1697 __cpu_name[cpu] = "MIPS 1074Kc";
1699 case PRID_IMP_INTERAPTIV_UP:
1700 c->cputype = CPU_INTERAPTIV;
1701 __cpu_name[cpu] = "MIPS interAptiv";
1702 cpu_set_mt_per_tc_perf(c);
1704 case PRID_IMP_INTERAPTIV_MP:
1705 c->cputype = CPU_INTERAPTIV;
1706 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1707 cpu_set_mt_per_tc_perf(c);
1709 case PRID_IMP_PROAPTIV_UP:
1710 c->cputype = CPU_PROAPTIV;
1711 __cpu_name[cpu] = "MIPS proAptiv";
1713 case PRID_IMP_PROAPTIV_MP:
1714 c->cputype = CPU_PROAPTIV;
1715 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1717 case PRID_IMP_P5600:
1718 c->cputype = CPU_P5600;
1719 __cpu_name[cpu] = "MIPS P5600";
1721 case PRID_IMP_P6600:
1722 c->cputype = CPU_P6600;
1723 __cpu_name[cpu] = "MIPS P6600";
1725 case PRID_IMP_I6400:
1726 c->cputype = CPU_I6400;
1727 __cpu_name[cpu] = "MIPS I6400";
1729 case PRID_IMP_I6500:
1730 c->cputype = CPU_I6500;
1731 __cpu_name[cpu] = "MIPS I6500";
1733 case PRID_IMP_M5150:
1734 c->cputype = CPU_M5150;
1735 __cpu_name[cpu] = "MIPS M5150";
1737 case PRID_IMP_M6250:
1738 c->cputype = CPU_M6250;
1739 __cpu_name[cpu] = "MIPS M6250";
1747 switch (__get_cpu_type(c->cputype)) {
1749 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1752 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1759 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1762 switch (c->processor_id & PRID_IMP_MASK) {
1763 case PRID_IMP_AU1_REV1:
1764 case PRID_IMP_AU1_REV2:
1765 c->cputype = CPU_ALCHEMY;
1766 switch ((c->processor_id >> 24) & 0xff) {
1768 __cpu_name[cpu] = "Au1000";
1771 __cpu_name[cpu] = "Au1500";
1774 __cpu_name[cpu] = "Au1100";
1777 __cpu_name[cpu] = "Au1550";
1780 __cpu_name[cpu] = "Au1200";
1781 if ((c->processor_id & PRID_REV_MASK) == 2)
1782 __cpu_name[cpu] = "Au1250";
1785 __cpu_name[cpu] = "Au1210";
1788 __cpu_name[cpu] = "Au1xxx";
1795 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1799 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1800 switch (c->processor_id & PRID_IMP_MASK) {
1802 c->cputype = CPU_SB1;
1803 __cpu_name[cpu] = "SiByte SB1";
1804 /* FPU in pass1 is known to have issues. */
1805 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1806 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1809 c->cputype = CPU_SB1A;
1810 __cpu_name[cpu] = "SiByte SB1A";
1815 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1818 switch (c->processor_id & PRID_IMP_MASK) {
1819 case PRID_IMP_SR71000:
1820 c->cputype = CPU_SR71000;
1821 __cpu_name[cpu] = "Sandcraft SR71000";
1828 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1831 switch (c->processor_id & PRID_IMP_MASK) {
1832 case PRID_IMP_PR4450:
1833 c->cputype = CPU_PR4450;
1834 __cpu_name[cpu] = "Philips PR4450";
1835 set_isa(c, MIPS_CPU_ISA_M32R1);
1840 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1843 switch (c->processor_id & PRID_IMP_MASK) {
1844 case PRID_IMP_BMIPS32_REV4:
1845 case PRID_IMP_BMIPS32_REV8:
1846 c->cputype = CPU_BMIPS32;
1847 __cpu_name[cpu] = "Broadcom BMIPS32";
1848 set_elf_platform(cpu, "bmips32");
1850 case PRID_IMP_BMIPS3300:
1851 case PRID_IMP_BMIPS3300_ALT:
1852 case PRID_IMP_BMIPS3300_BUG:
1853 c->cputype = CPU_BMIPS3300;
1854 __cpu_name[cpu] = "Broadcom BMIPS3300";
1855 set_elf_platform(cpu, "bmips3300");
1857 case PRID_IMP_BMIPS43XX: {
1858 int rev = c->processor_id & PRID_REV_MASK;
1860 if (rev >= PRID_REV_BMIPS4380_LO &&
1861 rev <= PRID_REV_BMIPS4380_HI) {
1862 c->cputype = CPU_BMIPS4380;
1863 __cpu_name[cpu] = "Broadcom BMIPS4380";
1864 set_elf_platform(cpu, "bmips4380");
1865 c->options |= MIPS_CPU_RIXI;
1867 c->cputype = CPU_BMIPS4350;
1868 __cpu_name[cpu] = "Broadcom BMIPS4350";
1869 set_elf_platform(cpu, "bmips4350");
1873 case PRID_IMP_BMIPS5000:
1874 case PRID_IMP_BMIPS5200:
1875 c->cputype = CPU_BMIPS5000;
1876 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1877 __cpu_name[cpu] = "Broadcom BMIPS5200";
1879 __cpu_name[cpu] = "Broadcom BMIPS5000";
1880 set_elf_platform(cpu, "bmips5000");
1881 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1886 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1889 switch (c->processor_id & PRID_IMP_MASK) {
1890 case PRID_IMP_CAVIUM_CN38XX:
1891 case PRID_IMP_CAVIUM_CN31XX:
1892 case PRID_IMP_CAVIUM_CN30XX:
1893 c->cputype = CPU_CAVIUM_OCTEON;
1894 __cpu_name[cpu] = "Cavium Octeon";
1896 case PRID_IMP_CAVIUM_CN58XX:
1897 case PRID_IMP_CAVIUM_CN56XX:
1898 case PRID_IMP_CAVIUM_CN50XX:
1899 case PRID_IMP_CAVIUM_CN52XX:
1900 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1901 __cpu_name[cpu] = "Cavium Octeon+";
1903 set_elf_platform(cpu, "octeon");
1905 case PRID_IMP_CAVIUM_CN61XX:
1906 case PRID_IMP_CAVIUM_CN63XX:
1907 case PRID_IMP_CAVIUM_CN66XX:
1908 case PRID_IMP_CAVIUM_CN68XX:
1909 case PRID_IMP_CAVIUM_CNF71XX:
1910 c->cputype = CPU_CAVIUM_OCTEON2;
1911 __cpu_name[cpu] = "Cavium Octeon II";
1912 set_elf_platform(cpu, "octeon2");
1914 case PRID_IMP_CAVIUM_CN70XX:
1915 case PRID_IMP_CAVIUM_CN73XX:
1916 case PRID_IMP_CAVIUM_CNF75XX:
1917 case PRID_IMP_CAVIUM_CN78XX:
1918 c->cputype = CPU_CAVIUM_OCTEON3;
1919 __cpu_name[cpu] = "Cavium Octeon III";
1920 set_elf_platform(cpu, "octeon3");
1923 printk(KERN_INFO "Unknown Octeon chip!\n");
1924 c->cputype = CPU_UNKNOWN;
1929 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1931 switch (c->processor_id & PRID_IMP_MASK) {
1932 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1933 switch (c->processor_id & PRID_REV_MASK) {
1934 case PRID_REV_LOONGSON3A_R2_0:
1935 case PRID_REV_LOONGSON3A_R2_1:
1936 c->cputype = CPU_LOONGSON3;
1937 __cpu_name[cpu] = "ICT Loongson-3";
1938 set_elf_platform(cpu, "loongson3a");
1939 set_isa(c, MIPS_CPU_ISA_M64R2);
1941 case PRID_REV_LOONGSON3A_R3_0:
1942 case PRID_REV_LOONGSON3A_R3_1:
1943 c->cputype = CPU_LOONGSON3;
1944 __cpu_name[cpu] = "ICT Loongson-3";
1945 set_elf_platform(cpu, "loongson3a");
1946 set_isa(c, MIPS_CPU_ISA_M64R2);
1951 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1952 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1955 panic("Unknown Loongson Processor ID!");
1960 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1963 /* JZRISC does not implement the CP0 counter. */
1964 c->options &= ~MIPS_CPU_COUNTER;
1965 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1966 switch (c->processor_id & PRID_IMP_MASK) {
1967 case PRID_IMP_JZRISC:
1968 c->cputype = CPU_JZRISC;
1969 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1970 __cpu_name[cpu] = "Ingenic JZRISC";
1973 panic("Unknown Ingenic Processor ID!");
1978 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1982 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1983 c->cputype = CPU_ALCHEMY;
1984 __cpu_name[cpu] = "Au1300";
1985 /* following stuff is not for Alchemy */
1989 c->options = (MIPS_CPU_TLB |
1997 switch (c->processor_id & PRID_IMP_MASK) {
1998 case PRID_IMP_NETLOGIC_XLP2XX:
1999 case PRID_IMP_NETLOGIC_XLP9XX:
2000 case PRID_IMP_NETLOGIC_XLP5XX:
2001 c->cputype = CPU_XLP;
2002 __cpu_name[cpu] = "Broadcom XLPII";
2005 case PRID_IMP_NETLOGIC_XLP8XX:
2006 case PRID_IMP_NETLOGIC_XLP3XX:
2007 c->cputype = CPU_XLP;
2008 __cpu_name[cpu] = "Netlogic XLP";
2011 case PRID_IMP_NETLOGIC_XLR732:
2012 case PRID_IMP_NETLOGIC_XLR716:
2013 case PRID_IMP_NETLOGIC_XLR532:
2014 case PRID_IMP_NETLOGIC_XLR308:
2015 case PRID_IMP_NETLOGIC_XLR532C:
2016 case PRID_IMP_NETLOGIC_XLR516C:
2017 case PRID_IMP_NETLOGIC_XLR508C:
2018 case PRID_IMP_NETLOGIC_XLR308C:
2019 c->cputype = CPU_XLR;
2020 __cpu_name[cpu] = "Netlogic XLR";
2023 case PRID_IMP_NETLOGIC_XLS608:
2024 case PRID_IMP_NETLOGIC_XLS408:
2025 case PRID_IMP_NETLOGIC_XLS404:
2026 case PRID_IMP_NETLOGIC_XLS208:
2027 case PRID_IMP_NETLOGIC_XLS204:
2028 case PRID_IMP_NETLOGIC_XLS108:
2029 case PRID_IMP_NETLOGIC_XLS104:
2030 case PRID_IMP_NETLOGIC_XLS616B:
2031 case PRID_IMP_NETLOGIC_XLS608B:
2032 case PRID_IMP_NETLOGIC_XLS416B:
2033 case PRID_IMP_NETLOGIC_XLS412B:
2034 case PRID_IMP_NETLOGIC_XLS408B:
2035 case PRID_IMP_NETLOGIC_XLS404B:
2036 c->cputype = CPU_XLR;
2037 __cpu_name[cpu] = "Netlogic XLS";
2041 pr_info("Unknown Netlogic chip id [%02x]!\n",
2043 c->cputype = CPU_XLR;
2047 if (c->cputype == CPU_XLP) {
2048 set_isa(c, MIPS_CPU_ISA_M64R2);
2049 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2050 /* This will be updated again after all threads are woken up */
2051 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2053 set_isa(c, MIPS_CPU_ISA_M64R1);
2054 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2056 c->kscratch_mask = 0xf;
2060 /* For use by uaccess.h */
2062 EXPORT_SYMBOL(__ua_limit);
2065 const char *__cpu_name[NR_CPUS];
2066 const char *__elf_platform;
2068 void cpu_probe(void)
2070 struct cpuinfo_mips *c = ¤t_cpu_data;
2071 unsigned int cpu = smp_processor_id();
2074 * Set a default elf platform, cpu probe may later
2075 * overwrite it with a more precise value
2077 set_elf_platform(cpu, "mips");
2079 c->processor_id = PRID_IMP_UNKNOWN;
2080 c->fpu_id = FPIR_IMP_NONE;
2081 c->cputype = CPU_UNKNOWN;
2082 c->writecombine = _CACHE_UNCACHED;
2084 c->fpu_csr31 = FPU_CSR_RN;
2085 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2087 c->processor_id = read_c0_prid();
2088 switch (c->processor_id & PRID_COMP_MASK) {
2089 case PRID_COMP_LEGACY:
2090 cpu_probe_legacy(c, cpu);
2092 case PRID_COMP_MIPS:
2093 cpu_probe_mips(c, cpu);
2095 case PRID_COMP_ALCHEMY:
2096 cpu_probe_alchemy(c, cpu);
2098 case PRID_COMP_SIBYTE:
2099 cpu_probe_sibyte(c, cpu);
2101 case PRID_COMP_BROADCOM:
2102 cpu_probe_broadcom(c, cpu);
2104 case PRID_COMP_SANDCRAFT:
2105 cpu_probe_sandcraft(c, cpu);
2108 cpu_probe_nxp(c, cpu);
2110 case PRID_COMP_CAVIUM:
2111 cpu_probe_cavium(c, cpu);
2113 case PRID_COMP_LOONGSON:
2114 cpu_probe_loongson(c, cpu);
2116 case PRID_COMP_INGENIC_D0:
2117 case PRID_COMP_INGENIC_D1:
2118 case PRID_COMP_INGENIC_E1:
2119 cpu_probe_ingenic(c, cpu);
2121 case PRID_COMP_NETLOGIC:
2122 cpu_probe_netlogic(c, cpu);
2126 BUG_ON(!__cpu_name[cpu]);
2127 BUG_ON(c->cputype == CPU_UNKNOWN);
2130 * Platform code can force the cpu type to optimize code
2131 * generation. In that case be sure the cpu type is correctly
2132 * manually setup otherwise it could trigger some nasty bugs.
2134 BUG_ON(current_cpu_type() != c->cputype);
2137 /* Enable the RIXI exceptions */
2138 set_c0_pagegrain(PG_IEC);
2139 back_to_back_c0_hazard();
2140 /* Verify the IEC bit is set */
2141 if (read_c0_pagegrain() & PG_IEC)
2142 c->options |= MIPS_CPU_RIXIEX;
2145 if (mips_fpu_disabled)
2146 c->options &= ~MIPS_CPU_FPU;
2148 if (mips_dsp_disabled)
2149 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2151 if (mips_htw_disabled) {
2152 c->options &= ~MIPS_CPU_HTW;
2153 write_c0_pwctl(read_c0_pwctl() &
2154 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2157 if (c->options & MIPS_CPU_FPU)
2158 cpu_set_fpu_opts(c);
2160 cpu_set_nofpu_opts(c);
2162 if (cpu_has_bp_ghist)
2163 write_c0_r10k_diag(read_c0_r10k_diag() |
2166 if (cpu_has_mips_r2_r6) {
2167 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2168 /* R2 has Performance Counter Interrupt indicator */
2169 c->options |= MIPS_CPU_PCI;
2174 if (cpu_has_mips_r6)
2175 elf_hwcap |= HWCAP_MIPS_R6;
2178 c->msa_id = cpu_get_msa_id();
2179 WARN(c->msa_id & MSA_IR_WRPF,
2180 "Vector register partitioning unimplemented!");
2181 elf_hwcap |= HWCAP_MIPS_MSA;
2187 cpu_probe_vmbits(c);
2191 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2195 void cpu_report(void)
2197 struct cpuinfo_mips *c = ¤t_cpu_data;
2199 pr_info("CPU%d revision is: %08x (%s)\n",
2200 smp_processor_id(), c->processor_id, cpu_name_string());
2201 if (c->options & MIPS_CPU_FPU)
2202 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2204 pr_info("MSA revision is: %08x\n", c->msa_id);
2207 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2209 /* Ensure the core number fits in the field */
2210 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2211 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2213 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2214 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2217 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2219 /* Ensure the core number fits in the field */
2220 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2222 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2223 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2226 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2228 /* Ensure the VP(E) ID fits in the field */
2229 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2231 /* Ensure we're not using VP(E)s without support */
2232 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2233 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2235 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2236 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;