arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <linux/uaccess.h>
  34
  35 /* Hardware capabilities */
  36 unsigned int elf_hwcap __read_mostly;
  37 EXPORT_SYMBOL_GPL(elf_hwcap);
  38
  39 #ifdef CONFIG_MIPS_FP_SUPPORT
  40
  41 /*
  42  * Get the FPU Implementation/Revision.
  43  */
  44 static inline unsigned long cpu_get_fpu_id(void)
  45 {
  46         unsigned long tmp, fpu_id;
  47
  48         tmp = read_c0_status();
  49         __enable_fpu(FPU_AS_IS);
  50         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  51         write_c0_status(tmp);
  52         return fpu_id;
  53 }
  54
  55 /*
  56  * Check if the CPU has an external FPU.
  57  */
  58 static inline int __cpu_has_fpu(void)
  59 {
  60         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  61 }
  62
  63 /*
  64  * Determine the FCSR mask for FPU hardware.
  65  */
  66 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  67 {
  68         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  69
  70         fcsr = c->fpu_csr31;
  71         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  72
  73         sr = read_c0_status();
  74         __enable_fpu(FPU_AS_IS);
  75
  76         fcsr0 = fcsr & mask;
  77         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  78         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  79
  80         fcsr1 = fcsr | ~mask;
  81         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  82         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  83
  84         write_32bit_cp1_register(CP1_STATUS, fcsr);
  85
  86         write_c0_status(sr);
  87
  88         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  89 }
  90
  91 /*
  92  * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
  93  * supported by FPU hardware.
  94  */
  95 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
  96 {
  97         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
  98                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
  99                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 100                 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
 101
 102                 sr = read_c0_status();
 103                 __enable_fpu(FPU_AS_IS);
 104
 105                 fir = read_32bit_cp1_register(CP1_REVISION);
 106                 if (fir & MIPS_FPIR_HAS2008) {
 107                         fcsr = read_32bit_cp1_register(CP1_STATUS);
 108
 109                         fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 110                         write_32bit_cp1_register(CP1_STATUS, fcsr0);
 111                         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
 112
 113                         fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 114                         write_32bit_cp1_register(CP1_STATUS, fcsr1);
 115                         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
 116
 117                         write_32bit_cp1_register(CP1_STATUS, fcsr);
 118
 119                         if (!(fcsr0 & FPU_CSR_NAN2008))
 120                                 c->options |= MIPS_CPU_NAN_LEGACY;
 121                         if (fcsr1 & FPU_CSR_NAN2008)
 122                                 c->options |= MIPS_CPU_NAN_2008;
 123
 124                         if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
 125                                 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
 126                         else
 127                                 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
 128
 129                         if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
 130                                 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
 131                         else
 132                                 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
 133                 } else {
 134                         c->options |= MIPS_CPU_NAN_LEGACY;
 135                 }
 136
 137                 write_c0_status(sr);
 138         } else {
 139                 c->options |= MIPS_CPU_NAN_LEGACY;
 140         }
 141 }
 142
 143 /*
 144  * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
 145  * ABS.fmt/NEG.fmt execution mode.
 146  */
 147 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
 148
 149 /*
 150  * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
 151  * to support by the FPU emulator according to the IEEE 754 conformance
 152  * mode selected.  Note that "relaxed" straps the emulator so that it
 153  * allows 2008-NaN binaries even for legacy processors.
 154  */
 155 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
 156 {
 157         c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
 158         c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 159         c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 160
 161         switch (ieee754) {
 162         case STRICT:
 163                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 164                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 165                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 166                         c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 167                 } else {
 168                         c->options |= MIPS_CPU_NAN_LEGACY;
 169                         c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 170                 }
 171                 break;
 172         case LEGACY:
 173                 c->options |= MIPS_CPU_NAN_LEGACY;
 174                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 175                 break;
 176         case STD2008:
 177                 c->options |= MIPS_CPU_NAN_2008;
 178                 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 179                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 180                 break;
 181         case RELAXED:
 182                 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 183                 break;
 184         }
 185 }
 186
 187 /*
 188  * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
 189  * according to the "ieee754=" parameter.
 190  */
 191 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
 192 {
 193         switch (ieee754) {
 194         case STRICT:
 195                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 196                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 197                 break;
 198         case LEGACY:
 199                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 200                 mips_use_nan_2008 = !cpu_has_nan_legacy;
 201                 break;
 202         case STD2008:
 203                 mips_use_nan_legacy = !cpu_has_nan_2008;
 204                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 205                 break;
 206         case RELAXED:
 207                 mips_use_nan_legacy = true;
 208                 mips_use_nan_2008 = true;
 209                 break;
 210         }
 211 }
 212
 213 /*
 214  * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
 215  * settings:
 216  *
 217  * strict:  accept binaries that request a NaN encoding supported by the FPU
 218  * legacy:  only accept legacy-NaN binaries
 219  * 2008:    only accept 2008-NaN binaries
 220  * relaxed: accept any binaries regardless of whether supported by the FPU
 221  */
 222 static int __init ieee754_setup(char *s)
 223 {
 224         if (!s)
 225                 return -1;
 226         else if (!strcmp(s, "strict"))
 227                 ieee754 = STRICT;
 228         else if (!strcmp(s, "legacy"))
 229                 ieee754 = LEGACY;
 230         else if (!strcmp(s, "2008"))
 231                 ieee754 = STD2008;
 232         else if (!strcmp(s, "relaxed"))
 233                 ieee754 = RELAXED;
 234         else
 235                 return -1;
 236
 237         if (!(boot_cpu_data.options & MIPS_CPU_FPU))
 238                 cpu_set_nofpu_2008(&boot_cpu_data);
 239         cpu_set_nan_2008(&boot_cpu_data);
 240
 241         return 0;
 242 }
 243
 244 early_param("ieee754", ieee754_setup);
 245
 246 /*
 247  * Set the FIR feature flags for the FPU emulator.
 248  */
 249 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 250 {
 251         u32 value;
 252
 253         value = 0;
 254         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 255                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 256                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 257                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 258         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 259                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 260                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 261         if (c->options & MIPS_CPU_NAN_2008)
 262                 value |= MIPS_FPIR_HAS2008;
 263         c->fpu_id = value;
 264 }
 265
 266 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 267 static unsigned int mips_nofpu_msk31;
 268
 269 /*
 270  * Set options for FPU hardware.
 271  */
 272 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 273 {
 274         c->fpu_id = cpu_get_fpu_id();
 275         mips_nofpu_msk31 = c->fpu_msk31;
 276
 277         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 278                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 279                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 280                 if (c->fpu_id & MIPS_FPIR_3D)
 281                         c->ases |= MIPS_ASE_MIPS3D;
 282                 if (c->fpu_id & MIPS_FPIR_UFRP)
 283                         c->options |= MIPS_CPU_UFR;
 284                 if (c->fpu_id & MIPS_FPIR_FREP)
 285                         c->options |= MIPS_CPU_FRE;
 286         }
 287
 288         cpu_set_fpu_fcsr_mask(c);
 289         cpu_set_fpu_2008(c);
 290         cpu_set_nan_2008(c);
 291 }
 292
 293 /*
 294  * Set options for the FPU emulator.
 295  */
 296 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 297 {
 298         c->options &= ~MIPS_CPU_FPU;
 299         c->fpu_msk31 = mips_nofpu_msk31;
 300
 301         cpu_set_nofpu_2008(c);
 302         cpu_set_nan_2008(c);
 303         cpu_set_nofpu_id(c);
 304 }
 305
 306 static int mips_fpu_disabled;
 307
 308 static int __init fpu_disable(char *s)
 309 {
 310         cpu_set_nofpu_opts(&boot_cpu_data);
 311         mips_fpu_disabled = 1;
 312
 313         return 1;
 314 }
 315
 316 __setup("nofpu", fpu_disable);
 317
 318 #else /* !CONFIG_MIPS_FP_SUPPORT */
 319
 320 #define mips_fpu_disabled 1
 321
 322 static inline unsigned long cpu_get_fpu_id(void)
 323 {
 324         return FPIR_IMP_NONE;
 325 }
 326
 327 static inline int __cpu_has_fpu(void)
 328 {
 329         return 0;
 330 }
 331
 332 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 333 {
 334         /* no-op */
 335 }
 336
 337 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 338 {
 339         /* no-op */
 340 }
 341
 342 #endif /* CONFIG_MIPS_FP_SUPPORT */
 343
 344 static inline unsigned long cpu_get_msa_id(void)
 345 {
 346         unsigned long status, msa_id;
 347
 348         status = read_c0_status();
 349         __enable_fpu(FPU_64BIT);
 350         enable_msa();
 351         msa_id = read_msa_ir();
 352         disable_msa();
 353         write_c0_status(status);
 354         return msa_id;
 355 }
 356
 357 static int mips_dsp_disabled;
 358
 359 static int __init dsp_disable(char *s)
 360 {
 361         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 362         mips_dsp_disabled = 1;
 363
 364         return 1;
 365 }
 366
 367 __setup("nodsp", dsp_disable);
 368
 369 static int mips_htw_disabled;
 370
 371 static int __init htw_disable(char *s)
 372 {
 373         mips_htw_disabled = 1;
 374         cpu_data[0].options &= ~MIPS_CPU_HTW;
 375         write_c0_pwctl(read_c0_pwctl() &
 376                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 377
 378         return 1;
 379 }
 380
 381 __setup("nohtw", htw_disable);
 382
 383 static int mips_ftlb_disabled;
 384 static int mips_has_ftlb_configured;
 385
 386 enum ftlb_flags {
 387         FTLB_EN         = 1 << 0,
 388         FTLB_SET_PROB   = 1 << 1,
 389 };
 390
 391 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
 392
 393 static int __init ftlb_disable(char *s)
 394 {
 395         unsigned int config4, mmuextdef;
 396
 397         /*
 398          * If the core hasn't done any FTLB configuration, there is nothing
 399          * for us to do here.
 400          */
 401         if (!mips_has_ftlb_configured)
 402                 return 1;
 403
 404         /* Disable it in the boot cpu */
 405         if (set_ftlb_enable(&cpu_data[0], 0)) {
 406                 pr_warn("Can't turn FTLB off\n");
 407                 return 1;
 408         }
 409
 410         config4 = read_c0_config4();
 411
 412         /* Check that FTLB has been disabled */
 413         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 414         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 415         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 416                 /* This should never happen */
 417                 pr_warn("FTLB could not be disabled!\n");
 418                 return 1;
 419         }
 420
 421         mips_ftlb_disabled = 1;
 422         mips_has_ftlb_configured = 0;
 423
 424         /*
 425          * noftlb is mainly used for debug purposes so print
 426          * an informative message instead of using pr_debug()
 427          */
 428         pr_info("FTLB has been disabled\n");
 429
 430         /*
 431          * Some of these bits are duplicated in the decode_config4.
 432          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 433          * once FTLB has been disabled so undo what decode_config4 did.
 434          */
 435         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 436                                cpu_data[0].tlbsizeftlbsets;
 437         cpu_data[0].tlbsizeftlbsets = 0;
 438         cpu_data[0].tlbsizeftlbways = 0;
 439
 440         return 1;
 441 }
 442
 443 __setup("noftlb", ftlb_disable);
 444
 445 /*
 446  * Check if the CPU has per tc perf counters
 447  */
 448 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
 449 {
 450         if (read_c0_config7() & MTI_CONF7_PTC)
 451                 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
 452 }
 453
 454 static inline void check_errata(void)
 455 {
 456         struct cpuinfo_mips *c = &current_cpu_data;
 457
 458         switch (current_cpu_type()) {
 459         case CPU_34K:
 460                 /*
 461                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 462                  * This code only handles VPE0, any SMP/RTOS code
 463                  * making use of VPE1 will be responsable for that VPE.
 464                  */
 465                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 466                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 467                 break;
 468         default:
 469                 break;
 470         }
 471 }
 472
 473 void __init check_bugs32(void)
 474 {
 475         check_errata();
 476 }
 477
 478 /*
 479  * Probe whether cpu has config register by trying to play with
 480  * alternate cache bit and see whether it matters.
 481  * It's used by cpu_probe to distinguish between R3000A and R3081.
 482  */
 483 static inline int cpu_has_confreg(void)
 484 {
 485 #ifdef CONFIG_CPU_R3000
 486         extern unsigned long r3k_cache_size(unsigned long);
 487         unsigned long size1, size2;
 488         unsigned long cfg = read_c0_conf();
 489
 490         size1 = r3k_cache_size(ST0_ISC);
 491         write_c0_conf(cfg ^ R30XX_CONF_AC);
 492         size2 = r3k_cache_size(ST0_ISC);
 493         write_c0_conf(cfg);
 494         return size1 != size2;
 495 #else
 496         return 0;
 497 #endif
 498 }
 499
 500 static inline void set_elf_platform(int cpu, const char *plat)
 501 {
 502         if (cpu == 0)
 503                 __elf_platform = plat;
 504 }
 505
 506 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 507 {
 508 #ifdef __NEED_VMBITS_PROBE
 509         write_c0_entryhi(0x3fffffffffffe000ULL);
 510         back_to_back_c0_hazard();
 511         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 512 #endif
 513 }
 514
 515 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 516 {
 517         switch (isa) {
 518         case MIPS_CPU_ISA_M64R2:
 519                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 520                 /* fall through */
 521         case MIPS_CPU_ISA_M64R1:
 522                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 523                 /* fall through */
 524         case MIPS_CPU_ISA_V:
 525                 c->isa_level |= MIPS_CPU_ISA_V;
 526                 /* fall through */
 527         case MIPS_CPU_ISA_IV:
 528                 c->isa_level |= MIPS_CPU_ISA_IV;
 529                 /* fall through */
 530         case MIPS_CPU_ISA_III:
 531                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 532                 break;
 533
 534         /* R6 incompatible with everything else */
 535         case MIPS_CPU_ISA_M64R6:
 536                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 537                 /* fall through */
 538         case MIPS_CPU_ISA_M32R6:
 539                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 540                 /* Break here so we don't add incompatible ISAs */
 541                 break;
 542         case MIPS_CPU_ISA_M32R2:
 543                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 544                 /* fall through */
 545         case MIPS_CPU_ISA_M32R1:
 546                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 547                 /* fall through */
 548         case MIPS_CPU_ISA_II:
 549                 c->isa_level |= MIPS_CPU_ISA_II;
 550                 break;
 551         }
 552 }
 553
 554 static char unknown_isa[] = KERN_ERR \
 555         "Unsupported ISA type, c0.config0: %d.";
 556
 557 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 558 {
 559
 560         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 561
 562         /*
 563          * 0 = All TLBWR instructions go to FTLB
 564          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 565          * FTLB and 1 goes to the VTLB.
 566          * 2 = 7:1: As above with 7:1 ratio.
 567          * 3 = 3:1: As above with 3:1 ratio.
 568          *
 569          * Use the linear midpoint as the probability threshold.
 570          */
 571         if (probability >= 12)
 572                 return 1;
 573         else if (probability >= 6)
 574                 return 2;
 575         else
 576                 /*
 577                  * So FTLB is less than 4 times bigger than VTLB.
 578                  * A 3:1 ratio can still be useful though.
 579                  */
 580                 return 3;
 581 }
 582
 583 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 584 {
 585         unsigned int config;
 586
 587         /* It's implementation dependent how the FTLB can be enabled */
 588         switch (c->cputype) {
 589         case CPU_PROAPTIV:
 590         case CPU_P5600:
 591         case CPU_P6600:
 592                 /* proAptiv & related cores use Config6 to enable the FTLB */
 593                 config = read_c0_config6();
 594
 595                 if (flags & FTLB_EN)
 596                         config |= MIPS_CONF6_FTLBEN;
 597                 else
 598                         config &= ~MIPS_CONF6_FTLBEN;
 599
 600                 if (flags & FTLB_SET_PROB) {
 601                         config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 602                         config |= calculate_ftlb_probability(c)
 603                                   << MIPS_CONF6_FTLBP_SHIFT;
 604                 }
 605
 606                 write_c0_config6(config);
 607                 back_to_back_c0_hazard();
 608                 break;
 609         case CPU_I6400:
 610         case CPU_I6500:
 611                 /* There's no way to disable the FTLB */
 612                 if (!(flags & FTLB_EN))
 613                         return 1;
 614                 return 0;
 615         case CPU_LOONGSON3:
 616                 /* Flush ITLB, DTLB, VTLB and FTLB */
 617                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
 618                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
 619                 /* Loongson-3 cores use Config6 to enable the FTLB */
 620                 config = read_c0_config6();
 621                 if (flags & FTLB_EN)
 622                         /* Enable FTLB */
 623                         write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
 624                 else
 625                         /* Disable FTLB */
 626                         write_c0_config6(config | MIPS_CONF6_FTLBDIS);
 627                 break;
 628         default:
 629                 return 1;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 636 {
 637         unsigned int config0;
 638         int isa, mt;
 639
 640         config0 = read_c0_config();
 641
 642         /*
 643          * Look for Standard TLB or Dual VTLB and FTLB
 644          */
 645         mt = config0 & MIPS_CONF_MT;
 646         if (mt == MIPS_CONF_MT_TLB)
 647                 c->options |= MIPS_CPU_TLB;
 648         else if (mt == MIPS_CONF_MT_FTLB)
 649                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 650
 651         isa = (config0 & MIPS_CONF_AT) >> 13;
 652         switch (isa) {
 653         case 0:
 654                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 655                 case 0:
 656                         set_isa(c, MIPS_CPU_ISA_M32R1);
 657                         break;
 658                 case 1:
 659                         set_isa(c, MIPS_CPU_ISA_M32R2);
 660                         break;
 661                 case 2:
 662                         set_isa(c, MIPS_CPU_ISA_M32R6);
 663                         break;
 664                 default:
 665                         goto unknown;
 666                 }
 667                 break;
 668         case 2:
 669                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 670                 case 0:
 671                         set_isa(c, MIPS_CPU_ISA_M64R1);
 672                         break;
 673                 case 1:
 674                         set_isa(c, MIPS_CPU_ISA_M64R2);
 675                         break;
 676                 case 2:
 677                         set_isa(c, MIPS_CPU_ISA_M64R6);
 678                         break;
 679                 default:
 680                         goto unknown;
 681                 }
 682                 break;
 683         default:
 684                 goto unknown;
 685         }
 686
 687         return config0 & MIPS_CONF_M;
 688
 689 unknown:
 690         panic(unknown_isa, config0);
 691 }
 692
 693 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 694 {
 695         unsigned int config1;
 696
 697         config1 = read_c0_config1();
 698
 699         if (config1 & MIPS_CONF1_MD)
 700                 c->ases |= MIPS_ASE_MDMX;
 701         if (config1 & MIPS_CONF1_PC)
 702                 c->options |= MIPS_CPU_PERF;
 703         if (config1 & MIPS_CONF1_WR)
 704                 c->options |= MIPS_CPU_WATCH;
 705         if (config1 & MIPS_CONF1_CA)
 706                 c->ases |= MIPS_ASE_MIPS16;
 707         if (config1 & MIPS_CONF1_EP)
 708                 c->options |= MIPS_CPU_EJTAG;
 709         if (config1 & MIPS_CONF1_FP) {
 710                 c->options |= MIPS_CPU_FPU;
 711                 c->options |= MIPS_CPU_32FPR;
 712         }
 713         if (cpu_has_tlb) {
 714                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 715                 c->tlbsizevtlb = c->tlbsize;
 716                 c->tlbsizeftlbsets = 0;
 717         }
 718
 719         return config1 & MIPS_CONF_M;
 720 }
 721
 722 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 723 {
 724         unsigned int config2;
 725
 726         config2 = read_c0_config2();
 727
 728         if (config2 & MIPS_CONF2_SL)
 729                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 730
 731         return config2 & MIPS_CONF_M;
 732 }
 733
 734 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 735 {
 736         unsigned int config3;
 737
 738         config3 = read_c0_config3();
 739
 740         if (config3 & MIPS_CONF3_SM) {
 741                 c->ases |= MIPS_ASE_SMARTMIPS;
 742                 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
 743         }
 744         if (config3 & MIPS_CONF3_RXI)
 745                 c->options |= MIPS_CPU_RIXI;
 746         if (config3 & MIPS_CONF3_CTXTC)
 747                 c->options |= MIPS_CPU_CTXTC;
 748         if (config3 & MIPS_CONF3_DSP)
 749                 c->ases |= MIPS_ASE_DSP;
 750         if (config3 & MIPS_CONF3_DSP2P) {
 751                 c->ases |= MIPS_ASE_DSP2P;
 752                 if (cpu_has_mips_r6)
 753                         c->ases |= MIPS_ASE_DSP3;
 754         }
 755         if (config3 & MIPS_CONF3_VINT)
 756                 c->options |= MIPS_CPU_VINT;
 757         if (config3 & MIPS_CONF3_VEIC)
 758                 c->options |= MIPS_CPU_VEIC;
 759         if (config3 & MIPS_CONF3_LPA)
 760                 c->options |= MIPS_CPU_LPA;
 761         if (config3 & MIPS_CONF3_MT)
 762                 c->ases |= MIPS_ASE_MIPSMT;
 763         if (config3 & MIPS_CONF3_ULRI)
 764                 c->options |= MIPS_CPU_ULRI;
 765         if (config3 & MIPS_CONF3_ISA)
 766                 c->options |= MIPS_CPU_MICROMIPS;
 767         if (config3 & MIPS_CONF3_VZ)
 768                 c->ases |= MIPS_ASE_VZ;
 769         if (config3 & MIPS_CONF3_SC)
 770                 c->options |= MIPS_CPU_SEGMENTS;
 771         if (config3 & MIPS_CONF3_BI)
 772                 c->options |= MIPS_CPU_BADINSTR;
 773         if (config3 & MIPS_CONF3_BP)
 774                 c->options |= MIPS_CPU_BADINSTRP;
 775         if (config3 & MIPS_CONF3_MSA)
 776                 c->ases |= MIPS_ASE_MSA;
 777         if (config3 & MIPS_CONF3_PW) {
 778                 c->htw_seq = 0;
 779                 c->options |= MIPS_CPU_HTW;
 780         }
 781         if (config3 & MIPS_CONF3_CDMM)
 782                 c->options |= MIPS_CPU_CDMM;
 783         if (config3 & MIPS_CONF3_SP)
 784                 c->options |= MIPS_CPU_SP;
 785
 786         return config3 & MIPS_CONF_M;
 787 }
 788
 789 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 790 {
 791         unsigned int config4;
 792         unsigned int newcf4;
 793         unsigned int mmuextdef;
 794         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 795         unsigned long asid_mask;
 796
 797         config4 = read_c0_config4();
 798
 799         if (cpu_has_tlb) {
 800                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 801                         c->options |= MIPS_CPU_TLBINV;
 802
 803                 /*
 804                  * R6 has dropped the MMUExtDef field from config4.
 805                  * On R6 the fields always describe the FTLB, and only if it is
 806                  * present according to Config.MT.
 807                  */
 808                 if (!cpu_has_mips_r6)
 809                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 810                 else if (cpu_has_ftlb)
 811                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 812                 else
 813                         mmuextdef = 0;
 814
 815                 switch (mmuextdef) {
 816                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 817                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 818                         c->tlbsizevtlb = c->tlbsize;
 819                         break;
 820                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 821                         c->tlbsizevtlb +=
 822                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 823                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 824                         c->tlbsize = c->tlbsizevtlb;
 825                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 826                         /* fall through */
 827                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 828                         if (mips_ftlb_disabled)
 829                                 break;
 830                         newcf4 = (config4 & ~ftlb_page) |
 831                                 (page_size_ftlb(mmuextdef) <<
 832                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 833                         write_c0_config4(newcf4);
 834                         back_to_back_c0_hazard();
 835                         config4 = read_c0_config4();
 836                         if (config4 != newcf4) {
 837                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 838                                        PAGE_SIZE, config4);
 839                                 /* Switch FTLB off */
 840                                 set_ftlb_enable(c, 0);
 841                                 mips_ftlb_disabled = 1;
 842                                 break;
 843                         }
 844                         c->tlbsizeftlbsets = 1 <<
 845                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 846                                  MIPS_CONF4_FTLBSETS_SHIFT);
 847                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 848                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 849                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 850                         mips_has_ftlb_configured = 1;
 851                         break;
 852                 }
 853         }
 854
 855         c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 856                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 857
 858         asid_mask = MIPS_ENTRYHI_ASID;
 859         if (config4 & MIPS_CONF4_AE)
 860                 asid_mask |= MIPS_ENTRYHI_ASIDX;
 861         set_cpu_asid_mask(c, asid_mask);
 862
 863         /*
 864          * Warn if the computed ASID mask doesn't match the mask the kernel
 865          * is built for. This may indicate either a serious problem or an
 866          * easy optimisation opportunity, but either way should be addressed.
 867          */
 868         WARN_ON(asid_mask != cpu_asid_mask(c));
 869
 870         return config4 & MIPS_CONF_M;
 871 }
 872
 873 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 874 {
 875         unsigned int config5, max_mmid_width;
 876         unsigned long asid_mask;
 877
 878         config5 = read_c0_config5();
 879         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 880
 881         if (cpu_has_mips_r6) {
 882                 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
 883                         config5 |= MIPS_CONF5_MI;
 884                 else
 885                         config5 &= ~MIPS_CONF5_MI;
 886         }
 887
 888         write_c0_config5(config5);
 889
 890         if (config5 & MIPS_CONF5_EVA)
 891                 c->options |= MIPS_CPU_EVA;
 892         if (config5 & MIPS_CONF5_MRP)
 893                 c->options |= MIPS_CPU_MAAR;
 894         if (config5 & MIPS_CONF5_LLB)
 895                 c->options |= MIPS_CPU_RW_LLB;
 896         if (config5 & MIPS_CONF5_MVH)
 897                 c->options |= MIPS_CPU_MVH;
 898         if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 899                 c->options |= MIPS_CPU_VP;
 900         if (config5 & MIPS_CONF5_CA2)
 901                 c->ases |= MIPS_ASE_MIPS16E2;
 902
 903         if (config5 & MIPS_CONF5_CRCP)
 904                 elf_hwcap |= HWCAP_MIPS_CRC32;
 905
 906         if (cpu_has_mips_r6) {
 907                 /* Ensure the write to config5 above takes effect */
 908                 back_to_back_c0_hazard();
 909
 910                 /* Check whether we successfully enabled MMID support */
 911                 config5 = read_c0_config5();
 912                 if (config5 & MIPS_CONF5_MI)
 913                         c->options |= MIPS_CPU_MMID;
 914
 915                 /*
 916                  * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
 917                  * for the CPU we're running on, or if CPUs in an SMP system
 918                  * have inconsistent MMID support.
 919                  */
 920                 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
 921
 922                 if (cpu_has_mmid) {
 923                         write_c0_memorymapid(~0ul);
 924                         back_to_back_c0_hazard();
 925                         asid_mask = read_c0_memorymapid();
 926
 927                         /*
 928                          * We maintain a bitmap to track MMID allocation, and
 929                          * need a sensible upper bound on the size of that
 930                          * bitmap. The initial CPU with MMID support (I6500)
 931                          * supports 16 bit MMIDs, which gives us an 8KiB
 932                          * bitmap. The architecture recommends that hardware
 933                          * support 32 bit MMIDs, which would give us a 512MiB
 934                          * bitmap - that's too big in most cases.
 935                          *
 936                          * Cap MMID width at 16 bits for now & we can revisit
 937                          * this if & when hardware supports anything wider.
 938                          */
 939                         max_mmid_width = 16;
 940                         if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
 941                                 pr_info("Capping MMID width at %d bits",
 942                                         max_mmid_width);
 943                                 asid_mask = GENMASK(max_mmid_width - 1, 0);
 944                         }
 945
 946                         set_cpu_asid_mask(c, asid_mask);
 947                 }
 948         }
 949
 950         return config5 & MIPS_CONF_M;
 951 }
 952
 953 static void decode_configs(struct cpuinfo_mips *c)
 954 {
 955         int ok;
 956
 957         /* MIPS32 or MIPS64 compliant CPU.  */
 958         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 959                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 960
 961         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 962
 963         /* Enable FTLB if present and not disabled */
 964         set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
 965
 966         ok = decode_config0(c);                 /* Read Config registers.  */
 967         BUG_ON(!ok);                            /* Arch spec violation!  */
 968         if (ok)
 969                 ok = decode_config1(c);
 970         if (ok)
 971                 ok = decode_config2(c);
 972         if (ok)
 973                 ok = decode_config3(c);
 974         if (ok)
 975                 ok = decode_config4(c);
 976         if (ok)
 977                 ok = decode_config5(c);
 978
 979         /* Probe the EBase.WG bit */
 980         if (cpu_has_mips_r2_r6) {
 981                 u64 ebase;
 982                 unsigned int status;
 983
 984                 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
 985                 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
 986                                          : (s32)read_c0_ebase();
 987                 if (ebase & MIPS_EBASE_WG) {
 988                         /* WG bit already set, we can avoid the clumsy probe */
 989                         c->options |= MIPS_CPU_EBASE_WG;
 990                 } else {
 991                         /* Its UNDEFINED to change EBase while BEV=0 */
 992                         status = read_c0_status();
 993                         write_c0_status(status | ST0_BEV);
 994                         irq_enable_hazard();
 995                         /*
 996                          * On pre-r6 cores, this may well clobber the upper bits
 997                          * of EBase. This is hard to avoid without potentially
 998                          * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
 999                          */
1000                         if (cpu_has_mips64r6)
1001                                 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1002                         else
1003                                 write_c0_ebase(ebase | MIPS_EBASE_WG);
1004                         back_to_back_c0_hazard();
1005                         /* Restore BEV */
1006                         write_c0_status(status);
1007                         if (read_c0_ebase() & MIPS_EBASE_WG) {
1008                                 c->options |= MIPS_CPU_EBASE_WG;
1009                                 write_c0_ebase(ebase);
1010                         }
1011                 }
1012         }
1013
1014         /* configure the FTLB write probability */
1015         set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1016
1017         mips_probe_watch_registers(c);
1018
1019 #ifndef CONFIG_MIPS_CPS
1020         if (cpu_has_mips_r2_r6) {
1021                 unsigned int core;
1022
1023                 core = get_ebase_cpunum();
1024                 if (cpu_has_mipsmt)
1025                         core >>= fls(core_nvpes()) - 1;
1026                 cpu_set_core(c, core);
1027         }
1028 #endif
1029 }
1030
1031 /*
1032  * Probe for certain guest capabilities by writing config bits and reading back.
1033  * Finally write back the original value.
1034  */
1035 #define probe_gc0_config(name, maxconf, bits)                           \
1036 do {                                                                    \
1037         unsigned int tmp;                                               \
1038         tmp = read_gc0_##name();                                        \
1039         write_gc0_##name(tmp | (bits));                                 \
1040         back_to_back_c0_hazard();                                       \
1041         maxconf = read_gc0_##name();                                    \
1042         write_gc0_##name(tmp);                                          \
1043 } while (0)
1044
1045 /*
1046  * Probe for dynamic guest capabilities by changing certain config bits and
1047  * reading back to see if they change. Finally write back the original value.
1048  */
1049 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits)              \
1050 do {                                                                    \
1051         maxconf = read_gc0_##name();                                    \
1052         write_gc0_##name(maxconf ^ (bits));                             \
1053         back_to_back_c0_hazard();                                       \
1054         dynconf = maxconf ^ read_gc0_##name();                          \
1055         write_gc0_##name(maxconf);                                      \
1056         maxconf |= dynconf;                                             \
1057 } while (0)
1058
1059 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1060 {
1061         unsigned int config0;
1062
1063         probe_gc0_config(config, config0, MIPS_CONF_M);
1064
1065         if (config0 & MIPS_CONF_M)
1066                 c->guest.conf |= BIT(1);
1067         return config0 & MIPS_CONF_M;
1068 }
1069
1070 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1071 {
1072         unsigned int config1, config1_dyn;
1073
1074         probe_gc0_config_dyn(config1, config1, config1_dyn,
1075                              MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1076                              MIPS_CONF1_FP);
1077
1078         if (config1 & MIPS_CONF1_FP)
1079                 c->guest.options |= MIPS_CPU_FPU;
1080         if (config1_dyn & MIPS_CONF1_FP)
1081                 c->guest.options_dyn |= MIPS_CPU_FPU;
1082
1083         if (config1 & MIPS_CONF1_WR)
1084                 c->guest.options |= MIPS_CPU_WATCH;
1085         if (config1_dyn & MIPS_CONF1_WR)
1086                 c->guest.options_dyn |= MIPS_CPU_WATCH;
1087
1088         if (config1 & MIPS_CONF1_PC)
1089                 c->guest.options |= MIPS_CPU_PERF;
1090         if (config1_dyn & MIPS_CONF1_PC)
1091                 c->guest.options_dyn |= MIPS_CPU_PERF;
1092
1093         if (config1 & MIPS_CONF_M)
1094                 c->guest.conf |= BIT(2);
1095         return config1 & MIPS_CONF_M;
1096 }
1097
1098 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1099 {
1100         unsigned int config2;
1101
1102         probe_gc0_config(config2, config2, MIPS_CONF_M);
1103
1104         if (config2 & MIPS_CONF_M)
1105                 c->guest.conf |= BIT(3);
1106         return config2 & MIPS_CONF_M;
1107 }
1108
1109 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1110 {
1111         unsigned int config3, config3_dyn;
1112
1113         probe_gc0_config_dyn(config3, config3, config3_dyn,
1114                              MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1115                              MIPS_CONF3_CTXTC);
1116
1117         if (config3 & MIPS_CONF3_CTXTC)
1118                 c->guest.options |= MIPS_CPU_CTXTC;
1119         if (config3_dyn & MIPS_CONF3_CTXTC)
1120                 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1121
1122         if (config3 & MIPS_CONF3_PW)
1123                 c->guest.options |= MIPS_CPU_HTW;
1124
1125         if (config3 & MIPS_CONF3_ULRI)
1126                 c->guest.options |= MIPS_CPU_ULRI;
1127
1128         if (config3 & MIPS_CONF3_SC)
1129                 c->guest.options |= MIPS_CPU_SEGMENTS;
1130
1131         if (config3 & MIPS_CONF3_BI)
1132                 c->guest.options |= MIPS_CPU_BADINSTR;
1133         if (config3 & MIPS_CONF3_BP)
1134                 c->guest.options |= MIPS_CPU_BADINSTRP;
1135
1136         if (config3 & MIPS_CONF3_MSA)
1137                 c->guest.ases |= MIPS_ASE_MSA;
1138         if (config3_dyn & MIPS_CONF3_MSA)
1139                 c->guest.ases_dyn |= MIPS_ASE_MSA;
1140
1141         if (config3 & MIPS_CONF_M)
1142                 c->guest.conf |= BIT(4);
1143         return config3 & MIPS_CONF_M;
1144 }
1145
1146 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1147 {
1148         unsigned int config4;
1149
1150         probe_gc0_config(config4, config4,
1151                          MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1152
1153         c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1154                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
1155
1156         if (config4 & MIPS_CONF_M)
1157                 c->guest.conf |= BIT(5);
1158         return config4 & MIPS_CONF_M;
1159 }
1160
1161 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1162 {
1163         unsigned int config5, config5_dyn;
1164
1165         probe_gc0_config_dyn(config5, config5, config5_dyn,
1166                          MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1167
1168         if (config5 & MIPS_CONF5_MRP)
1169                 c->guest.options |= MIPS_CPU_MAAR;
1170         if (config5_dyn & MIPS_CONF5_MRP)
1171                 c->guest.options_dyn |= MIPS_CPU_MAAR;
1172
1173         if (config5 & MIPS_CONF5_LLB)
1174                 c->guest.options |= MIPS_CPU_RW_LLB;
1175
1176         if (config5 & MIPS_CONF5_MVH)
1177                 c->guest.options |= MIPS_CPU_MVH;
1178
1179         if (config5 & MIPS_CONF_M)
1180                 c->guest.conf |= BIT(6);
1181         return config5 & MIPS_CONF_M;
1182 }
1183
1184 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1185 {
1186         unsigned int ok;
1187
1188         ok = decode_guest_config0(c);
1189         if (ok)
1190                 ok = decode_guest_config1(c);
1191         if (ok)
1192                 ok = decode_guest_config2(c);
1193         if (ok)
1194                 ok = decode_guest_config3(c);
1195         if (ok)
1196                 ok = decode_guest_config4(c);
1197         if (ok)
1198                 decode_guest_config5(c);
1199 }
1200
1201 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1202 {
1203         unsigned int guestctl0, temp;
1204
1205         guestctl0 = read_c0_guestctl0();
1206
1207         if (guestctl0 & MIPS_GCTL0_G0E)
1208                 c->options |= MIPS_CPU_GUESTCTL0EXT;
1209         if (guestctl0 & MIPS_GCTL0_G1)
1210                 c->options |= MIPS_CPU_GUESTCTL1;
1211         if (guestctl0 & MIPS_GCTL0_G2)
1212                 c->options |= MIPS_CPU_GUESTCTL2;
1213         if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1214                 c->options |= MIPS_CPU_GUESTID;
1215
1216                 /*
1217                  * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1218                  * first, otherwise all data accesses will be fully virtualised
1219                  * as if they were performed by guest mode.
1220                  */
1221                 write_c0_guestctl1(0);
1222                 tlbw_use_hazard();
1223
1224                 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1225                 back_to_back_c0_hazard();
1226                 temp = read_c0_guestctl0();
1227
1228                 if (temp & MIPS_GCTL0_DRG) {
1229                         write_c0_guestctl0(guestctl0);
1230                         c->options |= MIPS_CPU_DRG;
1231                 }
1232         }
1233 }
1234
1235 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1236 {
1237         if (cpu_has_guestid) {
1238                 /* determine the number of bits of GuestID available */
1239                 write_c0_guestctl1(MIPS_GCTL1_ID);
1240                 back_to_back_c0_hazard();
1241                 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1242                                                 >> MIPS_GCTL1_ID_SHIFT;
1243                 write_c0_guestctl1(0);
1244         }
1245 }
1246
1247 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1248 {
1249         /* determine the number of bits of GTOffset available */
1250         write_c0_gtoffset(0xffffffff);
1251         back_to_back_c0_hazard();
1252         c->gtoffset_mask = read_c0_gtoffset();
1253         write_c0_gtoffset(0);
1254 }
1255
1256 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1257 {
1258         cpu_probe_guestctl0(c);
1259         if (cpu_has_guestctl1)
1260                 cpu_probe_guestctl1(c);
1261
1262         cpu_probe_gtoffset(c);
1263
1264         decode_guest_configs(c);
1265 }
1266
1267 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1268                 | MIPS_CPU_COUNTER)
1269
1270 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1271 {
1272         switch (c->processor_id & PRID_IMP_MASK) {
1273         case PRID_IMP_R2000:
1274                 c->cputype = CPU_R2000;
1275                 __cpu_name[cpu] = "R2000";
1276                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1277                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1278                              MIPS_CPU_NOFPUEX;
1279                 if (__cpu_has_fpu())
1280                         c->options |= MIPS_CPU_FPU;
1281                 c->tlbsize = 64;
1282                 break;
1283         case PRID_IMP_R3000:
1284                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1285                         if (cpu_has_confreg()) {
1286                                 c->cputype = CPU_R3081E;
1287                                 __cpu_name[cpu] = "R3081";
1288                         } else {
1289                                 c->cputype = CPU_R3000A;
1290                                 __cpu_name[cpu] = "R3000A";
1291                         }
1292                 } else {
1293                         c->cputype = CPU_R3000;
1294                         __cpu_name[cpu] = "R3000";
1295                 }
1296                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1297                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1298                              MIPS_CPU_NOFPUEX;
1299                 if (__cpu_has_fpu())
1300                         c->options |= MIPS_CPU_FPU;
1301                 c->tlbsize = 64;
1302                 break;
1303         case PRID_IMP_R4000:
1304                 if (read_c0_config() & CONF_SC) {
1305                         if ((c->processor_id & PRID_REV_MASK) >=
1306                             PRID_REV_R4400) {
1307                                 c->cputype = CPU_R4400PC;
1308                                 __cpu_name[cpu] = "R4400PC";
1309                         } else {
1310                                 c->cputype = CPU_R4000PC;
1311                                 __cpu_name[cpu] = "R4000PC";
1312                         }
1313                 } else {
1314                         int cca = read_c0_config() & CONF_CM_CMASK;
1315                         int mc;
1316
1317                         /*
1318                          * SC and MC versions can't be reliably told apart,
1319                          * but only the latter support coherent caching
1320                          * modes so assume the firmware has set the KSEG0
1321                          * coherency attribute reasonably (if uncached, we
1322                          * assume SC).
1323                          */
1324                         switch (cca) {
1325                         case CONF_CM_CACHABLE_CE:
1326                         case CONF_CM_CACHABLE_COW:
1327                         case CONF_CM_CACHABLE_CUW:
1328                                 mc = 1;
1329                                 break;
1330                         default:
1331                                 mc = 0;
1332                                 break;
1333                         }
1334                         if ((c->processor_id & PRID_REV_MASK) >=
1335                             PRID_REV_R4400) {
1336                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1337                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1338                         } else {
1339                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1340                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1341                         }
1342                 }
1343
1344                 set_isa(c, MIPS_CPU_ISA_III);
1345                 c->fpu_msk31 |= FPU_CSR_CONDX;
1346                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1347                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
1348                              MIPS_CPU_LLSC;
1349                 c->tlbsize = 48;
1350                 break;
1351         case PRID_IMP_VR41XX:
1352                 set_isa(c, MIPS_CPU_ISA_III);
1353                 c->fpu_msk31 |= FPU_CSR_CONDX;
1354                 c->options = R4K_OPTS;
1355                 c->tlbsize = 32;
1356                 switch (c->processor_id & 0xf0) {
1357                 case PRID_REV_VR4111:
1358                         c->cputype = CPU_VR4111;
1359                         __cpu_name[cpu] = "NEC VR4111";
1360                         break;
1361                 case PRID_REV_VR4121:
1362                         c->cputype = CPU_VR4121;
1363                         __cpu_name[cpu] = "NEC VR4121";
1364                         break;
1365                 case PRID_REV_VR4122:
1366                         if ((c->processor_id & 0xf) < 0x3) {
1367                                 c->cputype = CPU_VR4122;
1368                                 __cpu_name[cpu] = "NEC VR4122";
1369                         } else {
1370                                 c->cputype = CPU_VR4181A;
1371                                 __cpu_name[cpu] = "NEC VR4181A";
1372                         }
1373                         break;
1374                 case PRID_REV_VR4130:
1375                         if ((c->processor_id & 0xf) < 0x4) {
1376                                 c->cputype = CPU_VR4131;
1377                                 __cpu_name[cpu] = "NEC VR4131";
1378                         } else {
1379                                 c->cputype = CPU_VR4133;
1380                                 c->options |= MIPS_CPU_LLSC;
1381                                 __cpu_name[cpu] = "NEC VR4133";
1382                         }
1383                         break;
1384                 default:
1385                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1386                         c->cputype = CPU_VR41XX;
1387                         __cpu_name[cpu] = "NEC Vr41xx";
1388                         break;
1389                 }
1390                 break;
1391         case PRID_IMP_R4300:
1392                 c->cputype = CPU_R4300;
1393                 __cpu_name[cpu] = "R4300";
1394                 set_isa(c, MIPS_CPU_ISA_III);
1395                 c->fpu_msk31 |= FPU_CSR_CONDX;
1396                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1397                              MIPS_CPU_LLSC;
1398                 c->tlbsize = 32;
1399                 break;
1400         case PRID_IMP_R4600:
1401                 c->cputype = CPU_R4600;
1402                 __cpu_name[cpu] = "R4600";
1403                 set_isa(c, MIPS_CPU_ISA_III);
1404                 c->fpu_msk31 |= FPU_CSR_CONDX;
1405                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1406                              MIPS_CPU_LLSC;
1407                 c->tlbsize = 48;
1408                 break;
1409         #if 0
1410         case PRID_IMP_R4650:
1411                 /*
1412                  * This processor doesn't have an MMU, so it's not
1413                  * "real easy" to run Linux on it. It is left purely
1414                  * for documentation.  Commented out because it shares
1415                  * it's c0_prid id number with the TX3900.
1416                  */
1417                 c->cputype = CPU_R4650;
1418                 __cpu_name[cpu] = "R4650";
1419                 set_isa(c, MIPS_CPU_ISA_III);
1420                 c->fpu_msk31 |= FPU_CSR_CONDX;
1421                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1422                 c->tlbsize = 48;
1423                 break;
1424         #endif
1425         case PRID_IMP_TX39:
1426                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1427                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1428
1429                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1430                         c->cputype = CPU_TX3927;
1431                         __cpu_name[cpu] = "TX3927";
1432                         c->tlbsize = 64;
1433                 } else {
1434                         switch (c->processor_id & PRID_REV_MASK) {
1435                         case PRID_REV_TX3912:
1436                                 c->cputype = CPU_TX3912;
1437                                 __cpu_name[cpu] = "TX3912";
1438                                 c->tlbsize = 32;
1439                                 break;
1440                         case PRID_REV_TX3922:
1441                                 c->cputype = CPU_TX3922;
1442                                 __cpu_name[cpu] = "TX3922";
1443                                 c->tlbsize = 64;
1444                                 break;
1445                         }
1446                 }
1447                 break;
1448         case PRID_IMP_R4700:
1449                 c->cputype = CPU_R4700;
1450                 __cpu_name[cpu] = "R4700";
1451                 set_isa(c, MIPS_CPU_ISA_III);
1452                 c->fpu_msk31 |= FPU_CSR_CONDX;
1453                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1454                              MIPS_CPU_LLSC;
1455                 c->tlbsize = 48;
1456                 break;
1457         case PRID_IMP_TX49:
1458                 c->cputype = CPU_TX49XX;
1459                 __cpu_name[cpu] = "R49XX";
1460                 set_isa(c, MIPS_CPU_ISA_III);
1461                 c->fpu_msk31 |= FPU_CSR_CONDX;
1462                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1463                 if (!(c->processor_id & 0x08))
1464                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1465                 c->tlbsize = 48;
1466                 break;
1467         case PRID_IMP_R5000:
1468                 c->cputype = CPU_R5000;
1469                 __cpu_name[cpu] = "R5000";
1470                 set_isa(c, MIPS_CPU_ISA_IV);
1471                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1472                              MIPS_CPU_LLSC;
1473                 c->tlbsize = 48;
1474                 break;
1475         case PRID_IMP_R5432:
1476                 c->cputype = CPU_R5432;
1477                 __cpu_name[cpu] = "R5432";
1478                 set_isa(c, MIPS_CPU_ISA_IV);
1479                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1480                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1481                 c->tlbsize = 48;
1482                 break;
1483         case PRID_IMP_R5500:
1484                 c->cputype = CPU_R5500;
1485                 __cpu_name[cpu] = "R5500";
1486                 set_isa(c, MIPS_CPU_ISA_IV);
1487                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1488                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1489                 c->tlbsize = 48;
1490                 break;
1491         case PRID_IMP_NEVADA:
1492                 c->cputype = CPU_NEVADA;
1493                 __cpu_name[cpu] = "Nevada";
1494                 set_isa(c, MIPS_CPU_ISA_IV);
1495                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1496                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1497                 c->tlbsize = 48;
1498                 break;
1499         case PRID_IMP_RM7000:
1500                 c->cputype = CPU_RM7000;
1501                 __cpu_name[cpu] = "RM7000";
1502                 set_isa(c, MIPS_CPU_ISA_IV);
1503                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1504                              MIPS_CPU_LLSC;
1505                 /*
1506                  * Undocumented RM7000:  Bit 29 in the info register of
1507                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
1508                  * entries.
1509                  *
1510                  * 29      1 =>    64 entry JTLB
1511                  *         0 =>    48 entry JTLB
1512                  */
1513                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1514                 break;
1515         case PRID_IMP_R8000:
1516                 c->cputype = CPU_R8000;
1517                 __cpu_name[cpu] = "RM8000";
1518                 set_isa(c, MIPS_CPU_ISA_IV);
1519                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1520                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1521                              MIPS_CPU_LLSC;
1522                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
1523                 break;
1524         case PRID_IMP_R10000:
1525                 c->cputype = CPU_R10000;
1526                 __cpu_name[cpu] = "R10000";
1527                 set_isa(c, MIPS_CPU_ISA_IV);
1528                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1529                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1530                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1531                              MIPS_CPU_LLSC;
1532                 c->tlbsize = 64;
1533                 break;
1534         case PRID_IMP_R12000:
1535                 c->cputype = CPU_R12000;
1536                 __cpu_name[cpu] = "R12000";
1537                 set_isa(c, MIPS_CPU_ISA_IV);
1538                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1539                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1540                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1541                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1542                 c->tlbsize = 64;
1543                 break;
1544         case PRID_IMP_R14000:
1545                 if (((c->processor_id >> 4) & 0x0f) > 2) {
1546                         c->cputype = CPU_R16000;
1547                         __cpu_name[cpu] = "R16000";
1548                 } else {
1549                         c->cputype = CPU_R14000;
1550                         __cpu_name[cpu] = "R14000";
1551                 }
1552                 set_isa(c, MIPS_CPU_ISA_IV);
1553                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1554                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1555                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1556                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1557                 c->tlbsize = 64;
1558                 break;
1559         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1560                 switch (c->processor_id & PRID_REV_MASK) {
1561                 case PRID_REV_LOONGSON2E:
1562                         c->cputype = CPU_LOONGSON2;
1563                         __cpu_name[cpu] = "ICT Loongson-2";
1564                         set_elf_platform(cpu, "loongson2e");
1565                         set_isa(c, MIPS_CPU_ISA_III);
1566                         c->fpu_msk31 |= FPU_CSR_CONDX;
1567                         break;
1568                 case PRID_REV_LOONGSON2F:
1569                         c->cputype = CPU_LOONGSON2;
1570                         __cpu_name[cpu] = "ICT Loongson-2";
1571                         set_elf_platform(cpu, "loongson2f");
1572                         set_isa(c, MIPS_CPU_ISA_III);
1573                         c->fpu_msk31 |= FPU_CSR_CONDX;
1574                         break;
1575                 case PRID_REV_LOONGSON3A_R1:
1576                         c->cputype = CPU_LOONGSON3;
1577                         __cpu_name[cpu] = "ICT Loongson-3";
1578                         set_elf_platform(cpu, "loongson3a");
1579                         set_isa(c, MIPS_CPU_ISA_M64R1);
1580                         break;
1581                 case PRID_REV_LOONGSON3B_R1:
1582                 case PRID_REV_LOONGSON3B_R2:
1583                         c->cputype = CPU_LOONGSON3;
1584                         __cpu_name[cpu] = "ICT Loongson-3";
1585                         set_elf_platform(cpu, "loongson3b");
1586                         set_isa(c, MIPS_CPU_ISA_M64R1);
1587                         break;
1588                 }
1589
1590                 c->options = R4K_OPTS |
1591                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1592                              MIPS_CPU_32FPR;
1593                 c->tlbsize = 64;
1594                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1595                 break;
1596         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1597                 decode_configs(c);
1598
1599                 c->cputype = CPU_LOONGSON1;
1600
1601                 switch (c->processor_id & PRID_REV_MASK) {
1602                 case PRID_REV_LOONGSON1B:
1603                         __cpu_name[cpu] = "Loongson 1B";
1604                         break;
1605                 }
1606
1607                 break;
1608         }
1609 }
1610
1611 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1612 {
1613         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1614         switch (c->processor_id & PRID_IMP_MASK) {
1615         case PRID_IMP_QEMU_GENERIC:
1616                 c->writecombine = _CACHE_UNCACHED;
1617                 c->cputype = CPU_QEMU_GENERIC;
1618                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1619                 break;
1620         case PRID_IMP_4KC:
1621                 c->cputype = CPU_4KC;
1622                 c->writecombine = _CACHE_UNCACHED;
1623                 __cpu_name[cpu] = "MIPS 4Kc";
1624                 break;
1625         case PRID_IMP_4KEC:
1626         case PRID_IMP_4KECR2:
1627                 c->cputype = CPU_4KEC;
1628                 c->writecombine = _CACHE_UNCACHED;
1629                 __cpu_name[cpu] = "MIPS 4KEc";
1630                 break;
1631         case PRID_IMP_4KSC:
1632         case PRID_IMP_4KSD:
1633                 c->cputype = CPU_4KSC;
1634                 c->writecombine = _CACHE_UNCACHED;
1635                 __cpu_name[cpu] = "MIPS 4KSc";
1636                 break;
1637         case PRID_IMP_5KC:
1638                 c->cputype = CPU_5KC;
1639                 c->writecombine = _CACHE_UNCACHED;
1640                 __cpu_name[cpu] = "MIPS 5Kc";
1641                 break;
1642         case PRID_IMP_5KE:
1643                 c->cputype = CPU_5KE;
1644                 c->writecombine = _CACHE_UNCACHED;
1645                 __cpu_name[cpu] = "MIPS 5KE";
1646                 break;
1647         case PRID_IMP_20KC:
1648                 c->cputype = CPU_20KC;
1649                 c->writecombine = _CACHE_UNCACHED;
1650                 __cpu_name[cpu] = "MIPS 20Kc";
1651                 break;
1652         case PRID_IMP_24K:
1653                 c->cputype = CPU_24K;
1654                 c->writecombine = _CACHE_UNCACHED;
1655                 __cpu_name[cpu] = "MIPS 24Kc";
1656                 break;
1657         case PRID_IMP_24KE:
1658                 c->cputype = CPU_24K;
1659                 c->writecombine = _CACHE_UNCACHED;
1660                 __cpu_name[cpu] = "MIPS 24KEc";
1661                 break;
1662         case PRID_IMP_25KF:
1663                 c->cputype = CPU_25KF;
1664                 c->writecombine = _CACHE_UNCACHED;
1665                 __cpu_name[cpu] = "MIPS 25Kc";
1666                 break;
1667         case PRID_IMP_34K:
1668                 c->cputype = CPU_34K;
1669                 c->writecombine = _CACHE_UNCACHED;
1670                 __cpu_name[cpu] = "MIPS 34Kc";
1671                 cpu_set_mt_per_tc_perf(c);
1672                 break;
1673         case PRID_IMP_74K:
1674                 c->cputype = CPU_74K;
1675                 c->writecombine = _CACHE_UNCACHED;
1676                 __cpu_name[cpu] = "MIPS 74Kc";
1677                 break;
1678         case PRID_IMP_M14KC:
1679                 c->cputype = CPU_M14KC;
1680                 c->writecombine = _CACHE_UNCACHED;
1681                 __cpu_name[cpu] = "MIPS M14Kc";
1682                 break;
1683         case PRID_IMP_M14KEC:
1684                 c->cputype = CPU_M14KEC;
1685                 c->writecombine = _CACHE_UNCACHED;
1686                 __cpu_name[cpu] = "MIPS M14KEc";
1687                 break;
1688         case PRID_IMP_1004K:
1689                 c->cputype = CPU_1004K;
1690                 c->writecombine = _CACHE_UNCACHED;
1691                 __cpu_name[cpu] = "MIPS 1004Kc";
1692                 cpu_set_mt_per_tc_perf(c);
1693                 break;
1694         case PRID_IMP_1074K:
1695                 c->cputype = CPU_1074K;
1696                 c->writecombine = _CACHE_UNCACHED;
1697                 __cpu_name[cpu] = "MIPS 1074Kc";
1698                 break;
1699         case PRID_IMP_INTERAPTIV_UP:
1700                 c->cputype = CPU_INTERAPTIV;
1701                 __cpu_name[cpu] = "MIPS interAptiv";
1702                 cpu_set_mt_per_tc_perf(c);
1703                 break;
1704         case PRID_IMP_INTERAPTIV_MP:
1705                 c->cputype = CPU_INTERAPTIV;
1706                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1707                 cpu_set_mt_per_tc_perf(c);
1708                 break;
1709         case PRID_IMP_PROAPTIV_UP:
1710                 c->cputype = CPU_PROAPTIV;
1711                 __cpu_name[cpu] = "MIPS proAptiv";
1712                 break;
1713         case PRID_IMP_PROAPTIV_MP:
1714                 c->cputype = CPU_PROAPTIV;
1715                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1716                 break;
1717         case PRID_IMP_P5600:
1718                 c->cputype = CPU_P5600;
1719                 __cpu_name[cpu] = "MIPS P5600";
1720                 break;
1721         case PRID_IMP_P6600:
1722                 c->cputype = CPU_P6600;
1723                 __cpu_name[cpu] = "MIPS P6600";
1724                 break;
1725         case PRID_IMP_I6400:
1726                 c->cputype = CPU_I6400;
1727                 __cpu_name[cpu] = "MIPS I6400";
1728                 break;
1729         case PRID_IMP_I6500:
1730                 c->cputype = CPU_I6500;
1731                 __cpu_name[cpu] = "MIPS I6500";
1732                 break;
1733         case PRID_IMP_M5150:
1734                 c->cputype = CPU_M5150;
1735                 __cpu_name[cpu] = "MIPS M5150";
1736                 break;
1737         case PRID_IMP_M6250:
1738                 c->cputype = CPU_M6250;
1739                 __cpu_name[cpu] = "MIPS M6250";
1740                 break;
1741         }
1742
1743         decode_configs(c);
1744
1745         spram_config();
1746
1747         switch (__get_cpu_type(c->cputype)) {
1748         case CPU_I6500:
1749                 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1750                 /* fall-through */
1751         case CPU_I6400:
1752                 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1753                 /* fall-through */
1754         default:
1755                 break;
1756         }
1757 }
1758
1759 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1760 {
1761         decode_configs(c);
1762         switch (c->processor_id & PRID_IMP_MASK) {
1763         case PRID_IMP_AU1_REV1:
1764         case PRID_IMP_AU1_REV2:
1765                 c->cputype = CPU_ALCHEMY;
1766                 switch ((c->processor_id >> 24) & 0xff) {
1767                 case 0:
1768                         __cpu_name[cpu] = "Au1000";
1769                         break;
1770                 case 1:
1771                         __cpu_name[cpu] = "Au1500";
1772                         break;
1773                 case 2:
1774                         __cpu_name[cpu] = "Au1100";
1775                         break;
1776                 case 3:
1777                         __cpu_name[cpu] = "Au1550";
1778                         break;
1779                 case 4:
1780                         __cpu_name[cpu] = "Au1200";
1781                         if ((c->processor_id & PRID_REV_MASK) == 2)
1782                                 __cpu_name[cpu] = "Au1250";
1783                         break;
1784                 case 5:
1785                         __cpu_name[cpu] = "Au1210";
1786                         break;
1787                 default:
1788                         __cpu_name[cpu] = "Au1xxx";
1789                         break;
1790                 }
1791                 break;
1792         }
1793 }
1794
1795 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1796 {
1797         decode_configs(c);
1798
1799         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1800         switch (c->processor_id & PRID_IMP_MASK) {
1801         case PRID_IMP_SB1:
1802                 c->cputype = CPU_SB1;
1803                 __cpu_name[cpu] = "SiByte SB1";
1804                 /* FPU in pass1 is known to have issues. */
1805                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1806                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1807                 break;
1808         case PRID_IMP_SB1A:
1809                 c->cputype = CPU_SB1A;
1810                 __cpu_name[cpu] = "SiByte SB1A";
1811                 break;
1812         }
1813 }
1814
1815 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1816 {
1817         decode_configs(c);
1818         switch (c->processor_id & PRID_IMP_MASK) {
1819         case PRID_IMP_SR71000:
1820                 c->cputype = CPU_SR71000;
1821                 __cpu_name[cpu] = "Sandcraft SR71000";
1822                 c->scache.ways = 8;
1823                 c->tlbsize = 64;
1824                 break;
1825         }
1826 }
1827
1828 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1829 {
1830         decode_configs(c);
1831         switch (c->processor_id & PRID_IMP_MASK) {
1832         case PRID_IMP_PR4450:
1833                 c->cputype = CPU_PR4450;
1834                 __cpu_name[cpu] = "Philips PR4450";
1835                 set_isa(c, MIPS_CPU_ISA_M32R1);
1836                 break;
1837         }
1838 }
1839
1840 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1841 {
1842         decode_configs(c);
1843         switch (c->processor_id & PRID_IMP_MASK) {
1844         case PRID_IMP_BMIPS32_REV4:
1845         case PRID_IMP_BMIPS32_REV8:
1846                 c->cputype = CPU_BMIPS32;
1847                 __cpu_name[cpu] = "Broadcom BMIPS32";
1848                 set_elf_platform(cpu, "bmips32");
1849                 break;
1850         case PRID_IMP_BMIPS3300:
1851         case PRID_IMP_BMIPS3300_ALT:
1852         case PRID_IMP_BMIPS3300_BUG:
1853                 c->cputype = CPU_BMIPS3300;
1854                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1855                 set_elf_platform(cpu, "bmips3300");
1856                 break;
1857         case PRID_IMP_BMIPS43XX: {
1858                 int rev = c->processor_id & PRID_REV_MASK;
1859
1860                 if (rev >= PRID_REV_BMIPS4380_LO &&
1861                                 rev <= PRID_REV_BMIPS4380_HI) {
1862                         c->cputype = CPU_BMIPS4380;
1863                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1864                         set_elf_platform(cpu, "bmips4380");
1865                         c->options |= MIPS_CPU_RIXI;
1866                 } else {
1867                         c->cputype = CPU_BMIPS4350;
1868                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1869                         set_elf_platform(cpu, "bmips4350");
1870                 }
1871                 break;
1872         }
1873         case PRID_IMP_BMIPS5000:
1874         case PRID_IMP_BMIPS5200:
1875                 c->cputype = CPU_BMIPS5000;
1876                 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1877                         __cpu_name[cpu] = "Broadcom BMIPS5200";
1878                 else
1879                         __cpu_name[cpu] = "Broadcom BMIPS5000";
1880                 set_elf_platform(cpu, "bmips5000");
1881                 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1882                 break;
1883         }
1884 }
1885
1886 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1887 {
1888         decode_configs(c);
1889         switch (c->processor_id & PRID_IMP_MASK) {
1890         case PRID_IMP_CAVIUM_CN38XX:
1891         case PRID_IMP_CAVIUM_CN31XX:
1892         case PRID_IMP_CAVIUM_CN30XX:
1893                 c->cputype = CPU_CAVIUM_OCTEON;
1894                 __cpu_name[cpu] = "Cavium Octeon";
1895                 goto platform;
1896         case PRID_IMP_CAVIUM_CN58XX:
1897         case PRID_IMP_CAVIUM_CN56XX:
1898         case PRID_IMP_CAVIUM_CN50XX:
1899         case PRID_IMP_CAVIUM_CN52XX:
1900                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1901                 __cpu_name[cpu] = "Cavium Octeon+";
1902 platform:
1903                 set_elf_platform(cpu, "octeon");
1904                 break;
1905         case PRID_IMP_CAVIUM_CN61XX:
1906         case PRID_IMP_CAVIUM_CN63XX:
1907         case PRID_IMP_CAVIUM_CN66XX:
1908         case PRID_IMP_CAVIUM_CN68XX:
1909         case PRID_IMP_CAVIUM_CNF71XX:
1910                 c->cputype = CPU_CAVIUM_OCTEON2;
1911                 __cpu_name[cpu] = "Cavium Octeon II";
1912                 set_elf_platform(cpu, "octeon2");
1913                 break;
1914         case PRID_IMP_CAVIUM_CN70XX:
1915         case PRID_IMP_CAVIUM_CN73XX:
1916         case PRID_IMP_CAVIUM_CNF75XX:
1917         case PRID_IMP_CAVIUM_CN78XX:
1918                 c->cputype = CPU_CAVIUM_OCTEON3;
1919                 __cpu_name[cpu] = "Cavium Octeon III";
1920                 set_elf_platform(cpu, "octeon3");
1921                 break;
1922         default:
1923                 printk(KERN_INFO "Unknown Octeon chip!\n");
1924                 c->cputype = CPU_UNKNOWN;
1925                 break;
1926         }
1927 }
1928
1929 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1930 {
1931         switch (c->processor_id & PRID_IMP_MASK) {
1932         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1933                 switch (c->processor_id & PRID_REV_MASK) {
1934                 case PRID_REV_LOONGSON3A_R2_0:
1935                 case PRID_REV_LOONGSON3A_R2_1:
1936                         c->cputype = CPU_LOONGSON3;
1937                         __cpu_name[cpu] = "ICT Loongson-3";
1938                         set_elf_platform(cpu, "loongson3a");
1939                         set_isa(c, MIPS_CPU_ISA_M64R2);
1940                         break;
1941                 case PRID_REV_LOONGSON3A_R3_0:
1942                 case PRID_REV_LOONGSON3A_R3_1:
1943                         c->cputype = CPU_LOONGSON3;
1944                         __cpu_name[cpu] = "ICT Loongson-3";
1945                         set_elf_platform(cpu, "loongson3a");
1946                         set_isa(c, MIPS_CPU_ISA_M64R2);
1947                         break;
1948                 }
1949
1950                 decode_configs(c);
1951                 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1952                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1953                 break;
1954         default:
1955                 panic("Unknown Loongson Processor ID!");
1956                 break;
1957         }
1958 }
1959
1960 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1961 {
1962         decode_configs(c);
1963         /* JZRISC does not implement the CP0 counter. */
1964         c->options &= ~MIPS_CPU_COUNTER;
1965         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1966         switch (c->processor_id & PRID_IMP_MASK) {
1967         case PRID_IMP_JZRISC:
1968                 c->cputype = CPU_JZRISC;
1969                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1970                 __cpu_name[cpu] = "Ingenic JZRISC";
1971                 break;
1972         default:
1973                 panic("Unknown Ingenic Processor ID!");
1974                 break;
1975         }
1976 }
1977
1978 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1979 {
1980         decode_configs(c);
1981
1982         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1983                 c->cputype = CPU_ALCHEMY;
1984                 __cpu_name[cpu] = "Au1300";
1985                 /* following stuff is not for Alchemy */
1986                 return;
1987         }
1988
1989         c->options = (MIPS_CPU_TLB       |
1990                         MIPS_CPU_4KEX    |
1991                         MIPS_CPU_COUNTER |
1992                         MIPS_CPU_DIVEC   |
1993                         MIPS_CPU_WATCH   |
1994                         MIPS_CPU_EJTAG   |
1995                         MIPS_CPU_LLSC);
1996
1997         switch (c->processor_id & PRID_IMP_MASK) {
1998         case PRID_IMP_NETLOGIC_XLP2XX:
1999         case PRID_IMP_NETLOGIC_XLP9XX:
2000         case PRID_IMP_NETLOGIC_XLP5XX:
2001                 c->cputype = CPU_XLP;
2002                 __cpu_name[cpu] = "Broadcom XLPII";
2003                 break;
2004
2005         case PRID_IMP_NETLOGIC_XLP8XX:
2006         case PRID_IMP_NETLOGIC_XLP3XX:
2007                 c->cputype = CPU_XLP;
2008                 __cpu_name[cpu] = "Netlogic XLP";
2009                 break;
2010
2011         case PRID_IMP_NETLOGIC_XLR732:
2012         case PRID_IMP_NETLOGIC_XLR716:
2013         case PRID_IMP_NETLOGIC_XLR532:
2014         case PRID_IMP_NETLOGIC_XLR308:
2015         case PRID_IMP_NETLOGIC_XLR532C:
2016         case PRID_IMP_NETLOGIC_XLR516C:
2017         case PRID_IMP_NETLOGIC_XLR508C:
2018         case PRID_IMP_NETLOGIC_XLR308C:
2019                 c->cputype = CPU_XLR;
2020                 __cpu_name[cpu] = "Netlogic XLR";
2021                 break;
2022
2023         case PRID_IMP_NETLOGIC_XLS608:
2024         case PRID_IMP_NETLOGIC_XLS408:
2025         case PRID_IMP_NETLOGIC_XLS404:
2026         case PRID_IMP_NETLOGIC_XLS208:
2027         case PRID_IMP_NETLOGIC_XLS204:
2028         case PRID_IMP_NETLOGIC_XLS108:
2029         case PRID_IMP_NETLOGIC_XLS104:
2030         case PRID_IMP_NETLOGIC_XLS616B:
2031         case PRID_IMP_NETLOGIC_XLS608B:
2032         case PRID_IMP_NETLOGIC_XLS416B:
2033         case PRID_IMP_NETLOGIC_XLS412B:
2034         case PRID_IMP_NETLOGIC_XLS408B:
2035         case PRID_IMP_NETLOGIC_XLS404B:
2036                 c->cputype = CPU_XLR;
2037                 __cpu_name[cpu] = "Netlogic XLS";
2038                 break;
2039
2040         default:
2041                 pr_info("Unknown Netlogic chip id [%02x]!\n",
2042                        c->processor_id);
2043                 c->cputype = CPU_XLR;
2044                 break;
2045         }
2046
2047         if (c->cputype == CPU_XLP) {
2048                 set_isa(c, MIPS_CPU_ISA_M64R2);
2049                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2050                 /* This will be updated again after all threads are woken up */
2051                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2052         } else {
2053                 set_isa(c, MIPS_CPU_ISA_M64R1);
2054                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2055         }
2056         c->kscratch_mask = 0xf;
2057 }
2058
2059 #ifdef CONFIG_64BIT
2060 /* For use by uaccess.h */
2061 u64 __ua_limit;
2062 EXPORT_SYMBOL(__ua_limit);
2063 #endif
2064
2065 const char *__cpu_name[NR_CPUS];
2066 const char *__elf_platform;
2067
2068 void cpu_probe(void)
2069 {
2070         struct cpuinfo_mips *c = &current_cpu_data;
2071         unsigned int cpu = smp_processor_id();
2072
2073         /*
2074          * Set a default elf platform, cpu probe may later
2075          * overwrite it with a more precise value
2076          */
2077         set_elf_platform(cpu, "mips");
2078
2079         c->processor_id = PRID_IMP_UNKNOWN;
2080         c->fpu_id       = FPIR_IMP_NONE;
2081         c->cputype      = CPU_UNKNOWN;
2082         c->writecombine = _CACHE_UNCACHED;
2083
2084         c->fpu_csr31    = FPU_CSR_RN;
2085         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2086
2087         c->processor_id = read_c0_prid();
2088         switch (c->processor_id & PRID_COMP_MASK) {
2089         case PRID_COMP_LEGACY:
2090                 cpu_probe_legacy(c, cpu);
2091                 break;
2092         case PRID_COMP_MIPS:
2093                 cpu_probe_mips(c, cpu);
2094                 break;
2095         case PRID_COMP_ALCHEMY:
2096                 cpu_probe_alchemy(c, cpu);
2097                 break;
2098         case PRID_COMP_SIBYTE:
2099                 cpu_probe_sibyte(c, cpu);
2100                 break;
2101         case PRID_COMP_BROADCOM:
2102                 cpu_probe_broadcom(c, cpu);
2103                 break;
2104         case PRID_COMP_SANDCRAFT:
2105                 cpu_probe_sandcraft(c, cpu);
2106                 break;
2107         case PRID_COMP_NXP:
2108                 cpu_probe_nxp(c, cpu);
2109                 break;
2110         case PRID_COMP_CAVIUM:
2111                 cpu_probe_cavium(c, cpu);
2112                 break;
2113         case PRID_COMP_LOONGSON:
2114                 cpu_probe_loongson(c, cpu);
2115                 break;
2116         case PRID_COMP_INGENIC_D0:
2117         case PRID_COMP_INGENIC_D1:
2118         case PRID_COMP_INGENIC_E1:
2119                 cpu_probe_ingenic(c, cpu);
2120                 break;
2121         case PRID_COMP_NETLOGIC:
2122                 cpu_probe_netlogic(c, cpu);
2123                 break;
2124         }
2125
2126         BUG_ON(!__cpu_name[cpu]);
2127         BUG_ON(c->cputype == CPU_UNKNOWN);
2128
2129         /*
2130          * Platform code can force the cpu type to optimize code
2131          * generation. In that case be sure the cpu type is correctly
2132          * manually setup otherwise it could trigger some nasty bugs.
2133          */
2134         BUG_ON(current_cpu_type() != c->cputype);
2135
2136         if (cpu_has_rixi) {
2137                 /* Enable the RIXI exceptions */
2138                 set_c0_pagegrain(PG_IEC);
2139                 back_to_back_c0_hazard();
2140                 /* Verify the IEC bit is set */
2141                 if (read_c0_pagegrain() & PG_IEC)
2142                         c->options |= MIPS_CPU_RIXIEX;
2143         }
2144
2145         if (mips_fpu_disabled)
2146                 c->options &= ~MIPS_CPU_FPU;
2147
2148         if (mips_dsp_disabled)
2149                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2150
2151         if (mips_htw_disabled) {
2152                 c->options &= ~MIPS_CPU_HTW;
2153                 write_c0_pwctl(read_c0_pwctl() &
2154                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2155         }
2156
2157         if (c->options & MIPS_CPU_FPU)
2158                 cpu_set_fpu_opts(c);
2159         else
2160                 cpu_set_nofpu_opts(c);
2161
2162         if (cpu_has_bp_ghist)
2163                 write_c0_r10k_diag(read_c0_r10k_diag() |
2164                                    R10K_DIAG_E_GHIST);
2165
2166         if (cpu_has_mips_r2_r6) {
2167                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2168                 /* R2 has Performance Counter Interrupt indicator */
2169                 c->options |= MIPS_CPU_PCI;
2170         }
2171         else
2172                 c->srsets = 1;
2173
2174         if (cpu_has_mips_r6)
2175                 elf_hwcap |= HWCAP_MIPS_R6;
2176
2177         if (cpu_has_msa) {
2178                 c->msa_id = cpu_get_msa_id();
2179                 WARN(c->msa_id & MSA_IR_WRPF,
2180                      "Vector register partitioning unimplemented!");
2181                 elf_hwcap |= HWCAP_MIPS_MSA;
2182         }
2183
2184         if (cpu_has_vz)
2185                 cpu_probe_vz(c);
2186
2187         cpu_probe_vmbits(c);
2188
2189 #ifdef CONFIG_64BIT
2190         if (cpu == 0)
2191                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2192 #endif
2193 }
2194
2195 void cpu_report(void)
2196 {
2197         struct cpuinfo_mips *c = &current_cpu_data;
2198
2199         pr_info("CPU%d revision is: %08x (%s)\n",
2200                 smp_processor_id(), c->processor_id, cpu_name_string());
2201         if (c->options & MIPS_CPU_FPU)
2202                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2203         if (cpu_has_msa)
2204                 pr_info("MSA revision is: %08x\n", c->msa_id);
2205 }
2206
2207 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2208 {
2209         /* Ensure the core number fits in the field */
2210         WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2211                            MIPS_GLOBALNUMBER_CLUSTER_SHF));
2212
2213         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2214         cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2215 }
2216
2217 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2218 {
2219         /* Ensure the core number fits in the field */
2220         WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2221
2222         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2223         cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2224 }
2225
2226 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2227 {
2228         /* Ensure the VP(E) ID fits in the field */
2229         WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2230
2231         /* Ensure we're not using VP(E)s without support */
2232         WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2233                 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2234
2235         cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2236         cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2237 }